[8dcfc0a] | 1 | /** |
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| 2 | * @file |
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| 3 | * |
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| 4 | * @brief Boot and system start code. |
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| 5 | */ |
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| 6 | |
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| 7 | /* |
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[13cf952] | 8 | * Copyright (c) 2008-2013 embedded brains GmbH. All rights reserved. |
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[8dcfc0a] | 9 | * |
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[4c622e5] | 10 | * embedded brains GmbH |
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| 11 | * Obere Lagerstr. 30 |
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| 12 | * 82178 Puchheim |
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| 13 | * Germany |
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| 14 | * <rtems@embedded-brains.de> |
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| 15 | * |
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| 16 | * The license and distribution terms for this file may be |
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| 17 | * found in the file LICENSE in this distribution or at |
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| 18 | * http://www.rtems.com/license/LICENSE. |
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[8dcfc0a] | 19 | */ |
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[091705c] | 20 | |
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| 21 | #include <rtems/asm.h> |
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[c193baad] | 22 | #include <rtems/system.h> |
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[39c8fdb] | 23 | #include <rtems/score/cpu.h> |
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[c193baad] | 24 | |
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[091705c] | 25 | #include <bspopts.h> |
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[4c622e5] | 26 | #include <bsp/irq.h> |
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[8dcfc0a] | 27 | #include <bsp/linker-symbols.h> |
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| 28 | |
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[4c622e5] | 29 | /* External symbols */ |
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| 30 | .extern bsp_reset |
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| 31 | .extern boot_card |
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| 32 | .extern bsp_start_hook_0 |
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| 33 | .extern bsp_start_hook_1 |
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[13cf952] | 34 | .extern _ARMV4_Exception_undef_default |
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| 35 | .extern _ARMV4_Exception_swi_default |
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| 36 | .extern _ARMV4_Exception_data_abort_default |
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| 37 | .extern _ARMV4_Exception_pref_abort_default |
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| 38 | .extern _ARMV4_Exception_reserved_default |
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| 39 | .extern _ARMV4_Exception_irq_default |
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| 40 | .extern _ARMV4_Exception_fiq_default |
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[04f399d] | 41 | .extern _ARMV7M_Exception_default |
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[8dcfc0a] | 42 | |
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[4c622e5] | 43 | /* Global symbols */ |
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| 44 | .globl _start |
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| 45 | .globl bsp_start_vector_table_begin |
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| 46 | .globl bsp_start_vector_table_end |
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| 47 | .globl bsp_start_vector_table_size |
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| 48 | .globl bsp_vector_table_size |
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[8dcfc0a] | 49 | |
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[4c622e5] | 50 | .section ".bsp_start_text", "ax" |
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[8dcfc0a] | 51 | |
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[4c622e5] | 52 | #if defined(ARM_MULTILIB_ARCH_V4) |
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[091705c] | 53 | |
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[4c622e5] | 54 | .arm |
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[9647f7fe] | 55 | |
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| 56 | /* |
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| 57 | * This is the exception vector table and the pointers to the default |
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| 58 | * exceptions handlers. |
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| 59 | */ |
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| 60 | |
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[4c622e5] | 61 | bsp_start_vector_table_begin: |
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[9647f7fe] | 62 | |
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| 63 | ldr pc, handler_addr_reset |
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| 64 | ldr pc, handler_addr_undef |
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| 65 | ldr pc, handler_addr_swi |
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| 66 | ldr pc, handler_addr_prefetch |
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| 67 | ldr pc, handler_addr_abort |
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| 68 | |
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| 69 | /* Program signature checked by boot loader */ |
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| 70 | .word 0xb8a06f58 |
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| 71 | |
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| 72 | ldr pc, handler_addr_irq |
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| 73 | ldr pc, handler_addr_fiq |
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| 74 | |
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| 75 | handler_addr_reset: |
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| 76 | |
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[091705c] | 77 | #ifdef BSP_START_RESET_VECTOR |
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| 78 | .word BSP_START_RESET_VECTOR |
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| 79 | #else |
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[a3579d3b] | 80 | .word _start |
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[091705c] | 81 | #endif |
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[9647f7fe] | 82 | |
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| 83 | handler_addr_undef: |
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| 84 | |
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[13cf952] | 85 | .word _ARMV4_Exception_undef_default |
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[9647f7fe] | 86 | |
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| 87 | handler_addr_swi: |
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| 88 | |
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[13cf952] | 89 | .word _ARMV4_Exception_swi_default |
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[9647f7fe] | 90 | |
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| 91 | handler_addr_prefetch: |
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| 92 | |
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[13cf952] | 93 | .word _ARMV4_Exception_data_abort_default |
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[9647f7fe] | 94 | |
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| 95 | handler_addr_abort: |
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| 96 | |
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[13cf952] | 97 | .word _ARMV4_Exception_pref_abort_default |
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[9647f7fe] | 98 | |
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| 99 | handler_addr_reserved: |
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| 100 | |
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[13cf952] | 101 | .word _ARMV4_Exception_reserved_default |
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[9647f7fe] | 102 | |
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| 103 | handler_addr_irq: |
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| 104 | |
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[13cf952] | 105 | .word _ARMV4_Exception_irq_default |
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[9647f7fe] | 106 | |
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| 107 | handler_addr_fiq: |
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| 108 | |
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[13cf952] | 109 | .word _ARMV4_Exception_fiq_default |
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[9647f7fe] | 110 | |
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[4c622e5] | 111 | bsp_start_vector_table_end: |
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| 112 | |
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[8dcfc0a] | 113 | /* Start entry */ |
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| 114 | |
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[a3579d3b] | 115 | _start: |
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[8dcfc0a] | 116 | |
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[091705c] | 117 | /* |
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| 118 | * We do not save the context since we do not return to the boot |
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| 119 | * loader. |
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| 120 | */ |
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[8dcfc0a] | 121 | |
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[091705c] | 122 | /* |
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| 123 | * Set SVC mode, disable interrupts and enable ARM instructions. |
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| 124 | */ |
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[39c8fdb] | 125 | mov r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F) |
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[8dcfc0a] | 126 | msr cpsr, r0 |
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| 127 | |
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[091705c] | 128 | /* Initialize stack pointer registers for the various modes */ |
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[8dcfc0a] | 129 | |
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[091705c] | 130 | /* Enter IRQ mode and set up the IRQ stack pointer */ |
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[39c8fdb] | 131 | mov r0, #(ARM_PSR_M_IRQ | ARM_PSR_I | ARM_PSR_F) |
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[8dcfc0a] | 132 | msr cpsr, r0 |
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[7ae2775] | 133 | ldr sp, =bsp_stack_irq_end |
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[8dcfc0a] | 134 | |
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[091705c] | 135 | /* Enter FIQ mode and set up the FIQ stack pointer */ |
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[39c8fdb] | 136 | mov r0, #(ARM_PSR_M_FIQ | ARM_PSR_I | ARM_PSR_F) |
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[8dcfc0a] | 137 | msr cpsr, r0 |
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[7ae2775] | 138 | ldr sp, =bsp_stack_fiq_end |
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[8dcfc0a] | 139 | |
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[091705c] | 140 | /* Enter ABT mode and set up the ABT stack pointer */ |
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[39c8fdb] | 141 | mov r0, #(ARM_PSR_M_ABT | ARM_PSR_I | ARM_PSR_F) |
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[8dcfc0a] | 142 | msr cpsr, r0 |
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[7ae2775] | 143 | ldr sp, =bsp_stack_abt_end |
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[8dcfc0a] | 144 | |
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[39c8fdb] | 145 | /* Enter UND mode and set up the UND stack pointer */ |
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| 146 | mov r0, #(ARM_PSR_M_UND | ARM_PSR_I | ARM_PSR_F) |
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[8dcfc0a] | 147 | msr cpsr, r0 |
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[39c8fdb] | 148 | ldr sp, =bsp_stack_und_end |
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[8dcfc0a] | 149 | |
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[091705c] | 150 | /* Enter SVC mode and set up the SVC stack pointer */ |
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[39c8fdb] | 151 | mov r0, #(ARM_PSR_M_SVC | ARM_PSR_I | ARM_PSR_F) |
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[8dcfc0a] | 152 | msr cpsr, r0 |
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[7ae2775] | 153 | ldr sp, =bsp_stack_svc_end |
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[8dcfc0a] | 154 | |
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[091705c] | 155 | /* Stay in SVC mode */ |
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[8dcfc0a] | 156 | |
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[cfd8d7a] | 157 | #ifdef ARM_MULTILIB_VFP_D32 |
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| 158 | /* Read CPACR */ |
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| 159 | mrc p15, 0, r0, c1, c0, 2 |
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| 160 | |
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| 161 | /* Enable CP10 and CP11 */ |
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| 162 | orr r0, r0, #(1 << 20) |
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| 163 | orr r0, r0, #(1 << 22) |
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| 164 | |
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| 165 | /* Clear ASEDIS and D32DIS */ |
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| 166 | bic r0, r0, #(3 << 30) |
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| 167 | |
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| 168 | /* Write CPACR */ |
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| 169 | mcr p15, 0, r0, c1, c0, 2 |
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| 170 | isb |
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| 171 | |
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| 172 | /* Enable FPU */ |
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| 173 | mov r0, #(1 << 30) |
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| 174 | vmsr FPEXC, r0 |
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| 175 | #endif |
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| 176 | |
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[091705c] | 177 | /* |
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| 178 | * Branch to start hook 0. |
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| 179 | * |
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[7a6f8d0] | 180 | * The previous code and parts of the start hook 0 may run with an |
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| 181 | * address offset. This implies that only branches relative to the |
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| 182 | * program counter are allowed. After the start hook 0 it is assumed |
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| 183 | * that the code can run at its intended position. Thus the link |
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| 184 | * register will be loaded with the absolute address. In THUMB mode |
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| 185 | * the start hook 0 must be within a 2kByte range due to the branch |
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| 186 | * instruction limitation. |
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[091705c] | 187 | */ |
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| 188 | |
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| 189 | ldr lr, =bsp_start_hook_0_done |
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[7a6f8d0] | 190 | #ifdef __thumb__ |
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| 191 | orr lr, #1 |
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| 192 | #endif |
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| 193 | |
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| 194 | SWITCH_FROM_ARM_TO_THUMB r0 |
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| 195 | |
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[091705c] | 196 | b bsp_start_hook_0 |
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[8dcfc0a] | 197 | |
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[091705c] | 198 | bsp_start_hook_0_done: |
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| 199 | |
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[7a6f8d0] | 200 | SWITCH_FROM_THUMB_TO_ARM |
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| 201 | |
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[091705c] | 202 | /* |
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[8dcfc0a] | 203 | * Initialize the exception vectors. This includes the exceptions |
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| 204 | * vectors and the pointers to the default exception handlers. |
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[091705c] | 205 | */ |
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[8dcfc0a] | 206 | |
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[c5d8d2dc] | 207 | ldr r0, =bsp_vector_table_begin |
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[4c622e5] | 208 | adr r1, bsp_start_vector_table_begin |
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[9ce65803] | 209 | cmp r0, r1 |
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| 210 | beq bsp_vector_table_copy_done |
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[8dcfc0a] | 211 | ldmia r1!, {r2-r9} |
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| 212 | stmia r0!, {r2-r9} |
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| 213 | ldmia r1!, {r2-r9} |
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| 214 | stmia r0!, {r2-r9} |
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| 215 | |
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[9ce65803] | 216 | bsp_vector_table_copy_done: |
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| 217 | |
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[7a6f8d0] | 218 | SWITCH_FROM_ARM_TO_THUMB r0 |
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| 219 | |
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[091705c] | 220 | /* Branch to start hook 1 */ |
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[8dcfc0a] | 221 | bl bsp_start_hook_1 |
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| 222 | |
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[091705c] | 223 | /* Branch to boot card */ |
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[7ae2775] | 224 | mov r0, #0 |
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[8dcfc0a] | 225 | bl boot_card |
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| 226 | |
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[305234f7] | 227 | twiddle: |
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| 228 | |
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[091705c] | 229 | /* Branch to reset function */ |
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[8dcfc0a] | 230 | bl bsp_reset |
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[39c8fdb] | 231 | |
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[305234f7] | 232 | b twiddle |
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[8dcfc0a] | 233 | |
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[4c622e5] | 234 | #elif defined(ARM_MULTILIB_ARCH_V7M) |
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[091705c] | 235 | |
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[4c622e5] | 236 | .syntax unified |
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[091705c] | 237 | |
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[4c622e5] | 238 | .extern bsp_stack_main_end |
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[091705c] | 239 | |
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[4c622e5] | 240 | .thumb |
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[091705c] | 241 | |
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[4c622e5] | 242 | bsp_start_vector_table_begin: |
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[091705c] | 243 | |
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[4c622e5] | 244 | .word bsp_stack_main_end |
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| 245 | .word _start /* Reset */ |
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[04f399d] | 246 | .word _ARMV7M_Exception_default /* NMI */ |
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| 247 | .word _ARMV7M_Exception_default /* Hard Fault */ |
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| 248 | .word _ARMV7M_Exception_default /* MPU Fault */ |
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| 249 | .word _ARMV7M_Exception_default /* Bus Fault */ |
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| 250 | .word _ARMV7M_Exception_default /* Usage Fault */ |
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| 251 | .word _ARMV7M_Exception_default /* Reserved */ |
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| 252 | .word _ARMV7M_Exception_default /* Reserved */ |
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| 253 | .word _ARMV7M_Exception_default /* Reserved */ |
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| 254 | .word _ARMV7M_Exception_default /* Reserved */ |
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| 255 | .word _ARMV7M_Exception_default /* SVC */ |
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| 256 | .word _ARMV7M_Exception_default /* Debug Monitor */ |
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| 257 | .word _ARMV7M_Exception_default /* Reserved */ |
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| 258 | .word _ARMV7M_Exception_default /* PendSV */ |
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| 259 | .word _ARMV7M_Exception_default /* SysTick */ |
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[4c622e5] | 260 | .rept BSP_INTERRUPT_VECTOR_MAX + 1 |
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[04f399d] | 261 | .word _ARMV7M_Exception_default /* IRQ */ |
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[4c622e5] | 262 | .endr |
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[091705c] | 263 | |
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[4c622e5] | 264 | bsp_start_vector_table_end: |
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[091705c] | 265 | |
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[4c622e5] | 266 | .thumb_func |
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[091705c] | 267 | |
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[4c622e5] | 268 | _start: |
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[091705c] | 269 | |
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[4c622e5] | 270 | ldr sp, =bsp_stack_main_end |
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| 271 | ldr lr, =bsp_start_hook_0_done + 1 |
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| 272 | b bsp_start_hook_0 |
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| 273 | |
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| 274 | bsp_start_hook_0_done: |
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| 275 | |
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| 276 | bl bsp_start_hook_1 |
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| 277 | movs r0, #0 |
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| 278 | bl boot_card |
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| 279 | |
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| 280 | twiddle: |
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| 281 | |
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| 282 | bl bsp_reset |
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| 283 | b twiddle |
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| 284 | |
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| 285 | #endif /* defined(ARM_MULTILIB_ARCH_V7M) */ |
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| 286 | |
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| 287 | .set bsp_start_vector_table_size, bsp_start_vector_table_end - bsp_start_vector_table_begin |
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| 288 | .set bsp_vector_table_size, bsp_start_vector_table_size |
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