source: rtems/c/src/lib/libbsp/arm/shared/lpc/network/lpc-ethernet.c @ d8134178

4.115
Last change on this file since d8134178 was f12ef239, checked in by Sebastian Huber <sebastian.huber@…>, on 01/09/13 at 15:25:37

bsps/arm: Fix LPC Ethernet driver initialization

  • Property mode set to 100644
File size: 45.5 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup lpc_eth
5 *
6 * @brief Ethernet driver.
7 */
8
9/*
10 * Copyright (c) 2009-2012 embedded brains GmbH.  All rights reserved.
11 *
12 *  embedded brains GmbH
13 *  Obere Lagerstr. 30
14 *  82178 Puchheim
15 *  Germany
16 *  <rtems@embedded-brains.de>
17 *
18 * The license and distribution terms for this file may be
19 * found in the file LICENSE in this distribution or at
20 * http://www.rtems.com/license/LICENSE.
21 */
22
23#define __INSIDE_RTEMS_BSD_TCPIP_STACK__ 1
24#define __BSD_VISIBLE 1
25
26#include <errno.h>
27#include <inttypes.h>
28#include <stdlib.h>
29#include <stdio.h>
30#include <string.h>
31#include <assert.h>
32
33#include <rtems.h>
34#include <rtems/rtems_bsdnet.h>
35#include <rtems/rtems_mii_ioctl.h>
36
37#include <sys/param.h>
38#include <sys/socket.h>
39#include <sys/sockio.h>
40#include <sys/mbuf.h>
41
42#include <net/if.h>
43#include <net/if_arp.h>
44#include <netinet/in.h>
45#include <netinet/if_ether.h>
46#include <netinet/in_systm.h>
47#include <netinet/ip.h>
48
49#include <bsp.h>
50#include <bsp/irq.h>
51#include <bsp/lpc-ethernet-config.h>
52#include <bsp/utility.h>
53
54#if MCLBYTES > (2 * 1024)
55  #error "MCLBYTES to large"
56#endif
57
58#ifdef LPC_ETH_CONFIG_USE_TRANSMIT_DMA
59  #define LPC_ETH_CONFIG_TX_BUF_SIZE sizeof(struct mbuf *)
60#else
61  #define LPC_ETH_CONFIG_TX_BUF_SIZE 1518U
62#endif
63
64#define DEFAULT_PHY 0
65#define WATCHDOG_TIMEOUT 5
66
67typedef struct {
68  uint32_t start;
69  uint32_t control;
70} lpc_eth_transfer_descriptor;
71
72typedef struct {
73  uint32_t info;
74  uint32_t hash_crc;
75} lpc_eth_receive_status;
76
77typedef struct {
78  uint32_t mac1;
79  uint32_t mac2;
80  uint32_t ipgt;
81  uint32_t ipgr;
82  uint32_t clrt;
83  uint32_t maxf;
84  uint32_t supp;
85  uint32_t test;
86  uint32_t mcfg;
87  uint32_t mcmd;
88  uint32_t madr;
89  uint32_t mwtd;
90  uint32_t mrdd;
91  uint32_t mind;
92  uint32_t reserved_0 [2];
93  uint32_t sa0;
94  uint32_t sa1;
95  uint32_t sa2;
96  uint32_t reserved_1 [45];
97  uint32_t command;
98  uint32_t status;
99  uint32_t rxdescriptor;
100  uint32_t rxstatus;
101  uint32_t rxdescriptornum;
102  uint32_t rxproduceindex;
103  uint32_t rxconsumeindex;
104  uint32_t txdescriptor;
105  uint32_t txstatus;
106  uint32_t txdescriptornum;
107  uint32_t txproduceindex;
108  uint32_t txconsumeindex;
109  uint32_t reserved_2 [10];
110  uint32_t tsv0;
111  uint32_t tsv1;
112  uint32_t rsv;
113  uint32_t reserved_3 [3];
114  uint32_t flowcontrolcnt;
115  uint32_t flowcontrolsts;
116  uint32_t reserved_4 [34];
117  uint32_t rxfilterctrl;
118  uint32_t rxfilterwolsts;
119  uint32_t rxfilterwolclr;
120  uint32_t reserved_5 [1];
121  uint32_t hashfilterl;
122  uint32_t hashfilterh;
123  uint32_t reserved_6 [882];
124  uint32_t intstatus;
125  uint32_t intenable;
126  uint32_t intclear;
127  uint32_t intset;
128  uint32_t reserved_7 [1];
129  uint32_t powerdown;
130} lpc_eth_controller;
131
132static volatile lpc_eth_controller *const lpc_eth =
133  (volatile lpc_eth_controller *) LPC_ETH_CONFIG_REG_BASE;
134
135/* ETH_RX_CTRL */
136
137#define ETH_RX_CTRL_SIZE_MASK 0x000007ffU
138#define ETH_RX_CTRL_INTERRUPT 0x80000000U
139
140/* ETH_RX_STAT */
141
142#define ETH_RX_STAT_RXSIZE_MASK 0x000007ffU
143#define ETH_RX_STAT_BYTES 0x00000100U
144#define ETH_RX_STAT_CONTROL_FRAME 0x00040000U
145#define ETH_RX_STAT_VLAN 0x00080000U
146#define ETH_RX_STAT_FAIL_FILTER 0x00100000U
147#define ETH_RX_STAT_MULTICAST 0x00200000U
148#define ETH_RX_STAT_BROADCAST 0x00400000U
149#define ETH_RX_STAT_CRC_ERROR 0x00800000U
150#define ETH_RX_STAT_SYMBOL_ERROR 0x01000000U
151#define ETH_RX_STAT_LENGTH_ERROR 0x02000000U
152#define ETH_RX_STAT_RANGE_ERROR 0x04000000U
153#define ETH_RX_STAT_ALIGNMENT_ERROR 0x08000000U
154#define ETH_RX_STAT_OVERRUN 0x10000000U
155#define ETH_RX_STAT_NO_DESCRIPTOR 0x20000000U
156#define ETH_RX_STAT_LAST_FLAG 0x40000000U
157#define ETH_RX_STAT_ERROR 0x80000000U
158
159/* ETH_TX_CTRL */
160
161#define ETH_TX_CTRL_SIZE_MASK 0x7ffU
162#define ETH_TX_CTRL_SIZE_SHIFT 0
163#define ETH_TX_CTRL_OVERRIDE 0x04000000U
164#define ETH_TX_CTRL_HUGE 0x08000000U
165#define ETH_TX_CTRL_PAD 0x10000000U
166#define ETH_TX_CTRL_CRC 0x20000000U
167#define ETH_TX_CTRL_LAST 0x40000000U
168#define ETH_TX_CTRL_INTERRUPT 0x80000000U
169
170/* ETH_TX_STAT */
171
172#define ETH_TX_STAT_COLLISION_COUNT_MASK 0x01e00000U
173#define ETH_TX_STAT_DEFER 0x02000000U
174#define ETH_TX_STAT_EXCESSIVE_DEFER 0x04000000U
175#define ETH_TX_STAT_EXCESSIVE_COLLISION 0x08000000U
176#define ETH_TX_STAT_LATE_COLLISION 0x10000000U
177#define ETH_TX_STAT_UNDERRUN 0x20000000U
178#define ETH_TX_STAT_NO_DESCRIPTOR 0x40000000U
179#define ETH_TX_STAT_ERROR 0x80000000U
180
181/* ETH_INT */
182
183#define ETH_INT_RX_OVERRUN 0x00000001U
184#define ETH_INT_RX_ERROR 0x00000002U
185#define ETH_INT_RX_FINISHED 0x00000004U
186#define ETH_INT_RX_DONE 0x00000008U
187#define ETH_INT_TX_UNDERRUN 0x00000010U
188#define ETH_INT_TX_ERROR 0x00000020U
189#define ETH_INT_TX_FINISHED 0x00000040U
190#define ETH_INT_TX_DONE 0x00000080U
191#define ETH_INT_SOFT 0x00001000U
192#define ETH_INT_WAKEUP 0x00002000U
193
194/* ETH_RX_FIL_CTRL */
195
196#define ETH_RX_FIL_CTRL_ACCEPT_UNICAST 0x00000001U
197#define ETH_RX_FIL_CTRL_ACCEPT_BROADCAST 0x00000002U
198#define ETH_RX_FIL_CTRL_ACCEPT_MULTICAST 0x00000004U
199#define ETH_RX_FIL_CTRL_ACCEPT_UNICAST_HASH 0x00000008U
200#define ETH_RX_FIL_CTRL_ACCEPT_MULTICAST_HASH 0x00000010U
201#define ETH_RX_FIL_CTRL_ACCEPT_PERFECT 0x00000020U
202#define ETH_RX_FIL_CTRL_MAGIC_PACKET_WOL 0x00001000U
203#define ETH_RX_FIL_CTRL_RX_FILTER_WOL 0x00002000U
204
205/* ETH_CMD */
206
207#define ETH_CMD_RX_ENABLE 0x00000001U
208#define ETH_CMD_TX_ENABLE 0x00000002U
209#define ETH_CMD_REG_RESET 0x00000008U
210#define ETH_CMD_TX_RESET 0x00000010U
211#define ETH_CMD_RX_RESET 0x00000020U
212#define ETH_CMD_PASS_RUNT_FRAME 0x00000040U
213#define ETH_CMD_PASS_RX_FILTER 0X00000080U
214#define ETH_CMD_TX_FLOW_CONTROL 0x00000100U
215#define ETH_CMD_RMII 0x00000200U
216#define ETH_CMD_FULL_DUPLEX 0x00000400U
217
218/* ETH_STAT */
219
220#define ETH_STAT_RX_ACTIVE 0x00000001U
221#define ETH_STAT_TX_ACTIVE 0x00000002U
222
223/* ETH_MAC2 */
224
225#define ETH_MAC2_FULL_DUPLEX BSP_BIT32(8)
226
227/* ETH_SUPP */
228
229#define ETH_SUPP_SPEED BSP_BIT32(8)
230
231/* ETH_MCFG */
232
233#define ETH_MCFG_CLOCK_SELECT(val) BSP_FLD32(val, 2, 4)
234
235/* ETH_MCMD */
236
237#define ETH_MCMD_READ BSP_BIT32(0)
238#define ETH_MCMD_SCAN BSP_BIT32(1)
239
240/* ETH_MADR */
241
242#define ETH_MADR_REG(val) BSP_FLD32(val, 0, 4)
243#define ETH_MADR_PHY(val) BSP_FLD32(val, 8, 12)
244
245/* ETH_MIND */
246
247#define ETH_MIND_BUSY BSP_BIT32(0)
248#define ETH_MIND_SCANNING BSP_BIT32(1)
249#define ETH_MIND_NOT_VALID BSP_BIT32(2)
250#define ETH_MIND_MII_LINK_FAIL BSP_BIT32(3)
251
252/* Events */
253
254#define LPC_ETH_EVENT_INITIALIZE RTEMS_EVENT_1
255
256#define LPC_ETH_EVENT_TXSTART RTEMS_EVENT_2
257
258#define LPC_ETH_EVENT_INTERRUPT RTEMS_EVENT_3
259
260#define LPC_ETH_EVENT_STOP RTEMS_EVENT_4
261
262/* Status */
263
264#define LPC_ETH_INTERRUPT_RECEIVE \
265  (ETH_INT_RX_ERROR | ETH_INT_RX_FINISHED | ETH_INT_RX_DONE)
266
267#define LPC_ETH_INTERRUPT_TRANSMIT \
268  (ETH_INT_TX_DONE | ETH_INT_TX_FINISHED | ETH_INT_TX_ERROR)
269
270#define LPC_ETH_RX_STAT_ERRORS \
271  (ETH_RX_STAT_CRC_ERROR \
272    | ETH_RX_STAT_SYMBOL_ERROR \
273    | ETH_RX_STAT_LENGTH_ERROR \
274    | ETH_RX_STAT_ALIGNMENT_ERROR \
275    | ETH_RX_STAT_OVERRUN \
276    | ETH_RX_STAT_NO_DESCRIPTOR)
277
278#define LPC_ETH_LAST_FRAGMENT_FLAGS \
279  (ETH_TX_CTRL_OVERRIDE \
280    | ETH_TX_CTRL_PAD \
281    | ETH_TX_CTRL_CRC \
282    | ETH_TX_CTRL_INTERRUPT \
283    | ETH_TX_CTRL_LAST)
284
285/* Debug */
286
287#ifdef DEBUG
288  #define LPC_ETH_PRINTF(...) printf(__VA_ARGS__)
289  #define LPC_ETH_PRINTK(...) printk(__VA_ARGS__)
290#else
291  #define LPC_ETH_PRINTF(...)
292  #define LPC_ETH_PRINTK(...)
293#endif
294
295typedef enum {
296  LPC_ETH_STATE_NOT_INITIALIZED = 0,
297  LPC_ETH_STATE_DOWN,
298  LPC_ETH_STATE_UP
299} lpc_eth_state;
300
301typedef struct {
302  struct arpcom arpcom;
303  lpc_eth_state state;
304  struct rtems_mdio_info mdio;
305  uint32_t anlpar;
306  rtems_id receive_task;
307  rtems_id transmit_task;
308  unsigned rx_unit_count;
309  unsigned tx_unit_count;
310  volatile lpc_eth_transfer_descriptor *rx_desc_table;
311  volatile lpc_eth_receive_status *rx_status_table;
312  struct mbuf **rx_mbuf_table;
313  volatile lpc_eth_transfer_descriptor *tx_desc_table;
314  volatile uint32_t *tx_status_table;
315  void *tx_buf_table;
316  unsigned received_frames;
317  unsigned receive_interrupts;
318  unsigned transmitted_frames;
319  unsigned transmit_interrupts;
320  unsigned receive_drop_errors;
321  unsigned receive_overrun_errors;
322  unsigned receive_fragment_errors;
323  unsigned receive_crc_errors;
324  unsigned receive_symbol_errors;
325  unsigned receive_length_errors;
326  unsigned receive_alignment_errors;
327  unsigned receive_no_descriptor_errors;
328  unsigned receive_fatal_errors;
329  unsigned transmit_underrun_errors;
330  unsigned transmit_late_collision_errors;
331  unsigned transmit_excessive_collision_errors;
332  unsigned transmit_excessive_defer_errors;
333  unsigned transmit_no_descriptor_errors;
334  unsigned transmit_overflow_errors;
335  unsigned transmit_fatal_errors;
336  uint32_t phy_id;
337  rtems_vector_number interrupt_number;
338  rtems_id control_task;
339} lpc_eth_driver_entry;
340
341static lpc_eth_driver_entry lpc_eth_driver_data;
342
343static void lpc_eth_control_request_complete(const lpc_eth_driver_entry *e)
344{
345  rtems_status_code sc = rtems_event_transient_send(e->control_task);
346  assert(sc == RTEMS_SUCCESSFUL);
347}
348
349static void lpc_eth_control_request(
350  lpc_eth_driver_entry *e,
351  rtems_id task,
352  rtems_event_set event
353)
354{
355  rtems_status_code sc = RTEMS_SUCCESSFUL;
356  uint32_t nest_count = 0;
357
358  e->control_task = rtems_task_self();
359
360  sc = rtems_bsdnet_event_send(task, event);
361  assert(sc == RTEMS_SUCCESSFUL);
362
363  nest_count = rtems_bsdnet_semaphore_release_recursive();
364  sc = rtems_event_transient_receive(RTEMS_WAIT, RTEMS_NO_TIMEOUT);
365  assert(sc == RTEMS_SUCCESSFUL);
366  rtems_bsdnet_semaphore_obtain_recursive(nest_count);
367
368  e->control_task = 0;
369}
370
371static inline uint32_t lpc_eth_increment(
372  uint32_t value,
373  uint32_t cycle
374)
375{
376  if (value < cycle) {
377    return ++value;
378  } else {
379    return 0;
380  }
381}
382
383static void lpc_eth_enable_promiscous_mode(bool enable)
384{
385  if (enable) {
386    lpc_eth->rxfilterctrl = ETH_RX_FIL_CTRL_ACCEPT_UNICAST
387      | ETH_RX_FIL_CTRL_ACCEPT_MULTICAST
388      | ETH_RX_FIL_CTRL_ACCEPT_BROADCAST;
389  } else {
390    lpc_eth->rxfilterctrl = ETH_RX_FIL_CTRL_ACCEPT_PERFECT
391      | ETH_RX_FIL_CTRL_ACCEPT_MULTICAST_HASH
392      | ETH_RX_FIL_CTRL_ACCEPT_BROADCAST;
393  }
394}
395
396static void lpc_eth_interrupt_handler(void *arg)
397{
398  lpc_eth_driver_entry *e = (lpc_eth_driver_entry *) arg;
399  rtems_event_set re = 0;
400  rtems_event_set te = 0;
401  uint32_t ie = 0;
402
403  /* Get interrupt status */
404  uint32_t im = lpc_eth->intenable;
405  uint32_t is = lpc_eth->intstatus & im;
406
407  /* Check receive interrupts */
408  if ((is & ETH_INT_RX_OVERRUN) != 0) {
409    re = LPC_ETH_EVENT_INITIALIZE;
410    ++e->receive_fatal_errors;
411  } else if ((is & LPC_ETH_INTERRUPT_RECEIVE) != 0) {
412    re = LPC_ETH_EVENT_INTERRUPT;
413    ie |= LPC_ETH_INTERRUPT_RECEIVE;
414  }
415
416  /* Send events to receive task */
417  if (re != 0) {
418    ++e->receive_interrupts;
419    (void) rtems_bsdnet_event_send(e->receive_task, re);
420  }
421
422  /* Check transmit interrupts */
423  if ((is & ETH_INT_TX_UNDERRUN) != 0) {
424    te = LPC_ETH_EVENT_INITIALIZE;
425    ++e->transmit_fatal_errors;
426  } else if ((is & LPC_ETH_INTERRUPT_TRANSMIT) != 0) {
427    te = LPC_ETH_EVENT_INTERRUPT;
428    ie |= LPC_ETH_INTERRUPT_TRANSMIT;
429  }
430
431  /* Send events to transmit task */
432  if (te != 0) {
433    ++e->transmit_interrupts;
434    (void) rtems_bsdnet_event_send(e->transmit_task, te);
435  }
436
437  LPC_ETH_PRINTK("interrupt: rx = 0x%08x, tx = 0x%08x\n", re, te);
438
439  /* Update interrupt mask */
440  lpc_eth->intenable = im & ~ie;
441
442  /* Clear interrupts */
443  lpc_eth->intclear = is;
444}
445
446static void lpc_eth_enable_receive_interrupts(void)
447{
448  rtems_interrupt_level level;
449
450  rtems_interrupt_disable(level);
451  lpc_eth->intenable |= LPC_ETH_INTERRUPT_RECEIVE;
452  rtems_interrupt_enable(level);
453}
454
455static void lpc_eth_disable_receive_interrupts(void)
456{
457  rtems_interrupt_level level;
458
459  rtems_interrupt_disable(level);
460  lpc_eth->intenable &= ~LPC_ETH_INTERRUPT_RECEIVE;
461  rtems_interrupt_enable(level);
462}
463
464static void lpc_eth_enable_transmit_interrupts(void)
465{
466  rtems_interrupt_level level;
467
468  rtems_interrupt_disable(level);
469  lpc_eth->intenable |= LPC_ETH_INTERRUPT_TRANSMIT;
470  rtems_interrupt_enable(level);
471}
472
473static void lpc_eth_disable_transmit_interrupts(void)
474{
475  rtems_interrupt_level level;
476
477  rtems_interrupt_disable(level);
478  lpc_eth->intenable &= ~LPC_ETH_INTERRUPT_TRANSMIT;
479  rtems_interrupt_enable(level);
480}
481
482#define LPC_ETH_RX_DATA_OFFSET 2
483
484static struct mbuf *lpc_eth_new_mbuf(struct ifnet *ifp, bool wait)
485{
486  struct mbuf *m = NULL;
487  int mw = wait ? M_WAIT : M_DONTWAIT;
488
489  MGETHDR(m, mw, MT_DATA);
490  if (m != NULL) {
491    MCLGET(m, mw);
492    if ((m->m_flags & M_EXT) != 0) {
493      /* Set receive interface */
494      m->m_pkthdr.rcvif = ifp;
495
496      /* Adjust by two bytes for proper IP header alignment */
497      m->m_data = mtod(m, char *) + LPC_ETH_RX_DATA_OFFSET;
498
499      return m;
500    } else {
501      m_free(m);
502    }
503  }
504
505  return NULL;
506}
507
508static bool lpc_eth_add_new_mbuf(
509  struct ifnet *ifp,
510  volatile lpc_eth_transfer_descriptor *desc,
511  struct mbuf **mbufs,
512  uint32_t i,
513  bool wait
514)
515{
516  /* New mbuf */
517  struct mbuf *m = lpc_eth_new_mbuf(ifp, wait);
518
519  /* Check mbuf */
520  if (m != NULL) {
521    /* Cache invalidate */
522    rtems_cache_invalidate_multiple_data_lines(
523      mtod(m, void *),
524      MCLBYTES - LPC_ETH_RX_DATA_OFFSET
525    );
526
527    /* Add mbuf to queue */
528    desc [i].start = mtod(m, uint32_t);
529    desc [i].control = (MCLBYTES - LPC_ETH_RX_DATA_OFFSET - 1)
530      | ETH_RX_CTRL_INTERRUPT;
531
532    /* Cache flush of descriptor  */
533    rtems_cache_flush_multiple_data_lines(
534      (void *) &desc [i],
535      sizeof(desc [0])
536    );
537
538    /* Add mbuf to table */
539    mbufs [i] = m;
540
541    return true;
542  } else {
543    return false;
544  }
545}
546
547static void lpc_eth_receive_task(void *arg)
548{
549  rtems_status_code sc = RTEMS_SUCCESSFUL;
550  rtems_event_set events = 0;
551  lpc_eth_driver_entry *const e = (lpc_eth_driver_entry *) arg;
552  struct ifnet *const ifp = &e->arpcom.ac_if;
553  volatile lpc_eth_transfer_descriptor *const desc = e->rx_desc_table;
554  volatile lpc_eth_receive_status *const status = e->rx_status_table;
555  struct mbuf **const mbufs = e->rx_mbuf_table;
556  uint32_t const index_max = e->rx_unit_count - 1;
557  uint32_t produce_index = 0;
558  uint32_t consume_index = 0;
559
560  LPC_ETH_PRINTF("%s\n", __func__);
561
562  /* Main event loop */
563  while (true) {
564    /* Wait for events */
565    sc = rtems_bsdnet_event_receive(
566      LPC_ETH_EVENT_INITIALIZE
567        | LPC_ETH_EVENT_STOP
568        | LPC_ETH_EVENT_INTERRUPT,
569      RTEMS_EVENT_ANY | RTEMS_WAIT,
570      RTEMS_NO_TIMEOUT,
571      &events
572    );
573    assert(sc == RTEMS_SUCCESSFUL);
574
575    LPC_ETH_PRINTF("rx: wake up: 0x%08" PRIx32 "\n", events);
576
577    /* Stop receiver? */
578    if ((events & LPC_ETH_EVENT_STOP) != 0) {
579      lpc_eth_control_request_complete(e);
580
581      /* Wait for events */
582      continue;
583    }
584
585    /* Initialize receiver? */
586    if ((events & LPC_ETH_EVENT_INITIALIZE) != 0) {
587      /* Disable receive interrupts */
588      lpc_eth_disable_receive_interrupts();
589
590      /* Disable receiver */
591      lpc_eth->command &= ~ETH_CMD_RX_ENABLE;
592
593      /* Wait for inactive status */
594      while ((lpc_eth->status & ETH_STAT_RX_ACTIVE) != 0) {
595        /* Wait */
596      }
597
598      /* Reset */
599      lpc_eth->command |= ETH_CMD_RX_RESET;
600
601      /* Clear receive interrupts */
602      lpc_eth->intclear = LPC_ETH_INTERRUPT_RECEIVE;
603
604      /* Move existing mbufs to the front */
605      consume_index = 0;
606      for (produce_index = 0; produce_index <= index_max; ++produce_index) {
607        if (mbufs [produce_index] != NULL) {
608          mbufs [consume_index] = mbufs [produce_index];
609          ++consume_index;
610        }
611      }
612
613      /* Fill receive queue */
614      for (
615        produce_index = consume_index;
616        produce_index <= index_max;
617        ++produce_index
618      ) {
619        lpc_eth_add_new_mbuf(ifp, desc, mbufs, produce_index, true);
620      }
621
622      /* Receive descriptor table */
623      lpc_eth->rxdescriptornum = index_max;
624      lpc_eth->rxdescriptor = (uint32_t) desc;
625      lpc_eth->rxstatus = (uint32_t) status;
626
627      /* Initialize indices */
628      produce_index = lpc_eth->rxproduceindex;
629      consume_index = lpc_eth->rxconsumeindex;
630
631      /* Enable receiver */
632      lpc_eth->command |= ETH_CMD_RX_ENABLE;
633
634      /* Enable receive interrupts */
635      lpc_eth_enable_receive_interrupts();
636
637      lpc_eth_control_request_complete(e);
638
639      /* Wait for events */
640      continue;
641    }
642
643    while (true) {
644      /* Clear receive interrupt status */
645      lpc_eth->intclear = LPC_ETH_INTERRUPT_RECEIVE;
646
647      /* Get current produce index */
648      produce_index = lpc_eth->rxproduceindex;
649
650      if (consume_index != produce_index) {
651        uint32_t stat = 0;
652
653        /* Fragment status */
654        rtems_cache_invalidate_multiple_data_lines(
655          (void *) &status [consume_index],
656          sizeof(status [0])
657        );
658        stat = status [consume_index].info;
659
660        if (
661          (stat & ETH_RX_STAT_LAST_FLAG) != 0
662            && (stat & LPC_ETH_RX_STAT_ERRORS) == 0
663        ) {
664          /* Received mbuf */
665          struct mbuf *m = mbufs [consume_index];
666
667          if (lpc_eth_add_new_mbuf(ifp, desc, mbufs, consume_index, false)) {
668            /* Ethernet header */
669            struct ether_header *eh = mtod(m, struct ether_header *);
670
671            /* Discard Ethernet header and CRC */
672            int sz = (int) (stat & ETH_RX_STAT_RXSIZE_MASK) + 1
673              - ETHER_HDR_LEN - ETHER_CRC_LEN;
674
675            /* Update mbuf */
676            m->m_len = sz;
677            m->m_pkthdr.len = sz;
678            m->m_data = mtod(m, char *) + ETHER_HDR_LEN;
679
680            LPC_ETH_PRINTF("rx: %02" PRIu32 ": %u\n", consume_index, sz);
681
682            /* Hand over */
683            ether_input(ifp, eh, m);
684
685            /* Increment received frames counter */
686            ++e->received_frames;
687          } else {
688            ++e->receive_drop_errors;
689          }
690        } else {
691          /* Update error counters */
692          if ((stat & ETH_RX_STAT_OVERRUN) != 0) {
693            ++e->receive_overrun_errors;
694          }
695          if ((stat & ETH_RX_STAT_LAST_FLAG) == 0) {
696            ++e->receive_fragment_errors;
697          }
698          if ((stat & ETH_RX_STAT_CRC_ERROR) != 0) {
699            ++e->receive_crc_errors;
700          }
701          if ((stat & ETH_RX_STAT_SYMBOL_ERROR) != 0) {
702            ++e->receive_symbol_errors;
703          }
704          if ((stat & ETH_RX_STAT_LENGTH_ERROR) != 0) {
705            ++e->receive_length_errors;
706          }
707          if ((stat & ETH_RX_STAT_ALIGNMENT_ERROR) != 0) {
708            ++e->receive_alignment_errors;
709          }
710          if ((stat & ETH_RX_STAT_NO_DESCRIPTOR) != 0) {
711            ++e->receive_no_descriptor_errors;
712          }
713        }
714
715        /* Increment and update consume index */
716        consume_index = lpc_eth_increment(consume_index, index_max);
717        lpc_eth->rxconsumeindex = consume_index;
718      } else {
719        /* Nothing to do, enable receive interrupts */
720        lpc_eth_enable_receive_interrupts();
721        break;
722      }
723    }
724  }
725}
726
727static struct mbuf *lpc_eth_next_fragment(
728  struct ifnet *ifp,
729  struct mbuf *m,
730  uint32_t *ctrl
731)
732{
733  struct mbuf *n = NULL;
734  int size = 0;
735
736  while (true) {
737    if (m == NULL) {
738      /* Dequeue first fragment of the next frame */
739      IF_DEQUEUE(&ifp->if_snd, m);
740
741      /* Empty queue? */
742      if (m == NULL) {
743        return m;
744      }
745    }
746
747    /* Get fragment size */
748    size = m->m_len;
749
750    if (size > 0) {
751      /* Now we have a not empty fragment */
752      break;
753    } else {
754      /* Discard empty fragments */
755      m = m_free(m);
756    }
757  }
758
759  /* Set fragment size */
760  *ctrl = (uint32_t) (size - 1);
761
762  /* Discard empty successive fragments */
763  n = m->m_next;
764  while (n != NULL && n->m_len <= 0) {
765    n = m_free(n);
766  }
767  m->m_next = n;
768
769  /* Is our fragment the last in the frame? */
770  if (n == NULL) {
771    *ctrl |= LPC_ETH_LAST_FRAGMENT_FLAGS;
772  }
773
774  return m;
775}
776
777static void lpc_eth_transmit_task(void *arg)
778{
779  rtems_status_code sc = RTEMS_SUCCESSFUL;
780  rtems_event_set events = 0;
781  lpc_eth_driver_entry *e = (lpc_eth_driver_entry *) arg;
782  struct ifnet *ifp = &e->arpcom.ac_if;
783  volatile lpc_eth_transfer_descriptor *const desc = e->tx_desc_table;
784  volatile uint32_t *const status = e->tx_status_table;
785  #ifdef LPC_ETH_CONFIG_USE_TRANSMIT_DMA
786    struct mbuf **const mbufs = e->tx_buf_table;
787  #else
788    char *const buf = e->tx_buf_table;
789  #endif
790  struct mbuf *m = NULL;
791  uint32_t const index_max = e->tx_unit_count - 1;
792  uint32_t produce_index = 0;
793  uint32_t consume_index = 0;
794  uint32_t ctrl = 0;
795  #ifndef LPC_ETH_CONFIG_USE_TRANSMIT_DMA
796    uint32_t frame_length = 0;
797    char *frame_buffer = NULL;
798  #endif
799
800  LPC_ETH_PRINTF("%s\n", __func__);
801
802  #ifndef LPC_ETH_CONFIG_USE_TRANSMIT_DMA
803    /* Initialize descriptor table */
804    for (produce_index = 0; produce_index <= index_max; ++produce_index) {
805      desc [produce_index].start =
806        (uint32_t) (buf + produce_index * LPC_ETH_CONFIG_TX_BUF_SIZE);
807    }
808  #endif
809
810  /* Main event loop */
811  while (true) {
812    /* Wait for events */
813    sc = rtems_bsdnet_event_receive(
814      LPC_ETH_EVENT_INITIALIZE
815        | LPC_ETH_EVENT_STOP
816        | LPC_ETH_EVENT_TXSTART
817        | LPC_ETH_EVENT_INTERRUPT,
818      RTEMS_EVENT_ANY | RTEMS_WAIT,
819      RTEMS_NO_TIMEOUT,
820      &events
821    );
822    assert(sc == RTEMS_SUCCESSFUL);
823
824    LPC_ETH_PRINTF("tx: wake up: 0x%08" PRIx32 "\n", events);
825
826    /* Stop transmitter? */
827    if ((events & LPC_ETH_EVENT_STOP) != 0) {
828      lpc_eth_control_request_complete(e);
829
830      /* Wait for events */
831      continue;
832    }
833
834    /* Initialize transmitter? */
835    if ((events & LPC_ETH_EVENT_INITIALIZE) != 0) {
836      /* Disable transmit interrupts */
837      lpc_eth_disable_transmit_interrupts();
838
839      /* Disable transmitter */
840      lpc_eth->command &= ~ETH_CMD_TX_ENABLE;
841
842      /* Wait for inactive status */
843      while ((lpc_eth->status & ETH_STAT_TX_ACTIVE) != 0) {
844        /* Wait */
845      }
846
847      /* Reset */
848      lpc_eth->command |= ETH_CMD_TX_RESET;
849
850      /* Clear transmit interrupts */
851      lpc_eth->intclear = LPC_ETH_INTERRUPT_TRANSMIT;
852
853      /* Transmit descriptors */
854      lpc_eth->txdescriptornum = index_max;
855      lpc_eth->txdescriptor = (uint32_t) desc;
856      lpc_eth->txstatus = (uint32_t) status;
857
858      #ifdef LPC_ETH_CONFIG_USE_TRANSMIT_DMA
859        /* Discard outstanding fragments (= data loss) */
860        for (produce_index = 0; produce_index <= index_max; ++produce_index) {
861          struct mbuf *victim = mbufs [produce_index];
862
863          if (victim != NULL) {
864            m_free(victim);
865            mbufs [produce_index] = NULL;
866          }
867        }
868      #endif
869
870      /* Initialize indices */
871      produce_index = lpc_eth->txproduceindex;
872      consume_index = lpc_eth->txconsumeindex;
873
874      #ifndef LPC_ETH_CONFIG_USE_TRANSMIT_DMA
875        /* Fresh frame length and buffer start */
876        frame_length = 0;
877        frame_buffer = (char *) desc [produce_index].start;
878      #endif
879
880      /* Enable transmitter */
881      lpc_eth->command |= ETH_CMD_TX_ENABLE;
882
883      lpc_eth_control_request_complete(e);
884    }
885
886    /* Free consumed fragments */
887    while (true) {
888      /* Save last known consume index */
889      uint32_t c = consume_index;
890
891      /* Clear transmit interrupt status */
892      lpc_eth->intclear = LPC_ETH_INTERRUPT_TRANSMIT;
893
894      /* Get new consume index */
895      consume_index = lpc_eth->txconsumeindex;
896
897      /* Nothing consumed in the meantime? */
898      if (c == consume_index) {
899        break;
900      }
901
902      while (c != consume_index) {
903        uint32_t s = status [c];
904
905        /* Update error counters */
906        if ((s & (ETH_TX_STAT_ERROR | ETH_TX_STAT_NO_DESCRIPTOR)) != 0) {
907          if ((s & ETH_TX_STAT_UNDERRUN) != 0) {
908            ++e->transmit_underrun_errors;
909          }
910          if ((s & ETH_TX_STAT_LATE_COLLISION) != 0) {
911            ++e->transmit_late_collision_errors;
912          }
913          if ((s & ETH_TX_STAT_EXCESSIVE_COLLISION) != 0) {
914            ++e->transmit_excessive_collision_errors;
915          }
916          if ((s & ETH_TX_STAT_EXCESSIVE_DEFER) != 0) {
917            ++e->transmit_excessive_defer_errors;
918          }
919          if ((s & ETH_TX_STAT_NO_DESCRIPTOR) != 0) {
920            ++e->transmit_no_descriptor_errors;
921          }
922        }
923
924        #ifdef LPC_ETH_CONFIG_USE_TRANSMIT_DMA
925          /* Release mbuf */
926          m_free(mbufs [c]);
927          mbufs [c] = NULL;
928        #endif
929
930        /* Next consume index */
931        c = lpc_eth_increment(c, index_max);
932      }
933    }
934
935    /* Transmit new fragments */
936    while (true) {
937      /* Compute next produce index */
938      uint32_t p = lpc_eth_increment(produce_index, index_max);
939
940      /* Get next fragment and control value */
941      m = lpc_eth_next_fragment(ifp, m, &ctrl);
942
943      /* Queue full? */
944      if (p == consume_index) {
945        LPC_ETH_PRINTF("tx: full queue: 0x%08x\n", m);
946
947        /* The queue is full, wait for transmit interrupt */
948        break;
949      }
950
951      /* New fragment? */
952      if (m != NULL) {
953        #ifdef LPC_ETH_CONFIG_USE_TRANSMIT_DMA
954          /* Set the transfer data */
955          rtems_cache_flush_multiple_data_lines(
956            mtod(m, const void *),
957            (size_t) m->m_len
958          );
959          desc [produce_index].start = mtod(m, uint32_t);
960          desc [produce_index].control = ctrl;
961          rtems_cache_flush_multiple_data_lines(
962            (void *) &desc [produce_index],
963            sizeof(desc [0])
964           );
965          mbufs [produce_index] = m;
966
967          LPC_ETH_PRINTF(
968            "tx: %02" PRIu32 ": %u %s\n",
969            produce_index, m->m_len,
970            (ctrl & ETH_TX_CTRL_LAST) != 0 ? "L" : ""
971          );
972
973          /* Next produce index */
974          produce_index = p;
975
976          /* Last fragment of a frame? */
977          if ((ctrl & ETH_TX_CTRL_LAST) != 0) {
978            /* Update the produce index */
979            lpc_eth->txproduceindex = produce_index;
980
981            /* Increment transmitted frames counter */
982            ++e->transmitted_frames;
983          }
984
985          /* Next fragment of the frame */
986          m = m->m_next;
987        #else
988          size_t fragment_length = (size_t) m->m_len;
989          void *fragment_start = mtod(m, void *);
990          uint32_t new_frame_length = frame_length + fragment_length;
991
992          /* Check buffer size */
993          if (new_frame_length > LPC_ETH_CONFIG_TX_BUF_SIZE) {
994            LPC_ETH_PRINTF("tx: overflow\n");
995
996            /* Discard overflow data */
997            new_frame_length = LPC_ETH_CONFIG_TX_BUF_SIZE;
998            fragment_length = new_frame_length - frame_length;
999
1000            /* Finalize frame */
1001            ctrl |= LPC_ETH_LAST_FRAGMENT_FLAGS;
1002
1003            /* Update error counter */
1004            ++e->transmit_overflow_errors;
1005          }
1006
1007          LPC_ETH_PRINTF(
1008            "tx: copy: %" PRIu32 "%s%s\n",
1009            fragment_length,
1010            (m->m_flags & M_EXT) != 0 ? ", E" : "",
1011            (m->m_flags & M_PKTHDR) != 0 ? ", H" : ""
1012          );
1013
1014          /* Copy fragment to buffer in Ethernet RAM */
1015          memcpy(frame_buffer, fragment_start, fragment_length);
1016
1017          if ((ctrl & ETH_TX_CTRL_LAST) != 0) {
1018            /* Finalize descriptor */
1019            desc [produce_index].control = (ctrl & ~ETH_TX_CTRL_SIZE_MASK)
1020              | (new_frame_length - 1);
1021
1022            LPC_ETH_PRINTF(
1023              "tx: %02" PRIu32 ": %" PRIu32 "\n",
1024              produce_index,
1025              new_frame_length
1026            );
1027
1028            /* Cache flush of data */
1029            rtems_cache_flush_multiple_data_lines(
1030              (const void *) desc [produce_index].start,
1031              new_frame_length
1032            );
1033
1034            /* Cache flush of descriptor  */
1035            rtems_cache_flush_multiple_data_lines(
1036              (void *) &desc [produce_index],
1037              sizeof(desc [0])
1038            );
1039
1040            /* Next produce index */
1041            produce_index = p;
1042
1043            /* Update the produce index */
1044            lpc_eth->txproduceindex = produce_index;
1045
1046            /* Fresh frame length and buffer start */
1047            frame_length = 0;
1048            frame_buffer = (char *) desc [produce_index].start;
1049
1050            /* Increment transmitted frames counter */
1051            ++e->transmitted_frames;
1052          } else {
1053            /* New frame length */
1054            frame_length = new_frame_length;
1055
1056            /* Update current frame buffer start */
1057            frame_buffer += fragment_length;
1058          }
1059
1060          /* Free mbuf and get next */
1061          m = m_free(m);
1062        #endif
1063      } else {
1064        /* Nothing to transmit */
1065        break;
1066      }
1067    }
1068
1069    /* No more fragments? */
1070    if (m == NULL) {
1071      /* Interface is now inactive */
1072      ifp->if_flags &= ~IFF_OACTIVE;
1073    } else {
1074      LPC_ETH_PRINTF("tx: enable interrupts\n");
1075
1076      /* Enable transmit interrupts */
1077      lpc_eth_enable_transmit_interrupts();
1078    }
1079  }
1080}
1081
1082static int lpc_eth_mdio_wait_for_not_busy(void)
1083{
1084  rtems_interval one_second = rtems_clock_get_ticks_per_second();
1085  rtems_interval i = 0;
1086
1087  while ((lpc_eth->mind & ETH_MIND_BUSY) != 0 && i < one_second) {
1088    rtems_task_wake_after(1);
1089    ++i;
1090  }
1091
1092  return i != one_second ? 0 : ETIMEDOUT;
1093}
1094
1095static uint32_t lpc_eth_mdio_read_anlpar(void)
1096{
1097  uint32_t madr = ETH_MADR_REG(MII_ANLPAR) | ETH_MADR_PHY(DEFAULT_PHY);
1098  uint32_t anlpar = 0;
1099  int eno = 0;
1100
1101  if (lpc_eth->madr != madr) {
1102    lpc_eth->madr = madr;
1103  }
1104
1105  if (lpc_eth->mcmd != ETH_MCMD_READ) {
1106    lpc_eth->mcmd = 0;
1107    lpc_eth->mcmd = ETH_MCMD_READ;
1108  }
1109
1110  eno = lpc_eth_mdio_wait_for_not_busy();
1111  if (eno == 0) {
1112    anlpar = lpc_eth->mrdd;
1113  }
1114
1115  /* Start next read */
1116  lpc_eth->mcmd = 0;
1117  lpc_eth->mcmd = ETH_MCMD_READ;
1118
1119  return anlpar;
1120}
1121
1122static int lpc_eth_mdio_read(
1123  int phy,
1124  void *arg __attribute__((unused)),
1125  unsigned reg,
1126  uint32_t *val
1127)
1128{
1129  int eno = 0;
1130
1131  if (phy == -1 || phy == 0) {
1132    lpc_eth->madr = ETH_MADR_REG(reg) | ETH_MADR_PHY(DEFAULT_PHY);
1133    lpc_eth->mcmd = 0;
1134    lpc_eth->mcmd = ETH_MCMD_READ;
1135    eno = lpc_eth_mdio_wait_for_not_busy();
1136
1137    if (eno == 0) {
1138      *val = lpc_eth->mrdd;
1139    }
1140  } else {
1141    eno = EINVAL;
1142  }
1143
1144  return eno;
1145}
1146
1147static int lpc_eth_mdio_write(
1148  int phy,
1149  void *arg __attribute__((unused)),
1150  unsigned reg,
1151  uint32_t val
1152)
1153{
1154  int eno = 0;
1155
1156  if (phy == -1 || phy == 0) {
1157    lpc_eth->madr = ETH_MADR_REG(reg) | ETH_MADR_PHY(DEFAULT_PHY);
1158    lpc_eth->mwtd = val;
1159    eno = lpc_eth_mdio_wait_for_not_busy();
1160  } else {
1161    eno = EINVAL;
1162  }
1163
1164  return eno;
1165}
1166
1167static int lpc_eth_phy_get_id(uint32_t *id)
1168{
1169  uint32_t id1 = 0;
1170  int eno = lpc_eth_mdio_read(DEFAULT_PHY, NULL, MII_PHYIDR1, &id1);
1171
1172  if (eno == 0) {
1173    uint32_t id2 = 0;
1174
1175    eno = lpc_eth_mdio_read(DEFAULT_PHY, NULL, MII_PHYIDR2, &id2);
1176    if (eno == 0) {
1177      *id = (id1 << 16) | (id2 & 0xfff0);
1178    }
1179  }
1180
1181  return eno;
1182}
1183
1184#define PHY_KSZ80X1RNL 0x221550
1185
1186typedef struct {
1187  unsigned reg;
1188  uint32_t set;
1189  uint32_t clear;
1190} lpc_eth_phy_action;
1191
1192static int lpc_eth_phy_set_and_clear(
1193  const lpc_eth_phy_action *actions,
1194  size_t n
1195)
1196{
1197  int eno = 0;
1198  size_t i;
1199
1200  for (i = 0; eno == 0 && i < n; ++i) {
1201    const lpc_eth_phy_action *action = &actions [i];
1202    uint32_t val;
1203
1204    eno = lpc_eth_mdio_read(DEFAULT_PHY, NULL, action->reg, &val);
1205    if (eno == 0) {
1206      val |= action->set;
1207      val &= ~action->clear;
1208      eno = lpc_eth_mdio_write(DEFAULT_PHY, NULL, action->reg, val);
1209    }
1210  }
1211
1212  return eno;
1213}
1214
1215static const lpc_eth_phy_action lpc_eth_phy_up_action_default [] = {
1216  { MII_BMCR, 0, BMCR_PDOWN },
1217  { MII_BMCR, BMCR_RESET, 0 },
1218  { MII_BMCR, BMCR_AUTOEN, 0 }
1219};
1220
1221static const lpc_eth_phy_action lpc_eth_phy_up_pre_action_KSZ80X1RNL [] = {
1222  /* Disable slow oscillator mode */
1223  { 0x11, 0, 0x10 }
1224};
1225
1226static const lpc_eth_phy_action lpc_eth_phy_up_post_action_KSZ80X1RNL [] = {
1227  /* Enable energy detect power down (EDPD) mode */
1228  { 0x18, 0x0800, 0 },
1229  /* Turn PLL of automatically in EDPD mode */
1230  { 0x10, 0x10, 0 }
1231};
1232
1233static int lpc_eth_phy_up(lpc_eth_driver_entry *e)
1234{
1235  int eno = lpc_eth_phy_get_id(&e->phy_id);
1236
1237  if (eno == 0) {
1238    switch (e->phy_id) {
1239      case PHY_KSZ80X1RNL:
1240        eno = lpc_eth_phy_set_and_clear(
1241          &lpc_eth_phy_up_pre_action_KSZ80X1RNL [0],
1242          RTEMS_ARRAY_SIZE(lpc_eth_phy_up_pre_action_KSZ80X1RNL)
1243        );
1244        break;
1245      case 0:
1246      case 0xfffffff0:
1247        eno = EIO;
1248        break;
1249      default:
1250        break;
1251    }
1252
1253    if (eno == 0) {
1254      eno = lpc_eth_phy_set_and_clear(
1255        &lpc_eth_phy_up_action_default [0],
1256        RTEMS_ARRAY_SIZE(lpc_eth_phy_up_action_default)
1257      );
1258    }
1259
1260    if (eno == 0) {
1261      switch (e->phy_id) {
1262        case PHY_KSZ80X1RNL:
1263          eno = lpc_eth_phy_set_and_clear(
1264            &lpc_eth_phy_up_post_action_KSZ80X1RNL [0],
1265            RTEMS_ARRAY_SIZE(lpc_eth_phy_up_post_action_KSZ80X1RNL)
1266          );
1267          break;
1268        default:
1269          break;
1270      }
1271    }
1272  } else {
1273    e->phy_id = 0;
1274  }
1275
1276  return eno;
1277}
1278
1279static const lpc_eth_phy_action lpc_eth_phy_down_action_default [] = {
1280  { MII_BMCR, BMCR_PDOWN, 0 }
1281};
1282
1283static const lpc_eth_phy_action lpc_eth_phy_down_post_action_KSZ80X1RNL [] = {
1284  /* Enable slow oscillator mode */
1285  { 0x11, 0x10, 0 }
1286};
1287
1288static void lpc_eth_phy_down(lpc_eth_driver_entry *e)
1289{
1290  int eno = lpc_eth_phy_set_and_clear(
1291    &lpc_eth_phy_down_action_default [0],
1292    RTEMS_ARRAY_SIZE(lpc_eth_phy_down_action_default)
1293  );
1294
1295  if (eno == 0) {
1296    switch (e->phy_id) {
1297      case PHY_KSZ80X1RNL:
1298        eno = lpc_eth_phy_set_and_clear(
1299          &lpc_eth_phy_down_post_action_KSZ80X1RNL [0],
1300          RTEMS_ARRAY_SIZE(lpc_eth_phy_down_post_action_KSZ80X1RNL)
1301        );
1302        break;
1303      default:
1304        break;
1305    }
1306  }
1307}
1308
1309static void lpc_eth_soft_reset(void)
1310{
1311  lpc_eth->command = 0x38;
1312  lpc_eth->mac1 = 0xcf00;
1313  lpc_eth->mac1 = 0x0;
1314}
1315
1316static int lpc_eth_up_or_down(lpc_eth_driver_entry *e, bool up)
1317{
1318  int eno = 0;
1319  rtems_status_code sc = RTEMS_SUCCESSFUL;
1320  struct ifnet *ifp = &e->arpcom.ac_if;
1321
1322  if (up && e->state == LPC_ETH_STATE_DOWN) {
1323
1324    lpc_eth_config_module_enable();
1325
1326    /* Enable RX/TX reset and disable soft reset */
1327    lpc_eth->mac1 = 0xf00;
1328
1329    /* Initialize PHY */
1330    lpc_eth->mcfg = ETH_MCFG_CLOCK_SELECT(0x7);
1331    eno = lpc_eth_phy_up(e);
1332
1333    if (eno == 0) {
1334      /*
1335       * We must have a valid external clock from the PHY at this point,
1336       * otherwise the system bus hangs and only a watchdog reset helps.
1337       */
1338      lpc_eth_soft_reset();
1339
1340      /* Reinitialize registers */
1341      lpc_eth->mac2 = 0x31;
1342      lpc_eth->ipgt = 0x15;
1343      lpc_eth->ipgr = 0x12;
1344      lpc_eth->clrt = 0x370f;
1345      lpc_eth->maxf = 0x0600;
1346      lpc_eth->supp = ETH_SUPP_SPEED;
1347      lpc_eth->test = 0;
1348      #ifdef LPC_ETH_CONFIG_RMII
1349        lpc_eth->command = 0x0600;
1350      #else
1351        lpc_eth->command = 0x0400;
1352      #endif
1353      lpc_eth->intenable = ETH_INT_RX_OVERRUN | ETH_INT_TX_UNDERRUN;
1354      lpc_eth->intclear = 0x30ff;
1355      lpc_eth->powerdown = 0;
1356
1357      /* MAC address */
1358      lpc_eth->sa0 = ((uint32_t) e->arpcom.ac_enaddr [5] << 8)
1359        | (uint32_t) e->arpcom.ac_enaddr [4];
1360      lpc_eth->sa1 = ((uint32_t) e->arpcom.ac_enaddr [3] << 8)
1361        | (uint32_t) e->arpcom.ac_enaddr [2];
1362      lpc_eth->sa2 = ((uint32_t) e->arpcom.ac_enaddr [1] << 8)
1363        | (uint32_t) e->arpcom.ac_enaddr [0];
1364
1365      /* Enable receiver */
1366      lpc_eth->mac1 = 0x03;
1367
1368      /* Initialize tasks */
1369      lpc_eth_control_request(e, e->receive_task, LPC_ETH_EVENT_INITIALIZE);
1370      lpc_eth_control_request(e, e->transmit_task, LPC_ETH_EVENT_INITIALIZE);
1371
1372      /* Install interrupt handler */
1373      sc = rtems_interrupt_handler_install(
1374        e->interrupt_number,
1375        "Ethernet",
1376        RTEMS_INTERRUPT_UNIQUE,
1377        lpc_eth_interrupt_handler,
1378        e
1379      );
1380      assert(sc == RTEMS_SUCCESSFUL);
1381
1382      /* Start watchdog timer */
1383      ifp->if_timer = 1;
1384
1385      /* Change state */
1386      e->state = LPC_ETH_STATE_UP;
1387    }
1388
1389    if (eno != 0) {
1390      ifp->if_flags &= ~IFF_UP;
1391    }
1392  } else if (!up && e->state == LPC_ETH_STATE_UP) {
1393    /* Remove interrupt handler */
1394    sc = rtems_interrupt_handler_remove(
1395      e->interrupt_number,
1396      lpc_eth_interrupt_handler,
1397      e
1398    );
1399    assert(sc == RTEMS_SUCCESSFUL);
1400
1401    /* Stop tasks */
1402    lpc_eth_control_request(e, e->receive_task, LPC_ETH_EVENT_STOP);
1403    lpc_eth_control_request(e, e->transmit_task, LPC_ETH_EVENT_STOP);
1404
1405    lpc_eth_soft_reset();
1406    lpc_eth_phy_down(e);
1407    lpc_eth_config_module_disable();
1408
1409    /* Stop watchdog timer */
1410    ifp->if_timer = 0;
1411
1412    /* Change state */
1413    e->state = LPC_ETH_STATE_DOWN;
1414  }
1415
1416  return eno;
1417}
1418
1419static void lpc_eth_interface_init(void *arg)
1420{
1421  /* Nothing to do */
1422}
1423
1424static void lpc_eth_interface_stats(lpc_eth_driver_entry *e)
1425{
1426  int eno = EIO;
1427  int media = 0;
1428
1429  if (e->state == LPC_ETH_STATE_UP) {
1430    media = IFM_MAKEWORD(0, 0, 0, 0);
1431    eno = rtems_mii_ioctl(&e->mdio, e, SIOCGIFMEDIA, &media);
1432  }
1433
1434  rtems_bsdnet_semaphore_release();
1435
1436  if (eno == 0) {
1437    rtems_ifmedia2str(media, NULL, 0);
1438    printf("\n");
1439  }
1440
1441  printf("received frames:                     %u\n", e->received_frames);
1442  printf("receive interrupts:                  %u\n", e->receive_interrupts);
1443  printf("transmitted frames:                  %u\n", e->transmitted_frames);
1444  printf("transmit interrupts:                 %u\n", e->transmit_interrupts);
1445  printf("receive drop errors:                 %u\n", e->receive_drop_errors);
1446  printf("receive overrun errors:              %u\n", e->receive_overrun_errors);
1447  printf("receive fragment errors:             %u\n", e->receive_fragment_errors);
1448  printf("receive CRC errors:                  %u\n", e->receive_crc_errors);
1449  printf("receive symbol errors:               %u\n", e->receive_symbol_errors);
1450  printf("receive length errors:               %u\n", e->receive_length_errors);
1451  printf("receive alignment errors:            %u\n", e->receive_alignment_errors);
1452  printf("receive no descriptor errors:        %u\n", e->receive_no_descriptor_errors);
1453  printf("receive fatal errors:                %u\n", e->receive_fatal_errors);
1454  printf("transmit underrun errors:            %u\n", e->transmit_underrun_errors);
1455  printf("transmit late collision errors:      %u\n", e->transmit_late_collision_errors);
1456  printf("transmit excessive collision errors: %u\n", e->transmit_excessive_collision_errors);
1457  printf("transmit excessive defer errors:     %u\n", e->transmit_excessive_defer_errors);
1458  printf("transmit no descriptor errors:       %u\n", e->transmit_no_descriptor_errors);
1459  printf("transmit overflow errors:            %u\n", e->transmit_overflow_errors);
1460  printf("transmit fatal errors:               %u\n", e->transmit_fatal_errors);
1461
1462  rtems_bsdnet_semaphore_obtain();
1463}
1464
1465static int lpc_eth_multicast_control(
1466  bool add,
1467  struct ifreq *ifr,
1468  struct arpcom *ac
1469)
1470{
1471  int eno = 0;
1472
1473  if (add) {
1474    eno = ether_addmulti(ifr, ac);
1475  } else {
1476    eno = ether_delmulti(ifr, ac);
1477  }
1478
1479  if (eno == ENETRESET) {
1480    struct ether_multistep step;
1481    struct ether_multi *enm;
1482
1483    eno = 0;
1484
1485    lpc_eth->hashfilterl = 0;
1486    lpc_eth->hashfilterh = 0;
1487
1488    ETHER_FIRST_MULTI(step, ac, enm);
1489    while (enm != NULL) {
1490      uint64_t addrlo = 0;
1491      uint64_t addrhi = 0;
1492
1493      memcpy(&addrlo, enm->enm_addrlo, ETHER_ADDR_LEN);
1494      memcpy(&addrhi, enm->enm_addrhi, ETHER_ADDR_LEN);
1495      while (addrlo <= addrhi) {
1496        /* XXX: ether_crc32_le() does not work, why? */
1497        uint32_t crc = ether_crc32_be((uint8_t *) &addrlo, ETHER_ADDR_LEN);
1498        uint32_t index = (crc >> 23) & 0x3f;
1499
1500        if (index < 32) {
1501          lpc_eth->hashfilterl |= 1U << index;
1502        } else {
1503          lpc_eth->hashfilterh |= 1U << (index - 32);
1504        }
1505        ++addrlo;
1506      }
1507      ETHER_NEXT_MULTI(step, enm);
1508    }
1509  }
1510
1511  return eno;
1512}
1513
1514static int lpc_eth_interface_ioctl(
1515  struct ifnet *ifp,
1516  ioctl_command_t cmd,
1517  caddr_t data
1518)
1519{
1520  lpc_eth_driver_entry *e = (lpc_eth_driver_entry *) ifp->if_softc;
1521  struct ifreq *ifr = (struct ifreq *) data;
1522  int eno = 0;
1523
1524  LPC_ETH_PRINTF("%s\n", __func__);
1525
1526  switch (cmd)  {
1527    case SIOCGIFMEDIA:
1528    case SIOCSIFMEDIA:
1529      rtems_mii_ioctl(&e->mdio, e, cmd, &ifr->ifr_media);
1530      break;
1531    case SIOCGIFADDR:
1532    case SIOCSIFADDR:
1533      ether_ioctl(ifp, cmd, data);
1534      break;
1535    case SIOCSIFFLAGS:
1536      eno = lpc_eth_up_or_down(e, (ifp->if_flags & IFF_UP) != 0);
1537      if (eno == 0 && (ifp->if_flags & IFF_UP) != 0) {
1538        lpc_eth_enable_promiscous_mode((ifp->if_flags & IFF_PROMISC) != 0);
1539      }
1540      break;
1541    case SIOCADDMULTI:
1542    case SIOCDELMULTI:
1543      eno = lpc_eth_multicast_control(cmd == SIOCADDMULTI, ifr, &e->arpcom);
1544      break;
1545    case SIO_RTEMS_SHOW_STATS:
1546      lpc_eth_interface_stats(e);
1547      break;
1548    default:
1549      eno = EINVAL;
1550      break;
1551  }
1552
1553  return eno;
1554}
1555
1556static void lpc_eth_interface_start(struct ifnet *ifp)
1557{
1558  rtems_status_code sc = RTEMS_SUCCESSFUL;
1559  lpc_eth_driver_entry *e = (lpc_eth_driver_entry *) ifp->if_softc;
1560
1561  ifp->if_flags |= IFF_OACTIVE;
1562
1563  if (e->state == LPC_ETH_STATE_UP) {
1564    sc = rtems_bsdnet_event_send(e->transmit_task, LPC_ETH_EVENT_TXSTART);
1565    assert(sc == RTEMS_SUCCESSFUL);
1566  }
1567}
1568
1569static void lpc_eth_interface_watchdog(struct ifnet *ifp)
1570{
1571  lpc_eth_driver_entry *e = (lpc_eth_driver_entry *) ifp->if_softc;
1572
1573  if (e->state == LPC_ETH_STATE_UP) {
1574    uint32_t anlpar = lpc_eth_mdio_read_anlpar();
1575
1576    if (e->anlpar != anlpar) {
1577      bool full_duplex = false;
1578      bool speed = false;
1579
1580      e->anlpar = anlpar;
1581
1582      if ((anlpar & ANLPAR_TX_FD) != 0) {
1583        full_duplex = true;
1584        speed = true;
1585      } else if ((anlpar & ANLPAR_T4) != 0) {
1586        speed = true;
1587      } else if ((anlpar & ANLPAR_TX) != 0) {
1588        speed = true;
1589      } else if ((anlpar & ANLPAR_10_FD) != 0) {
1590        full_duplex = true;
1591      }
1592
1593      if (full_duplex) {
1594        lpc_eth->mac2 |= ETH_MAC2_FULL_DUPLEX;
1595      } else {
1596        lpc_eth->mac2 &= ~ETH_MAC2_FULL_DUPLEX;
1597      }
1598
1599      if (speed) {
1600        lpc_eth->supp |= ETH_SUPP_SPEED;
1601      } else {
1602        lpc_eth->supp &= ~ETH_SUPP_SPEED;
1603      }
1604    }
1605
1606    ifp->if_timer = WATCHDOG_TIMEOUT;
1607  }
1608}
1609
1610static unsigned lpc_eth_fixup_unit_count(int count, int default_value, int max)
1611{
1612  if (count <= 0) {
1613    count = default_value;
1614  } else if (count > max) {
1615    count = max;
1616  }
1617
1618  return LPC_ETH_CONFIG_UNIT_MULTIPLE
1619    + (((unsigned) count - 1U) & ~(LPC_ETH_CONFIG_UNIT_MULTIPLE - 1U));
1620}
1621
1622static int lpc_eth_attach(struct rtems_bsdnet_ifconfig *config)
1623{
1624  lpc_eth_driver_entry *e = &lpc_eth_driver_data;
1625  struct ifnet *ifp = &e->arpcom.ac_if;
1626  char *unit_name = NULL;
1627  int unit_index = rtems_bsdnet_parse_driver_name(config, &unit_name);
1628  size_t table_area_size = 0;
1629  char *table_area = NULL;
1630  char *table_location = NULL;
1631
1632  /* Check parameter */
1633  if (unit_index < 0) {
1634    return 0;
1635  }
1636  if (unit_index != 0) {
1637    goto cleanup;
1638  }
1639  if (config->hardware_address == NULL) {
1640    goto cleanup;
1641  }
1642  if (e->state != LPC_ETH_STATE_NOT_INITIALIZED) {
1643    goto cleanup;
1644  }
1645
1646  /* MDIO */
1647  e->mdio.mdio_r = lpc_eth_mdio_read;
1648  e->mdio.mdio_w = lpc_eth_mdio_write;
1649  e->mdio.has_gmii = 0;
1650  e->anlpar = 0;
1651
1652  /* Interrupt number */
1653  config->irno = LPC_ETH_CONFIG_INTERRUPT;
1654
1655  /* Device control */
1656  config->drv_ctrl = e;
1657
1658  /* Receive unit count */
1659  e->rx_unit_count = lpc_eth_fixup_unit_count(
1660    config->rbuf_count,
1661    LPC_ETH_CONFIG_RX_UNIT_COUNT_DEFAULT,
1662    LPC_ETH_CONFIG_RX_UNIT_COUNT_MAX
1663  );
1664  config->rbuf_count = (int) e->rx_unit_count;
1665
1666  /* Transmit unit count */
1667  e->tx_unit_count = lpc_eth_fixup_unit_count(
1668    config->xbuf_count,
1669    LPC_ETH_CONFIG_TX_UNIT_COUNT_DEFAULT,
1670    LPC_ETH_CONFIG_TX_UNIT_COUNT_MAX
1671  );
1672  config->xbuf_count = (int) e->tx_unit_count;
1673
1674  /* Remember interrupt number */
1675  e->interrupt_number = config->irno;
1676
1677  /* Copy MAC address */
1678  memcpy(e->arpcom.ac_enaddr, config->hardware_address, ETHER_ADDR_LEN);
1679
1680  /* Allocate and clear table area */
1681  table_area_size =
1682    e->rx_unit_count
1683      * (sizeof(lpc_eth_transfer_descriptor)
1684        + sizeof(lpc_eth_receive_status)
1685        + sizeof(struct mbuf *))
1686    + e->tx_unit_count
1687      * (sizeof(lpc_eth_transfer_descriptor)
1688        + sizeof(uint32_t)
1689        + LPC_ETH_CONFIG_TX_BUF_SIZE);
1690  table_area = lpc_eth_config_alloc_table_area(table_area_size);
1691  if (table_area == NULL) {
1692    goto cleanup;
1693  }
1694  memset(table_area, 0, table_area_size);
1695
1696  table_location = table_area;
1697
1698  /*
1699   * The receive status table must be the first one since it has the strictest
1700   * alignment requirements.
1701   */
1702  e->rx_status_table = (volatile lpc_eth_receive_status *) table_location;
1703  table_location += e->rx_unit_count * sizeof(e->rx_status_table [0]);
1704
1705  e->rx_desc_table = (volatile lpc_eth_transfer_descriptor *) table_location;
1706  table_location += e->rx_unit_count * sizeof(e->rx_desc_table [0]);
1707
1708  e->rx_mbuf_table = (struct mbuf **) table_location;
1709  table_location += e->rx_unit_count * sizeof(e->rx_mbuf_table [0]);
1710
1711  e->tx_desc_table = (volatile lpc_eth_transfer_descriptor *) table_location;
1712  table_location += e->tx_unit_count * sizeof(e->tx_desc_table [0]);
1713
1714  e->tx_status_table = (volatile uint32_t *) table_location;
1715  table_location += e->tx_unit_count * sizeof(e->tx_status_table [0]);
1716
1717  e->tx_buf_table = table_location;
1718
1719  /* Set interface data */
1720  ifp->if_softc = e;
1721  ifp->if_unit = (short) unit_index;
1722  ifp->if_name = unit_name;
1723  ifp->if_mtu = (config->mtu > 0) ? (u_long) config->mtu : ETHERMTU;
1724  ifp->if_init = lpc_eth_interface_init;
1725  ifp->if_ioctl = lpc_eth_interface_ioctl;
1726  ifp->if_start = lpc_eth_interface_start;
1727  ifp->if_output = ether_output;
1728  ifp->if_watchdog = lpc_eth_interface_watchdog;
1729  ifp->if_flags = IFF_MULTICAST | IFF_BROADCAST | IFF_SIMPLEX;
1730  ifp->if_snd.ifq_maxlen = ifqmaxlen;
1731  ifp->if_timer = 0;
1732
1733  /* Create tasks */
1734  e->receive_task = rtems_bsdnet_newproc(
1735    "ntrx",
1736    4096,
1737    lpc_eth_receive_task,
1738    e
1739  );
1740  e->transmit_task = rtems_bsdnet_newproc(
1741    "nttx",
1742    4096,
1743    lpc_eth_transmit_task,
1744    e
1745  );
1746
1747  /* Change status */
1748  ifp->if_flags |= IFF_RUNNING;
1749  e->state = LPC_ETH_STATE_DOWN;
1750
1751  /* Attach the interface */
1752  if_attach(ifp);
1753  ether_ifattach(ifp);
1754
1755  return 1;
1756
1757cleanup:
1758
1759  lpc_eth_config_free_table_area(table_area);
1760
1761  /* FIXME: Type */
1762  free(unit_name, (int) 0xdeadbeef);
1763
1764  return 0;
1765}
1766
1767static int lpc_eth_detach(
1768  struct rtems_bsdnet_ifconfig *config __attribute__((unused))
1769)
1770{
1771  /* FIXME: Detach the interface from the upper layers? */
1772
1773  /* Module soft reset */
1774  lpc_eth->command = 0x38;
1775  lpc_eth->mac1 = 0xcf00;
1776
1777  /* FIXME: More cleanup */
1778
1779  return 0;
1780}
1781
1782int lpc_eth_attach_detach(
1783  struct rtems_bsdnet_ifconfig *config,
1784  int attaching
1785)
1786{
1787  /* FIXME: Return value */
1788
1789  if (attaching) {
1790    return lpc_eth_attach(config);
1791  } else {
1792    return lpc_eth_detach(config);
1793  }
1794}
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