source: rtems/c/src/lib/libbsp/arm/shared/lpc/network/lpc-ethernet.c @ 6d4d934

4.115
Last change on this file since 6d4d934 was 6d4d934, checked in by Sebastian Huber <sebastian.huber@…>, on 12/16/10 at 13:35:26

2010-12-16 Sebastian Huber <sebastian.huber@…>

  • shared/lpc/include/lpc-i2s.h: Documentation. Fixed defines.
  • shared/lpc/include/lpc-timer.h: Documentation.
  • shared/lpc/network/lpc-ethernet.c: Added support for 10MBit/s links.
  • Property mode set to 100644
File size: 40.2 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup lpc_eth
5 *
6 * @brief Ethernet driver.
7 */
8
9/*
10 * Copyright (c) 2009
11 * embedded brains GmbH
12 * Obere Lagerstr. 30
13 * D-82178 Puchheim
14 * Germany
15 * <rtems@embedded-brains.de>
16 *
17 * The license and distribution terms for this file may be
18 * found in the file LICENSE in this distribution or at
19 * http://www.rtems.com/license/LICENSE.
20 */
21
22#define __INSIDE_RTEMS_BSD_TCPIP_STACK__ 1
23#define __BSD_VISIBLE 1
24
25#include <errno.h>
26#include <inttypes.h>
27#include <stdlib.h>
28#include <stdio.h>
29#include <string.h>
30
31#include <rtems.h>
32#include <rtems/rtems_bsdnet.h>
33#include <rtems/rtems_mii_ioctl.h>
34
35#include <sys/param.h>
36#include <sys/socket.h>
37#include <sys/sockio.h>
38#include <sys/mbuf.h>
39
40#include <net/if.h>
41#include <net/if_arp.h>
42#include <netinet/in.h>
43#include <netinet/if_ether.h>
44#include <netinet/in_systm.h>
45#include <netinet/ip.h>
46
47#include <bsp.h>
48#include <bsp/irq.h>
49#include <bsp/lpc-ethernet-config.h>
50#include <bsp/utility.h>
51
52#include <rtems/status-checks.h>
53
54#if MCLBYTES > (2 * 1024)
55  #error "MCLBYTES to large"
56#endif
57
58#ifdef LPC_ETH_CONFIG_USE_TRANSMIT_DMA
59  #define LPC_ETH_CONFIG_TX_BUF_SIZE sizeof(struct mbuf *)
60#else
61  #define LPC_ETH_CONFIG_TX_BUF_SIZE 1518U
62#endif
63
64#define DEFAULT_PHY 0
65#define WATCHDOG_TIMEOUT 5
66
67typedef struct {
68  uint32_t start;
69  uint32_t control;
70} lpc_eth_transfer_descriptor;
71
72typedef struct {
73  uint32_t info;
74  uint32_t hash_crc;
75} lpc_eth_receive_status;
76
77typedef struct {
78  uint32_t mac1;
79  uint32_t mac2;
80  uint32_t ipgt;
81  uint32_t ipgr;
82  uint32_t clrt;
83  uint32_t maxf;
84  uint32_t supp;
85  uint32_t test;
86  uint32_t mcfg;
87  uint32_t mcmd;
88  uint32_t madr;
89  uint32_t mwtd;
90  uint32_t mrdd;
91  uint32_t mind;
92  uint32_t reserved_0 [2];
93  uint32_t sa0;
94  uint32_t sa1;
95  uint32_t sa2;
96  uint32_t reserved_1 [45];
97  uint32_t command;
98  uint32_t status;
99  uint32_t rxdescriptor;
100  uint32_t rxstatus;
101  uint32_t rxdescriptornum;
102  uint32_t rxproduceindex;
103  uint32_t rxconsumeindex;
104  uint32_t txdescriptor;
105  uint32_t txstatus;
106  uint32_t txdescriptornum;
107  uint32_t txproduceindex;
108  uint32_t txconsumeindex;
109  uint32_t reserved_2 [10];
110  uint32_t tsv0;
111  uint32_t tsv1;
112  uint32_t rsv;
113  uint32_t reserved_3 [3];
114  uint32_t flowcontrolcnt;
115  uint32_t flowcontrolsts;
116  uint32_t reserved_4 [34];
117  uint32_t rxfilterctrl;
118  uint32_t rxfilterwolsts;
119  uint32_t rxfilterwolclr;
120  uint32_t reserved_5 [1];
121  uint32_t hashfilterl;
122  uint32_t hashfilterh;
123  uint32_t reserved_6 [882];
124  uint32_t intstatus;
125  uint32_t intenable;
126  uint32_t intclear;
127  uint32_t intset;
128  uint32_t reserved_7 [1];
129  uint32_t powerdown;
130} lpc_eth_controller;
131
132static volatile lpc_eth_controller *const lpc_eth =
133  (volatile lpc_eth_controller *) LPC_ETH_CONFIG_REG_BASE;
134
135/* ETH_RX_CTRL */
136
137#define ETH_RX_CTRL_SIZE_MASK 0x000007ffU
138#define ETH_RX_CTRL_INTERRUPT 0x80000000U
139
140/* ETH_RX_STAT */
141
142#define ETH_RX_STAT_RXSIZE_MASK 0x000007ffU
143#define ETH_RX_STAT_BYTES 0x00000100U
144#define ETH_RX_STAT_CONTROL_FRAME 0x00040000U
145#define ETH_RX_STAT_VLAN 0x00080000U
146#define ETH_RX_STAT_FAIL_FILTER 0x00100000U
147#define ETH_RX_STAT_MULTICAST 0x00200000U
148#define ETH_RX_STAT_BROADCAST 0x00400000U
149#define ETH_RX_STAT_CRC_ERROR 0x00800000U
150#define ETH_RX_STAT_SYMBOL_ERROR 0x01000000U
151#define ETH_RX_STAT_LENGTH_ERROR 0x02000000U
152#define ETH_RX_STAT_RANGE_ERROR 0x04000000U
153#define ETH_RX_STAT_ALIGNMENT_ERROR 0x08000000U
154#define ETH_RX_STAT_OVERRUN 0x10000000U
155#define ETH_RX_STAT_NO_DESCRIPTOR 0x20000000U
156#define ETH_RX_STAT_LAST_FLAG 0x40000000U
157#define ETH_RX_STAT_ERROR 0x80000000U
158
159/* ETH_TX_CTRL */
160
161#define ETH_TX_CTRL_SIZE_MASK 0x7ffU
162#define ETH_TX_CTRL_SIZE_SHIFT 0
163#define ETH_TX_CTRL_OVERRIDE 0x04000000U
164#define ETH_TX_CTRL_HUGE 0x08000000U
165#define ETH_TX_CTRL_PAD 0x10000000U
166#define ETH_TX_CTRL_CRC 0x20000000U
167#define ETH_TX_CTRL_LAST 0x40000000U
168#define ETH_TX_CTRL_INTERRUPT 0x80000000U
169
170/* ETH_TX_STAT */
171
172#define ETH_TX_STAT_COLLISION_COUNT_MASK 0x01e00000U
173#define ETH_TX_STAT_DEFER 0x02000000U
174#define ETH_TX_STAT_EXCESSIVE_DEFER 0x04000000U
175#define ETH_TX_STAT_EXCESSIVE_COLLISION 0x08000000U
176#define ETH_TX_STAT_LATE_COLLISION 0x10000000U
177#define ETH_TX_STAT_UNDERRUN 0x20000000U
178#define ETH_TX_STAT_NO_DESCRIPTOR 0x40000000U
179#define ETH_TX_STAT_ERROR 0x80000000U
180
181/* ETH_INT */
182
183#define ETH_INT_RX_OVERRUN 0x00000001U
184#define ETH_INT_RX_ERROR 0x00000002U
185#define ETH_INT_RX_FINISHED 0x00000004U
186#define ETH_INT_RX_DONE 0x00000008U
187#define ETH_INT_TX_UNDERRUN 0x00000010U
188#define ETH_INT_TX_ERROR 0x00000020U
189#define ETH_INT_TX_FINISHED 0x00000040U
190#define ETH_INT_TX_DONE 0x00000080U
191#define ETH_INT_SOFT 0x00001000U
192#define ETH_INT_WAKEUP 0x00002000U
193
194/* ETH_RX_FIL_CTRL */
195
196#define ETH_RX_FIL_CTRL_ACCEPT_UNICAST 0x00000001U
197#define ETH_RX_FIL_CTRL_ACCEPT_BROADCAST 0x00000002U
198#define ETH_RX_FIL_CTRL_ACCEPT_MULTICAST 0x00000004U
199#define ETH_RX_FIL_CTRL_ACCEPT_UNICAST_HASH 0x00000008U
200#define ETH_RX_FIL_CTRL_ACCEPT_MULTICAST_HASH 0x00000010U
201#define ETH_RX_FIL_CTRL_ACCEPT_PERFECT 0x00000020U
202#define ETH_RX_FIL_CTRL_MAGIC_PACKET_WOL 0x00001000U
203#define ETH_RX_FIL_CTRL_RX_FILTER_WOL 0x00002000U
204
205/* ETH_CMD */
206
207#define ETH_CMD_RX_ENABLE 0x00000001U
208#define ETH_CMD_TX_ENABLE 0x00000002U
209#define ETH_CMD_REG_RESET 0x00000008U
210#define ETH_CMD_TX_RESET 0x00000010U
211#define ETH_CMD_RX_RESET 0x00000020U
212#define ETH_CMD_PASS_RUNT_FRAME 0x00000040U
213#define ETH_CMD_PASS_RX_FILTER 0X00000080U
214#define ETH_CMD_TX_FLOW_CONTROL 0x00000100U
215#define ETH_CMD_RMII 0x00000200U
216#define ETH_CMD_FULL_DUPLEX 0x00000400U
217
218/* ETH_STAT */
219
220#define ETH_STAT_RX_ACTIVE 0x00000001U
221#define ETH_STAT_TX_ACTIVE 0x00000002U
222
223/* ETH_MAC2 */
224
225#define ETH_MAC2_FULL_DUPLEX BSP_BIT32(8)
226
227/* ETH_SUPP */
228
229#define ETH_SUPP_SPEED BSP_BIT32(8)
230
231/* ETH_MCFG */
232
233#define ETH_MCFG_CLOCK_SELECT(val) BSP_FLD32(val, 2, 4)
234
235/* ETH_MCMD */
236
237#define ETH_MCMD_READ BSP_BIT32(0)
238#define ETH_MCMD_SCAN BSP_BIT32(1)
239
240/* ETH_MADR */
241
242#define ETH_MADR_REG(val) BSP_FLD32(val, 0, 4)
243#define ETH_MADR_PHY(val) BSP_FLD32(val, 8, 12)
244
245/* ETH_MIND */
246
247#define ETH_MIND_BUSY BSP_BIT32(0)
248#define ETH_MIND_SCANNING BSP_BIT32(1)
249#define ETH_MIND_NOT_VALID BSP_BIT32(2)
250#define ETH_MIND_MII_LINK_FAIL BSP_BIT32(3)
251
252/* Events */
253
254#define LPC_ETH_EVENT_INITIALIZE RTEMS_EVENT_1
255
256#define LPC_ETH_EVENT_START RTEMS_EVENT_2
257
258#define LPC_ETH_EVENT_INTERRUPT RTEMS_EVENT_3
259
260/* Status */
261
262#define LPC_ETH_INTERRUPT_RECEIVE \
263  (ETH_INT_RX_ERROR | ETH_INT_RX_FINISHED | ETH_INT_RX_DONE)
264
265#define LPC_ETH_INTERRUPT_TRANSMIT \
266  (ETH_INT_TX_DONE | ETH_INT_TX_FINISHED | ETH_INT_TX_ERROR)
267
268#define LPC_ETH_RX_STAT_ERRORS \
269  (ETH_RX_STAT_CRC_ERROR \
270    | ETH_RX_STAT_SYMBOL_ERROR \
271    | ETH_RX_STAT_LENGTH_ERROR \
272    | ETH_RX_STAT_ALIGNMENT_ERROR \
273    | ETH_RX_STAT_OVERRUN \
274    | ETH_RX_STAT_NO_DESCRIPTOR)
275
276#define LPC_ETH_LAST_FRAGMENT_FLAGS \
277  (ETH_TX_CTRL_OVERRIDE \
278    | ETH_TX_CTRL_PAD \
279    | ETH_TX_CTRL_CRC \
280    | ETH_TX_CTRL_INTERRUPT \
281    | ETH_TX_CTRL_LAST)
282
283/* Debug */
284
285#ifdef DEBUG
286  #define LPC_ETH_PRINTF(...) printf(__VA_ARGS__)
287  #define LPC_ETH_PRINTK(...) printk(__VA_ARGS__)
288#else
289  #define LPC_ETH_PRINTF(...)
290  #define LPC_ETH_PRINTK(...)
291#endif
292
293typedef enum {
294  LPC_ETH_NOT_INITIALIZED,
295  LPC_ETH_INITIALIZED,
296  LPC_ETH_STARTED,
297  LPC_ETH_RUNNING
298} lpc_eth_state;
299
300typedef struct {
301  struct arpcom arpcom;
302  lpc_eth_state state;
303  struct rtems_mdio_info mdio;
304  uint32_t anlpar;
305  rtems_id receive_task;
306  rtems_id transmit_task;
307  unsigned rx_unit_count;
308  unsigned tx_unit_count;
309  volatile lpc_eth_transfer_descriptor *rx_desc_table;
310  volatile lpc_eth_receive_status *rx_status_table;
311  struct mbuf **rx_mbuf_table;
312  volatile lpc_eth_transfer_descriptor *tx_desc_table;
313  volatile uint32_t *tx_status_table;
314  void *tx_buf_table;
315  unsigned received_frames;
316  unsigned receive_interrupts;
317  unsigned transmitted_frames;
318  unsigned transmit_interrupts;
319  unsigned receive_overrun_errors;
320  unsigned receive_fragment_errors;
321  unsigned receive_crc_errors;
322  unsigned receive_symbol_errors;
323  unsigned receive_length_errors;
324  unsigned receive_alignment_errors;
325  unsigned receive_no_descriptor_errors;
326  unsigned receive_fatal_errors;
327  unsigned transmit_underrun_errors;
328  unsigned transmit_late_collision_errors;
329  unsigned transmit_excessive_collision_errors;
330  unsigned transmit_excessive_defer_errors;
331  unsigned transmit_no_descriptor_errors;
332  unsigned transmit_overflow_errors;
333  unsigned transmit_fatal_errors;
334} lpc_eth_driver_entry;
335
336static lpc_eth_driver_entry lpc_eth_driver_data = {
337  .state = LPC_ETH_NOT_INITIALIZED,
338  .receive_task = RTEMS_ID_NONE,
339  .transmit_task = RTEMS_ID_NONE
340};
341
342static inline uint32_t lpc_eth_increment(
343  uint32_t value,
344  uint32_t cycle
345)
346{
347  if (value < cycle) {
348    return ++value;
349  } else {
350    return 0;
351  }
352}
353
354static void lpc_eth_enable_promiscous_mode(bool enable)
355{
356  if (enable) {
357    lpc_eth->rxfilterctrl = ETH_RX_FIL_CTRL_ACCEPT_PERFECT
358      | ETH_RX_FIL_CTRL_ACCEPT_UNICAST
359      | ETH_RX_FIL_CTRL_ACCEPT_MULTICAST
360      | ETH_RX_FIL_CTRL_ACCEPT_BROADCAST;
361  } else {
362    lpc_eth->rxfilterctrl = ETH_RX_FIL_CTRL_ACCEPT_PERFECT
363      | ETH_RX_FIL_CTRL_ACCEPT_BROADCAST;
364  }
365}
366
367static void lpc_eth_interrupt_handler(void *arg)
368{
369  lpc_eth_driver_entry *e = (lpc_eth_driver_entry *) arg;
370  rtems_event_set re = 0;
371  rtems_event_set te = 0;
372  uint32_t ie = 0;
373
374  /* Get interrupt status */
375  uint32_t im = lpc_eth->intenable;
376  uint32_t is = lpc_eth->intstatus & im;
377
378  /* Check receive interrupts */
379  if ((is & ETH_INT_RX_OVERRUN) != 0) {
380    re = LPC_ETH_EVENT_INITIALIZE;
381    ++e->receive_fatal_errors;
382  } else if ((is & LPC_ETH_INTERRUPT_RECEIVE) != 0) {
383    re = LPC_ETH_EVENT_INTERRUPT;
384    ie |= LPC_ETH_INTERRUPT_RECEIVE;
385  }
386
387  /* Send events to receive task */
388  if (re != 0) {
389    ++e->receive_interrupts;
390    (void) rtems_event_send(e->receive_task, re);
391  }
392
393  /* Check transmit interrupts */
394  if ((is & ETH_INT_TX_UNDERRUN) != 0) {
395    te = LPC_ETH_EVENT_INITIALIZE;
396    ++e->transmit_fatal_errors;
397  } else if ((is & LPC_ETH_INTERRUPT_TRANSMIT) != 0) {
398    te = LPC_ETH_EVENT_INTERRUPT;
399    ie |= LPC_ETH_INTERRUPT_TRANSMIT;
400  }
401
402  /* Send events to transmit task */
403  if (te != 0) {
404    ++e->transmit_interrupts;
405    (void) rtems_event_send(e->transmit_task, te);
406  }
407
408  LPC_ETH_PRINTK("interrupt: rx = 0x%08x, tx = 0x%08x\n", re, te);
409
410  /* Update interrupt mask */
411  lpc_eth->intenable = im & ~ie;
412
413  /* Clear interrupts */
414  lpc_eth->intclear = is;
415}
416
417static void lpc_eth_enable_receive_interrupts(void)
418{
419  rtems_interrupt_level level;
420
421  rtems_interrupt_disable(level);
422  lpc_eth->intenable |= LPC_ETH_INTERRUPT_RECEIVE;
423  rtems_interrupt_enable(level);
424}
425
426static void lpc_eth_disable_receive_interrupts(void)
427{
428  rtems_interrupt_level level;
429
430  rtems_interrupt_disable(level);
431  lpc_eth->intenable &= ~LPC_ETH_INTERRUPT_RECEIVE;
432  rtems_interrupt_enable(level);
433}
434
435static void lpc_eth_enable_transmit_interrupts(void)
436{
437  rtems_interrupt_level level;
438
439  rtems_interrupt_disable(level);
440  lpc_eth->intenable |= LPC_ETH_INTERRUPT_TRANSMIT;
441  rtems_interrupt_enable(level);
442}
443
444static void lpc_eth_disable_transmit_interrupts(void)
445{
446  rtems_interrupt_level level;
447
448  rtems_interrupt_disable(level);
449  lpc_eth->intenable &= ~LPC_ETH_INTERRUPT_TRANSMIT;
450  rtems_interrupt_enable(level);
451}
452
453#define LPC_ETH_RX_DATA_OFFSET 2
454
455static struct mbuf *lpc_eth_new_mbuf(struct ifnet *ifp, bool wait)
456{
457  struct mbuf *m = NULL;
458  int mw = wait ? M_WAIT : M_DONTWAIT;
459
460  MGETHDR(m, mw, MT_DATA);
461  if (m != NULL) {
462    MCLGET(m, mw);
463    if ((m->m_flags & M_EXT) != 0) {
464      /* Set receive interface */
465      m->m_pkthdr.rcvif = ifp;
466
467      /* Adjust by two bytes for proper IP header alignment */
468      m->m_data = mtod(m, char *) + LPC_ETH_RX_DATA_OFFSET;
469
470      return m;
471    } else {
472      m_free(m);
473    }
474  }
475
476  return NULL;
477}
478
479static bool lpc_eth_add_new_mbuf(
480  struct ifnet *ifp,
481  volatile lpc_eth_transfer_descriptor *desc,
482  struct mbuf **mbufs,
483  uint32_t i,
484  bool wait
485)
486{
487  /* New mbuf */
488  struct mbuf *m = lpc_eth_new_mbuf(ifp, wait);
489
490  /* Check mbuf */
491  if (m != NULL) {
492    /* Cache invalidate */
493    rtems_cache_invalidate_multiple_data_lines(
494      mtod(m, void *),
495      MCLBYTES - LPC_ETH_RX_DATA_OFFSET
496    );
497
498    /* Add mbuf to queue */
499    desc [i].start = mtod(m, uint32_t);
500    desc [i].control = (MCLBYTES - LPC_ETH_RX_DATA_OFFSET - 1)
501      | ETH_RX_CTRL_INTERRUPT;
502
503    /* Cache flush of descriptor  */
504    rtems_cache_flush_multiple_data_lines((void *)&desc [i],
505                                          sizeof(desc [0]));
506
507    /* Add mbuf to table */
508    mbufs [i] = m;
509
510    return true;
511  } else {
512    return false;
513  }
514}
515
516static void lpc_eth_receive_task(void *arg)
517{
518  rtems_status_code sc = RTEMS_SUCCESSFUL;
519  rtems_event_set events = 0;
520  lpc_eth_driver_entry *const e = (lpc_eth_driver_entry *) arg;
521  struct ifnet *const ifp = &e->arpcom.ac_if;
522  volatile lpc_eth_transfer_descriptor *const desc = e->rx_desc_table;
523  volatile lpc_eth_receive_status *const status = e->rx_status_table;
524  struct mbuf **const mbufs = e->rx_mbuf_table;
525  uint32_t const index_max = e->rx_unit_count - 1;
526  uint32_t produce_index = 0;
527  uint32_t consume_index = 0;
528  uint32_t receive_index = 0;
529
530  LPC_ETH_PRINTF("%s\n", __func__);
531
532  /* Main event loop */
533  while (true) {
534    bool wait_for_mbuf = false;
535
536    /* Wait for events */
537    sc = rtems_bsdnet_event_receive(
538      LPC_ETH_EVENT_INITIALIZE | LPC_ETH_EVENT_INTERRUPT,
539      RTEMS_EVENT_ANY | RTEMS_WAIT,
540      RTEMS_NO_TIMEOUT,
541      &events
542    );
543    RTEMS_CLEANUP_SC(sc, cleanup, "wait for events");
544
545    LPC_ETH_PRINTF("rx: wake up: 0x%08" PRIx32 "\n", events);
546
547    /* Initialize receiver? */
548    if ((events & LPC_ETH_EVENT_INITIALIZE) != 0) {
549      /* Disable receive interrupts */
550      lpc_eth_disable_receive_interrupts();
551
552      /* Disable receiver */
553      lpc_eth->command &= ~ETH_CMD_RX_ENABLE;
554
555      /* Wait for inactive status */
556      while ((lpc_eth->status & ETH_STAT_RX_ACTIVE) != 0) {
557        /* Wait */
558      }
559
560      /* Reset */
561      lpc_eth->command |= ETH_CMD_RX_RESET;
562
563      /* Clear receive interrupts */
564      lpc_eth->intclear = LPC_ETH_INTERRUPT_RECEIVE;
565
566      /* Move existing mbufs to the front */
567      consume_index = 0;
568      for (produce_index = 0; produce_index <= index_max; ++produce_index) {
569        if (mbufs [produce_index] != NULL) {
570          mbufs [consume_index] = mbufs [produce_index];
571          ++consume_index;
572        }
573      }
574
575      /* Fill receive queue */
576      for (
577        produce_index = consume_index;
578        produce_index <= index_max;
579        ++produce_index
580      ) {
581        lpc_eth_add_new_mbuf(ifp, desc, mbufs, produce_index, true);
582      }
583
584      /* Receive descriptor table */
585      lpc_eth->rxdescriptornum = index_max;
586      lpc_eth->rxdescriptor = (uint32_t) desc;
587      lpc_eth->rxstatus = (uint32_t) status;
588
589      /* Initialize indices */
590      produce_index = lpc_eth->rxproduceindex;
591      consume_index = lpc_eth->rxconsumeindex;
592      receive_index = consume_index;
593
594      /* Enable receiver */
595      lpc_eth->command |= ETH_CMD_RX_ENABLE;
596
597      /* Enable receive interrupts */
598      lpc_eth_enable_receive_interrupts();
599
600      /* Wait for events */
601      continue;
602    }
603
604    while (true) {
605      /* Clear receive interrupt status */
606      lpc_eth->intclear = LPC_ETH_INTERRUPT_RECEIVE;
607
608      /* Get current produce index */
609      produce_index = lpc_eth->rxproduceindex;
610
611      if (receive_index != produce_index) {
612        uint32_t stat = 0;
613
614        /* Fragment mbuf */
615        struct mbuf *m = mbufs [receive_index];
616
617        /* Fragment status */
618        rtems_cache_invalidate_multiple_data_lines
619          ((void *)&status [receive_index],
620           sizeof(status [0])
621           );
622        stat = status [receive_index].info;
623
624        /* Remove mbuf from table */
625        mbufs [receive_index] = NULL;
626
627        if (
628          (stat & ETH_RX_STAT_LAST_FLAG) != 0
629            && (stat & LPC_ETH_RX_STAT_ERRORS) == 0
630        ) {
631          /* Ethernet header */
632          struct ether_header *eh = mtod(m, struct ether_header *);
633
634          /* Discard Ethernet header and CRC */
635          int sz = (int) (stat & ETH_RX_STAT_RXSIZE_MASK) + 1
636            - ETHER_HDR_LEN - ETHER_CRC_LEN;
637
638          /* Update mbuf */
639          m->m_len = sz;
640          m->m_pkthdr.len = sz;
641          m->m_data = mtod(m, char *) + ETHER_HDR_LEN;
642
643          LPC_ETH_PRINTF("rx: %02" PRIu32 ": %u\n", receive_index, sz);
644
645          /* Hand over */
646          ether_input(ifp, eh, m);
647
648          /* Increment received frames counter */
649          ++e->received_frames;
650        } else {
651          /* Release mbuf */
652          m_free(m);
653
654          /* Update error counters */
655          if ((stat & ETH_RX_STAT_OVERRUN) != 0) {
656            ++e->receive_overrun_errors;
657          }
658          if ((stat & ETH_RX_STAT_LAST_FLAG) == 0) {
659            ++e->receive_fragment_errors;
660          }
661          if ((stat & ETH_RX_STAT_CRC_ERROR) != 0) {
662            ++e->receive_crc_errors;
663          }
664          if ((stat & ETH_RX_STAT_SYMBOL_ERROR) != 0) {
665            ++e->receive_symbol_errors;
666          }
667          if ((stat & ETH_RX_STAT_LENGTH_ERROR) != 0) {
668            ++e->receive_length_errors;
669          }
670          if ((stat & ETH_RX_STAT_ALIGNMENT_ERROR) != 0) {
671            ++e->receive_alignment_errors;
672          }
673          if ((stat & ETH_RX_STAT_NO_DESCRIPTOR) != 0) {
674            ++e->receive_no_descriptor_errors;
675          }
676        }
677
678        /* Increment receive index */
679        receive_index = lpc_eth_increment(receive_index, index_max);
680      } else {
681        /* Nothing to do, enable receive interrupts */
682        lpc_eth_enable_receive_interrupts();
683        break;
684      }
685    }
686
687    /* Wait for mbuf? */
688    wait_for_mbuf =
689      lpc_eth_increment(produce_index, index_max) == consume_index;
690
691    /* Fill queue with new mbufs */
692    while (consume_index != produce_index) {
693      /* Add new mbuf to queue */
694      if (
695        !lpc_eth_add_new_mbuf(ifp, desc, mbufs, consume_index, wait_for_mbuf)
696      ) {
697        break;
698      }
699
700      /* We wait for at most one mbuf */
701      wait_for_mbuf = false;
702
703      /* Increment consume index */
704      consume_index = lpc_eth_increment(consume_index, index_max);
705
706      /* Update consume indices */
707      lpc_eth->rxconsumeindex = consume_index;
708    }
709  }
710
711cleanup:
712
713  /* Clear task ID */
714  e->receive_task = RTEMS_ID_NONE;
715
716  /* Release network semaphore */
717  rtems_bsdnet_semaphore_release();
718
719  /* Terminate self */
720  (void) rtems_task_delete(RTEMS_SELF);
721}
722
723static struct mbuf *lpc_eth_next_fragment(
724  struct ifnet *ifp,
725  struct mbuf *m,
726  uint32_t *ctrl
727)
728{
729  struct mbuf *n = NULL;
730  int size = 0;
731
732  while (true) {
733    if (m == NULL) {
734      /* Dequeue first fragment of the next frame */
735      IF_DEQUEUE(&ifp->if_snd, m);
736
737      /* Empty queue? */
738      if (m == NULL) {
739        return m;
740      }
741    }
742
743    /* Get fragment size */
744    size = m->m_len;
745
746    if (size > 0) {
747      /* Now we have a not empty fragment */
748      break;
749    } else {
750      /* Discard empty fragments */
751      m = m_free(m);
752    }
753  }
754
755  /* Set fragment size */
756  *ctrl = (uint32_t) (size - 1);
757
758  /* Discard empty successive fragments */
759  n = m->m_next;
760  while (n != NULL && n->m_len <= 0) {
761    n = m_free(n);
762  }
763  m->m_next = n;
764
765  /* Is our fragment the last in the frame? */
766  if (n == NULL) {
767    *ctrl |= LPC_ETH_LAST_FRAGMENT_FLAGS;
768  }
769
770  return m;
771}
772
773static void lpc_eth_transmit_task(void *arg)
774{
775  rtems_status_code sc = RTEMS_SUCCESSFUL;
776  rtems_event_set events = 0;
777  lpc_eth_driver_entry *e = (lpc_eth_driver_entry *) arg;
778  struct ifnet *ifp = &e->arpcom.ac_if;
779  volatile lpc_eth_transfer_descriptor *const desc = e->tx_desc_table;
780  volatile uint32_t *const status = e->tx_status_table;
781  #ifdef LPC_ETH_CONFIG_USE_TRANSMIT_DMA
782    struct mbuf **const mbufs = e->tx_buf_table;
783  #else
784    char *const buf = e->tx_buf_table;
785  #endif
786  struct mbuf *m = NULL;
787  uint32_t const index_max = e->tx_unit_count - 1;
788  uint32_t produce_index = 0;
789  uint32_t consume_index = 0;
790  uint32_t ctrl = 0;
791  #ifndef LPC_ETH_CONFIG_USE_TRANSMIT_DMA
792    uint32_t frame_length = 0;
793    char *frame_buffer = NULL;
794  #endif
795
796  LPC_ETH_PRINTF("%s\n", __func__);
797
798  #ifndef LPC_ETH_CONFIG_USE_TRANSMIT_DMA
799    /* Initialize descriptor table */
800    for (produce_index = 0; produce_index <= index_max; ++produce_index) {
801      desc [produce_index].start =
802        (uint32_t) (buf + produce_index * LPC_ETH_CONFIG_TX_BUF_SIZE);
803    }
804  #endif
805
806  /* Main event loop */
807  while (true) {
808    /* Wait for events */
809    sc = rtems_bsdnet_event_receive(
810      LPC_ETH_EVENT_INITIALIZE
811        | LPC_ETH_EVENT_START
812        | LPC_ETH_EVENT_INTERRUPT,
813      RTEMS_EVENT_ANY | RTEMS_WAIT,
814      RTEMS_NO_TIMEOUT,
815      &events
816    );
817    RTEMS_CLEANUP_SC(sc, cleanup, "wait for events");
818
819    LPC_ETH_PRINTF("tx: wake up: 0x%08" PRIx32 "\n", events);
820
821    /* Initialize transmitter? */
822    if ((events & LPC_ETH_EVENT_INITIALIZE) != 0) {
823      /* Disable transmit interrupts */
824      lpc_eth_disable_transmit_interrupts();
825
826      /* Disable transmitter */
827      lpc_eth->command &= ~ETH_CMD_TX_ENABLE;
828
829      /* Wait for inactive status */
830      while ((lpc_eth->status & ETH_STAT_TX_ACTIVE) != 0) {
831        /* Wait */
832      }
833
834      /* Reset */
835      lpc_eth->command |= ETH_CMD_TX_RESET;
836
837      /* Clear transmit interrupts */
838      lpc_eth->intclear = LPC_ETH_INTERRUPT_TRANSMIT;
839
840      /* Transmit descriptors */
841      lpc_eth->txdescriptornum = index_max;
842      lpc_eth->txdescriptor = (uint32_t) desc;
843      lpc_eth->txstatus = (uint32_t) status;
844
845      #ifdef LPC_ETH_CONFIG_USE_TRANSMIT_DMA
846        /* Discard outstanding fragments (= data loss) */
847        for (produce_index = 0; produce_index <= index_max; ++produce_index) {
848          struct mbuf *victim = mbufs [produce_index];
849
850          if (victim != NULL) {
851            m_free(victim);
852            mbufs [produce_index] = NULL;
853          }
854        }
855      #endif
856
857      /* Initialize indices */
858      produce_index = lpc_eth->txproduceindex;
859      consume_index = lpc_eth->txconsumeindex;
860
861      #ifndef LPC_ETH_CONFIG_USE_TRANSMIT_DMA
862        /* Fresh frame length and buffer start */
863        frame_length = 0;
864        frame_buffer = (char *) desc [produce_index].start;
865      #endif
866
867      /* Enable transmitter */
868      lpc_eth->command |= ETH_CMD_TX_ENABLE;
869    }
870
871    /* Free consumed fragments */
872    while (true) {
873      /* Save last known consume index */
874      uint32_t c = consume_index;
875
876      /* Clear transmit interrupt status */
877      lpc_eth->intclear = LPC_ETH_INTERRUPT_TRANSMIT;
878
879      /* Get new consume index */
880      consume_index = lpc_eth->txconsumeindex;
881
882      /* Nothing consumed in the meantime? */
883      if (c == consume_index) {
884        break;
885      }
886
887      while (c != consume_index) {
888        uint32_t s = status [c];
889
890        /* Update error counters */
891        if ((s & (ETH_TX_STAT_ERROR | ETH_TX_STAT_NO_DESCRIPTOR)) != 0) {
892          if ((s & ETH_TX_STAT_UNDERRUN) != 0) {
893            ++e->transmit_underrun_errors;
894          }
895          if ((s & ETH_TX_STAT_LATE_COLLISION) != 0) {
896            ++e->transmit_late_collision_errors;
897          }
898          if ((s & ETH_TX_STAT_EXCESSIVE_COLLISION) != 0) {
899            ++e->transmit_excessive_collision_errors;
900          }
901          if ((s & ETH_TX_STAT_EXCESSIVE_DEFER) != 0) {
902            ++e->transmit_excessive_defer_errors;
903          }
904          if ((s & ETH_TX_STAT_NO_DESCRIPTOR) != 0) {
905            ++e->transmit_no_descriptor_errors;
906          }
907        }
908
909        #ifdef LPC_ETH_CONFIG_USE_TRANSMIT_DMA
910          /* Release mbuf */
911          m_free(mbufs [c]);
912          mbufs [c] = NULL;
913        #endif
914
915        /* Next consume index */
916        c = lpc_eth_increment(c, index_max);
917      }
918    }
919
920    /* Transmit new fragments */
921    while (true) {
922      /* Compute next produce index */
923      uint32_t p = lpc_eth_increment(produce_index, index_max);
924
925      /* Get next fragment and control value */
926      m = lpc_eth_next_fragment(ifp, m, &ctrl);
927
928      /* Queue full? */
929      if (p == consume_index) {
930        LPC_ETH_PRINTF("tx: full queue: 0x%08x\n", m);
931
932        /* The queue is full, wait for transmit interrupt */
933        break;
934      }
935
936      /* New fragment? */
937      if (m != NULL) {
938        #ifdef LPC_ETH_CONFIG_USE_TRANSMIT_DMA
939          /* Set the transfer data */
940          rtems_cache_flush_multiple_data_lines(
941            mtod(m, const void *),
942            (size_t) m->m_len
943          );
944          desc [produce_index].start = mtod(m, uint32_t);
945          desc [produce_index].control = ctrl;
946          rtems_cache_flush_multiple_data_lines
947            ((void *)&desc [produce_index],
948             sizeof(desc [0])
949             );
950          mbufs [produce_index] = m;
951
952          LPC_ETH_PRINTF(
953            "tx: %02" PRIu32 ": %u %s\n",
954            produce_index, m->m_len,
955            (ctrl & ETH_TX_CTRL_LAST) != 0 ? "L" : ""
956          );
957
958          /* Next produce index */
959          produce_index = p;
960
961          /* Last fragment of a frame? */
962          if ((ctrl & ETH_TX_CTRL_LAST) != 0) {
963            /* Update the produce index */
964            lpc_eth->txproduceindex = produce_index;
965
966            /* Increment transmitted frames counter */
967            ++e->transmitted_frames;
968          }
969
970          /* Next fragment of the frame */
971          m = m->m_next;
972        #else
973          size_t fragment_length = (size_t) m->m_len;
974          void *fragment_start = mtod(m, void *);
975          uint32_t new_frame_length = frame_length + fragment_length;
976
977          /* Check buffer size */
978          if (new_frame_length > LPC_ETH_CONFIG_TX_BUF_SIZE) {
979            LPC_ETH_PRINTF("tx: overflow\n");
980
981            /* Discard overflow data */
982            new_frame_length = LPC_ETH_CONFIG_TX_BUF_SIZE;
983            fragment_length = new_frame_length - frame_length;
984
985            /* Finalize frame */
986            ctrl |= LPC_ETH_LAST_FRAGMENT_FLAGS;
987
988            /* Update error counter */
989            ++e->transmit_overflow_errors;
990          }
991
992          LPC_ETH_PRINTF(
993            "tx: copy: %" PRIu32 "%s%s\n",
994            fragment_length,
995            (m->m_flags & M_EXT) != 0 ? ", E" : "",
996            (m->m_flags & M_PKTHDR) != 0 ? ", H" : ""
997          );
998
999          /* Copy fragment to buffer in Ethernet RAM */
1000          memcpy(frame_buffer, fragment_start, fragment_length);
1001
1002          if ((ctrl & ETH_TX_CTRL_LAST) != 0) {
1003            /* Finalize descriptor */
1004            desc [produce_index].control = (ctrl & ~ETH_TX_CTRL_SIZE_MASK)
1005              | (new_frame_length - 1);
1006
1007            LPC_ETH_PRINTF(
1008              "tx: %02" PRIu32 ": %" PRIu32 "\n",
1009              produce_index,
1010              new_frame_length
1011            );
1012
1013            /* Cache flush of data */
1014            rtems_cache_flush_multiple_data_lines(
1015              (const void *) desc [produce_index].start,
1016              new_frame_length
1017            );
1018
1019            /* Cache flush of descriptor  */
1020            rtems_cache_flush_multiple_data_lines
1021              ((void *)&desc [produce_index],
1022               sizeof(desc [0])
1023               );
1024
1025            /* Next produce index */
1026            produce_index = p;
1027
1028            /* Update the produce index */
1029            lpc_eth->txproduceindex = produce_index;
1030
1031            /* Fresh frame length and buffer start */
1032            frame_length = 0;
1033            frame_buffer = (char *) desc [produce_index].start;
1034
1035            /* Increment transmitted frames counter */
1036            ++e->transmitted_frames;
1037          } else {
1038            /* New frame length */
1039            frame_length = new_frame_length;
1040
1041            /* Update current frame buffer start */
1042            frame_buffer += fragment_length;
1043          }
1044
1045          /* Free mbuf and get next */
1046          m = m_free(m);
1047        #endif
1048      } else {
1049        /* Nothing to transmit */
1050        break;
1051      }
1052    }
1053
1054    /* No more fragments? */
1055    if (m == NULL) {
1056      /* Interface is now inactive */
1057      ifp->if_flags &= ~IFF_OACTIVE;
1058    } else {
1059      LPC_ETH_PRINTF("tx: enable interrupts\n");
1060
1061      /* Enable transmit interrupts */
1062      lpc_eth_enable_transmit_interrupts();
1063    }
1064  }
1065
1066cleanup:
1067
1068  /* Clear task ID */
1069  e->transmit_task = RTEMS_ID_NONE;
1070
1071  /* Release network semaphore */
1072  rtems_bsdnet_semaphore_release();
1073
1074  /* Terminate self */
1075  (void) rtems_task_delete(RTEMS_SELF);
1076}
1077
1078static void lpc_eth_mdio_wait_for_not_busy(void)
1079{
1080  while ((lpc_eth->mind & ETH_MIND_BUSY) != 0) {
1081    rtems_task_wake_after(2);
1082  }
1083}
1084
1085static uint32_t lpc_eth_mdio_read_anlpar(void)
1086{
1087  uint32_t madr = ETH_MADR_REG(MII_ANLPAR) | ETH_MADR_PHY(DEFAULT_PHY);
1088  uint32_t anlpar = 0;
1089
1090  if (lpc_eth->madr != madr) {
1091    lpc_eth->madr = madr;
1092  }
1093
1094  if (lpc_eth->mcmd != ETH_MCMD_READ) {
1095    lpc_eth->mcmd = 0;
1096    lpc_eth->mcmd = ETH_MCMD_READ;
1097  }
1098
1099  lpc_eth_mdio_wait_for_not_busy();
1100
1101  anlpar = lpc_eth->mrdd;
1102
1103  /* Start next read */
1104  lpc_eth->mcmd = 0;
1105  lpc_eth->mcmd = ETH_MCMD_READ;
1106
1107  return anlpar;
1108}
1109
1110static int lpc_eth_mdio_read(
1111  int phy __attribute__((unused)),
1112  void *arg __attribute__((unused)),
1113  unsigned reg,
1114  uint32_t *val
1115)
1116{
1117  int eno = 0;
1118
1119  if (phy == -1 || phy == 0) {
1120    lpc_eth->madr = ETH_MADR_REG(reg) | ETH_MADR_PHY(DEFAULT_PHY);
1121    lpc_eth->mcmd = 0;
1122    lpc_eth->mcmd = ETH_MCMD_READ;
1123    lpc_eth_mdio_wait_for_not_busy();
1124    *val = lpc_eth->mrdd;
1125  } else {
1126    eno = EINVAL;
1127  }
1128
1129  return eno;
1130}
1131
1132static int lpc_eth_mdio_write(
1133  int phy __attribute__((unused)),
1134  void *arg __attribute__((unused)),
1135  unsigned reg,
1136  uint32_t val
1137)
1138{
1139  int eno = 0;
1140
1141  if (phy == -1 || phy == 0) {
1142    lpc_eth->madr = ETH_MADR_REG(reg) | ETH_MADR_PHY(DEFAULT_PHY);
1143    lpc_eth->mwtd = val;
1144    lpc_eth_mdio_wait_for_not_busy();
1145  } else {
1146    eno = EINVAL;
1147  }
1148
1149  return eno;
1150}
1151
1152static void lpc_eth_interface_init(void *arg)
1153{
1154  rtems_status_code sc = RTEMS_SUCCESSFUL;
1155  lpc_eth_driver_entry *e = (lpc_eth_driver_entry *) arg;
1156  struct ifnet *ifp = &e->arpcom.ac_if;
1157
1158  LPC_ETH_PRINTF("%s\n", __func__);
1159
1160  if (e->state == LPC_ETH_INITIALIZED) {
1161    lpc_eth_config_module_enable();
1162
1163    /* Soft reset */
1164
1165    /* Do soft reset */
1166    lpc_eth->command = 0x38;
1167    lpc_eth->mac1 = 0xcf00;
1168    lpc_eth->mac1 = 0x0;
1169
1170    /* Initialize PHY */
1171    lpc_eth->mcfg = ETH_MCFG_CLOCK_SELECT(0x7);
1172    /* TODO */
1173
1174    /* Reinitialize registers */
1175    lpc_eth->mac2 = 0x31;
1176    lpc_eth->ipgt = 0x15;
1177    lpc_eth->ipgr = 0x12;
1178    lpc_eth->clrt = 0x370f;
1179    lpc_eth->maxf = 0x0600;
1180    lpc_eth->supp = ETH_SUPP_SPEED;
1181    lpc_eth->test = 0;
1182    #ifdef LPC_ETH_CONFIG_RMII
1183      lpc_eth->command = 0x0600;
1184    #else
1185      lpc_eth->command = 0x0400;
1186    #endif
1187    lpc_eth->intenable = 0;
1188    lpc_eth->intclear = 0x30ff;
1189    lpc_eth->powerdown = 0;
1190
1191    /* MAC address */
1192    lpc_eth->sa0 = ((uint32_t) e->arpcom.ac_enaddr [5] << 8)
1193      | (uint32_t) e->arpcom.ac_enaddr [4];
1194    lpc_eth->sa1 = ((uint32_t) e->arpcom.ac_enaddr [3] << 8)
1195      | (uint32_t) e->arpcom.ac_enaddr [2];
1196    lpc_eth->sa2 = ((uint32_t) e->arpcom.ac_enaddr [1] << 8)
1197      | (uint32_t) e->arpcom.ac_enaddr [0];
1198
1199    /* Enable receiver */
1200    lpc_eth->mac1 = 0x03;
1201
1202    /* Start receive task */
1203    if (e->receive_task == RTEMS_ID_NONE) {
1204      e->receive_task = rtems_bsdnet_newproc(
1205        "ntrx",
1206        4096,
1207        lpc_eth_receive_task,
1208        e
1209      );
1210      sc = rtems_event_send(e->receive_task, LPC_ETH_EVENT_INITIALIZE);
1211      RTEMS_SYSLOG_ERROR_SC(sc, "send receive initialize event");
1212    }
1213
1214    /* Start transmit task */
1215    if (e->transmit_task == RTEMS_ID_NONE) {
1216      e->transmit_task = rtems_bsdnet_newproc(
1217        "nttx",
1218        4096,
1219        lpc_eth_transmit_task,
1220        e
1221      );
1222      sc = rtems_event_send(e->transmit_task, LPC_ETH_EVENT_INITIALIZE);
1223      RTEMS_SYSLOG_ERROR_SC(sc, "send transmit initialize event");
1224    }
1225
1226    /* Change state */
1227    if (
1228      e->receive_task != RTEMS_ID_NONE && e->transmit_task != RTEMS_ID_NONE
1229    ) {
1230      e->state = LPC_ETH_STARTED;
1231    }
1232  }
1233
1234  if (e->state == LPC_ETH_STARTED) {
1235    /* Enable fatal interrupts */
1236    lpc_eth->intenable = ETH_INT_RX_OVERRUN | ETH_INT_TX_UNDERRUN;
1237
1238    /* Enable promiscous mode */
1239    lpc_eth_enable_promiscous_mode((ifp->if_flags & IFF_PROMISC) != 0);
1240
1241    /* Start watchdog timer */
1242    ifp->if_timer = 1;
1243
1244    /* Set interface to running state */
1245    ifp->if_flags |= IFF_RUNNING;
1246
1247    /* Change state */
1248    e->state = LPC_ETH_RUNNING;
1249  }
1250}
1251
1252static void lpc_eth_interface_stats(lpc_eth_driver_entry *e)
1253{
1254  int media = IFM_MAKEWORD(0, 0, 0, 0);
1255  int eno = rtems_mii_ioctl(&e->mdio, e, SIOCGIFMEDIA, &media);
1256
1257  rtems_bsdnet_semaphore_release();
1258
1259  if (eno == 0) {
1260    rtems_ifmedia2str(media, NULL, 0);
1261    printf("\n");
1262  }
1263
1264  printf("received frames:                     %u\n", e->received_frames);
1265  printf("receive interrupts:                  %u\n", e->receive_interrupts);
1266  printf("transmitted frames:                  %u\n", e->transmitted_frames);
1267  printf("transmit interrupts:                 %u\n", e->transmit_interrupts);
1268  printf("receive overrun errors:              %u\n", e->receive_overrun_errors);
1269  printf("receive fragment errors:             %u\n", e->receive_fragment_errors);
1270  printf("receive CRC errors:                  %u\n", e->receive_crc_errors);
1271  printf("receive symbol errors:               %u\n", e->receive_symbol_errors);
1272  printf("receive length errors:               %u\n", e->receive_length_errors);
1273  printf("receive alignment errors:            %u\n", e->receive_alignment_errors);
1274  printf("receive no descriptor errors:        %u\n", e->receive_no_descriptor_errors);
1275  printf("receive fatal errors:                %u\n", e->receive_fatal_errors);
1276  printf("transmit underrun errors:            %u\n", e->transmit_underrun_errors);
1277  printf("transmit late collision errors:      %u\n", e->transmit_late_collision_errors);
1278  printf("transmit excessive collision errors: %u\n", e->transmit_excessive_collision_errors);
1279  printf("transmit excessive defer errors:     %u\n", e->transmit_excessive_defer_errors);
1280  printf("transmit no descriptor errors:       %u\n", e->transmit_no_descriptor_errors);
1281  printf("transmit overflow errors:            %u\n", e->transmit_overflow_errors);
1282  printf("transmit fatal errors:               %u\n", e->transmit_fatal_errors);
1283
1284  rtems_bsdnet_semaphore_obtain();
1285}
1286
1287static int lpc_eth_interface_ioctl(
1288  struct ifnet *ifp,
1289  ioctl_command_t command,
1290  caddr_t data
1291)
1292{
1293  lpc_eth_driver_entry *e = (lpc_eth_driver_entry *) ifp->if_softc;
1294  int rv = 0;
1295
1296  LPC_ETH_PRINTF("%s\n", __func__);
1297
1298  switch (command)  {
1299    case SIOCGIFMEDIA:
1300    case SIOCSIFMEDIA:
1301      rtems_mii_ioctl(&e->mdio, e, command, (int *) data);
1302      break;
1303    case SIOCGIFADDR:
1304    case SIOCSIFADDR:
1305      ether_ioctl(ifp, command, data);
1306      break;
1307    case SIOCSIFFLAGS:
1308      if (ifp->if_flags & IFF_RUNNING) {
1309        /* TODO: off */
1310      }
1311      if (ifp->if_flags & IFF_UP) {
1312        ifp->if_flags |= IFF_RUNNING;
1313        /* TODO: init */
1314      }
1315      break;
1316    case SIO_RTEMS_SHOW_STATS:
1317      lpc_eth_interface_stats(e);
1318      break;
1319    default:
1320      rv = EINVAL;
1321      break;
1322  }
1323
1324  return rv;
1325}
1326
1327static void lpc_eth_interface_start(struct ifnet *ifp)
1328{
1329  rtems_status_code sc = RTEMS_SUCCESSFUL;
1330  lpc_eth_driver_entry *e = (lpc_eth_driver_entry *) ifp->if_softc;
1331
1332  ifp->if_flags |= IFF_OACTIVE;
1333
1334  sc = rtems_event_send(e->transmit_task, LPC_ETH_EVENT_START);
1335  RTEMS_SYSLOG_ERROR_SC(sc, "send transmit start event");
1336}
1337
1338static void lpc_eth_interface_watchdog(struct ifnet *ifp __attribute__((unused)))
1339{
1340  lpc_eth_driver_entry *e = (lpc_eth_driver_entry *) ifp->if_softc;
1341  uint32_t anlpar = lpc_eth_mdio_read_anlpar();
1342
1343  if (e->anlpar != anlpar) {
1344    bool full_duplex = false;
1345    bool speed = false;
1346
1347    e->anlpar = anlpar;
1348
1349    if ((anlpar & ANLPAR_TX_FD) != 0) {
1350      full_duplex = true;
1351      speed = true;
1352    } else if ((anlpar & ANLPAR_T4) != 0) {
1353      speed = true;
1354    } else if ((anlpar & ANLPAR_TX) != 0) {
1355      speed = true;
1356    } else if ((anlpar & ANLPAR_10_FD) != 0) {
1357      full_duplex = true;
1358    }
1359
1360    if (full_duplex) {
1361      lpc_eth->mac2 |= ETH_MAC2_FULL_DUPLEX;
1362    } else {
1363      lpc_eth->mac2 &= ~ETH_MAC2_FULL_DUPLEX;
1364    }
1365
1366    if (speed) {
1367      lpc_eth->supp |= ETH_SUPP_SPEED;
1368    } else {
1369      lpc_eth->supp &= ~ETH_SUPP_SPEED;
1370    }
1371  }
1372
1373  ifp->if_timer = WATCHDOG_TIMEOUT;
1374}
1375
1376static unsigned lpc_eth_fixup_unit_count(int count, int default_value, int max)
1377{
1378  if (count <= 0) {
1379    count = default_value;
1380  } else if (count > max) {
1381    count = max;
1382  }
1383
1384  return LPC_ETH_CONFIG_UNIT_MULTIPLE
1385    + (((unsigned) count - 1U) & ~(LPC_ETH_CONFIG_UNIT_MULTIPLE - 1U));
1386}
1387
1388static int lpc_eth_attach(struct rtems_bsdnet_ifconfig *config)
1389{
1390  rtems_status_code sc = RTEMS_SUCCESSFUL;
1391  lpc_eth_driver_entry *e = &lpc_eth_driver_data;
1392  struct ifnet *ifp = &e->arpcom.ac_if;
1393  char *unit_name = NULL;
1394  int unit_index = rtems_bsdnet_parse_driver_name(config, &unit_name);
1395  size_t table_area_size = 0;
1396  char *table_area = NULL;
1397  char *table_location = NULL;
1398
1399  /* Check parameter */
1400  if (unit_index < 0) {
1401    RTEMS_SYSLOG_ERROR("parse error for interface name\n");
1402    return 0;
1403  }
1404  if (unit_index != 0) {
1405    RTEMS_DO_CLEANUP(cleanup, "unexpected unit number");
1406  }
1407  if (config->hardware_address == NULL) {
1408    RTEMS_DO_CLEANUP(cleanup, "MAC address missing");
1409  }
1410  if (e->state != LPC_ETH_NOT_INITIALIZED) {
1411    RTEMS_DO_CLEANUP(cleanup, "already attached");
1412  }
1413
1414  /* MDIO */
1415  e->mdio.mdio_r = lpc_eth_mdio_read;
1416  e->mdio.mdio_w = lpc_eth_mdio_write;
1417  e->mdio.has_gmii = 0;
1418  e->anlpar = 0;
1419
1420  /* Interrupt number */
1421  config->irno = LPC_ETH_CONFIG_INTERRUPT;
1422
1423  /* Device control */
1424  config->drv_ctrl = e;
1425
1426  /* Receive unit count */
1427  e->rx_unit_count = lpc_eth_fixup_unit_count(
1428    config->rbuf_count,
1429    LPC_ETH_CONFIG_RX_UNIT_COUNT_DEFAULT,
1430    LPC_ETH_CONFIG_RX_UNIT_COUNT_MAX
1431  );
1432  config->rbuf_count = (int) e->rx_unit_count;
1433
1434  /* Transmit unit count */
1435  e->tx_unit_count = lpc_eth_fixup_unit_count(
1436    config->xbuf_count,
1437    LPC_ETH_CONFIG_TX_UNIT_COUNT_DEFAULT,
1438    LPC_ETH_CONFIG_TX_UNIT_COUNT_MAX
1439  );
1440  config->xbuf_count = (int) e->tx_unit_count;
1441
1442  /* Disable interrupts */
1443  lpc_eth->intenable = 0;
1444
1445  /* Install interrupt handler */
1446  sc = rtems_interrupt_handler_install(
1447    config->irno,
1448    "Ethernet",
1449    RTEMS_INTERRUPT_UNIQUE,
1450    lpc_eth_interrupt_handler,
1451    e
1452  );
1453  RTEMS_CLEANUP_SC(sc, cleanup, "install interrupt handler");
1454
1455  /* Copy MAC address */
1456  memcpy(e->arpcom.ac_enaddr, config->hardware_address, ETHER_ADDR_LEN);
1457
1458  /* Allocate and clear table area */
1459  table_area_size =
1460    e->rx_unit_count
1461      * (sizeof(lpc_eth_transfer_descriptor)
1462        + sizeof(lpc_eth_receive_status)
1463        + sizeof(struct mbuf *))
1464    + e->tx_unit_count
1465      * (sizeof(lpc_eth_transfer_descriptor)
1466        + sizeof(uint32_t)
1467        + LPC_ETH_CONFIG_TX_BUF_SIZE);
1468  table_area = lpc_eth_config_alloc_table_area(table_area_size);
1469  if (table_area == NULL) {
1470    RTEMS_DO_CLEANUP(cleanup, "no memory for table area");
1471  }
1472  memset(table_area, 0, table_area_size);
1473
1474  table_location = table_area;
1475
1476  /*
1477   * The receive status table must be the first one since it has the strictest
1478   * alignment requirements.
1479   */
1480  e->rx_status_table = (volatile lpc_eth_receive_status *) table_location;
1481  table_location += e->rx_unit_count * sizeof(e->rx_status_table [0]);
1482
1483  e->rx_desc_table = (volatile lpc_eth_transfer_descriptor *) table_location;
1484  table_location += e->rx_unit_count * sizeof(e->rx_desc_table [0]);
1485
1486  e->rx_mbuf_table = (struct mbuf **) table_location;
1487  table_location += e->rx_unit_count * sizeof(e->rx_mbuf_table [0]);
1488
1489  e->tx_desc_table = (volatile lpc_eth_transfer_descriptor *) table_location;
1490  table_location += e->tx_unit_count * sizeof(e->tx_desc_table [0]);
1491
1492  e->tx_status_table = (volatile uint32_t *) table_location;
1493  table_location += e->tx_unit_count * sizeof(e->tx_status_table [0]);
1494
1495  e->tx_buf_table = table_location;
1496
1497  /* Set interface data */
1498  ifp->if_softc = e;
1499  ifp->if_unit = (short) unit_index;
1500  ifp->if_name = unit_name;
1501  ifp->if_mtu = (config->mtu > 0) ? (u_long) config->mtu : ETHERMTU;
1502  ifp->if_init = lpc_eth_interface_init;
1503  ifp->if_ioctl = lpc_eth_interface_ioctl;
1504  ifp->if_start = lpc_eth_interface_start;
1505  ifp->if_output = ether_output;
1506  ifp->if_watchdog = lpc_eth_interface_watchdog;
1507  ifp->if_flags = config->ignore_broadcast ? 0 : IFF_BROADCAST;
1508  ifp->if_snd.ifq_maxlen = ifqmaxlen;
1509  ifp->if_timer = 0;
1510
1511  /* Change status */
1512  e->state = LPC_ETH_INITIALIZED;
1513
1514  /* Attach the interface */
1515  if_attach(ifp);
1516  ether_ifattach(ifp);
1517
1518  return 1;
1519
1520cleanup:
1521
1522  lpc_eth_config_free_table_area(table_area);
1523
1524  /* FIXME: Type */
1525  free(unit_name, (int) 0xdeadbeef);
1526
1527  return 0;
1528}
1529
1530static int lpc_eth_detach(
1531  struct rtems_bsdnet_ifconfig *config __attribute__((unused))
1532)
1533{
1534  /* FIXME: Detach the interface from the upper layers? */
1535
1536  /* Module soft reset */
1537  lpc_eth->command = 0x38;
1538  lpc_eth->mac1 = 0xcf00;
1539
1540  /* FIXME: More cleanup */
1541
1542  return 0;
1543}
1544
1545int lpc_eth_attach_detach(
1546  struct rtems_bsdnet_ifconfig *config,
1547  int attaching
1548)
1549{
1550  /* FIXME: Return value */
1551
1552  if (attaching) {
1553    return lpc_eth_attach(config);
1554  } else {
1555    return lpc_eth_detach(config);
1556  }
1557}
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