source: rtems/c/src/lib/libbsp/arm/shared/lpc/include/lpc-timer.h @ 991fdb33

4.115
Last change on this file since 991fdb33 was c499856, checked in by Chris Johns <chrisj@…>, on 03/20/14 at 21:10:47

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1/**
2 * @file
3 *
4 * @ingroup lpc_timer
5 *
6 * @brief Timer API.
7 */
8
9/*
10 * Copyright (c) 2009
11 * embedded brains GmbH
12 * Obere Lagerstr. 30
13 * D-82178 Puchheim
14 * Germany
15 * <rtems@embedded-brains.de>
16 *
17 * The license and distribution terms for this file may be
18 * found in the file LICENSE in this distribution or at
19 * http://www.rtems.org/license/LICENSE.
20 */
21
22#ifndef LIBBSP_ARM_SHARED_LPC_TIMER_H
23#define LIBBSP_ARM_SHARED_LPC_TIMER_H
24
25#include <stdint.h>
26
27#ifdef __cplusplus
28extern "C" {
29#endif
30
31/**
32 * @defgroup lpc_timer Timer Support
33 *
34 * @ingroup arm_lpc24xx
35 * @ingroup arm_lpc32xx
36 *
37 * @brief Timer support.
38 *
39 * @{
40 */
41
42/**
43 * @name Interrupt Register Defines
44 *
45 * @{
46 */
47
48#define LPC_TIMER_IR_MR0 0x1U
49#define LPC_TIMER_IR_MR1 0x2U
50#define LPC_TIMER_IR_MR2 0x4U
51#define LPC_TIMER_IR_MR3 0x8U
52#define LPC_TIMER_IR_CR0 0x10U
53#define LPC_TIMER_IR_CR1 0x20U
54#define LPC_TIMER_IR_CR2 0x40U
55#define LPC_TIMER_IR_CR3 0x80U
56#define LPC_TIMER_IR_ALL 0xffU
57
58/** @} */
59
60/**
61 * @name Timer Control Register Defines
62 *
63 * @{
64 */
65
66#define LPC_TIMER_TCR_EN 0x1U
67#define LPC_TIMER_TCR_RST 0x2U
68
69/** @} */
70
71/**
72 * @name Match Control Register Defines
73 *
74 * @{
75 */
76
77#define LPC_TIMER_MCR_MR0_INTR 0x1U
78#define LPC_TIMER_MCR_MR0_RST 0x2U
79#define LPC_TIMER_MCR_MR0_STOP 0x4U
80#define LPC_TIMER_MCR_MR1_INTR 0x8U
81#define LPC_TIMER_MCR_MR1_RST 0x10U
82#define LPC_TIMER_MCR_MR1_STOP 0x20U
83#define LPC_TIMER_MCR_MR2_INTR 0x40U
84#define LPC_TIMER_MCR_MR2_RST 0x80U
85#define LPC_TIMER_MCR_MR2_STOP 0x100U
86#define LPC_TIMER_MCR_MR3_INTR 0x200U
87#define LPC_TIMER_MCR_MR3_RST 0x400U
88#define LPC_TIMER_MCR_MR3_STOP 0x800U
89
90/** @} */
91
92/**
93 * @name Capture Control Register Defines
94 *
95 * @{
96 */
97
98#define LPC_TIMER_CCR_CAP0_RE 0x1U
99#define LPC_TIMER_CCR_CAP0_FE 0x2U
100#define LPC_TIMER_CCR_CAP0_INTR 0x4U
101#define LPC_TIMER_CCR_CAP1_RE 0x8U
102#define LPC_TIMER_CCR_CAP1_FE 0x10U
103#define LPC_TIMER_CCR_CAP1_INTR 0x20U
104#define LPC_TIMER_CCR_CAP2_RE 0x40U
105#define LPC_TIMER_CCR_CAP2_FE 0x80U
106#define LPC_TIMER_CCR_CAP2_INTR 0x100U
107#define LPC_TIMER_CCR_CAP3_RE 0x200U
108#define LPC_TIMER_CCR_CAP3_FE 0x400U
109#define LPC_TIMER_CCR_CAP3_INTR 0x800U
110
111/** @} */
112
113/**
114 * @name External Match Register Defines
115 *
116 * @{
117 */
118
119#define LPC_TIMER_EMR_EM0_RE 0x1U
120#define LPC_TIMER_EMR_EM1_FE 0x2U
121#define LPC_TIMER_EMR_EM2_INTR 0x4U
122#define LPC_TIMER_EMR_EM3_RE 0x8U
123#define LPC_TIMER_EMR_EMC0_FE 0x10U
124#define LPC_TIMER_EMR_EMC1_INTR 0x20U
125#define LPC_TIMER_EMR_EMC2_RE 0x40U
126#define LPC_TIMER_EMR_EMC3_FE 0x80U
127
128/** @} */
129
130/**
131 * @brief Timer control block.
132 */
133typedef struct {
134  uint32_t ir;
135  uint32_t tcr;
136  uint32_t tc;
137  uint32_t pr;
138  uint32_t pc;
139  uint32_t mcr;
140  uint32_t mr0;
141  uint32_t mr1;
142  uint32_t mr2;
143  uint32_t mr3;
144  uint32_t ccr;
145  uint32_t cr0;
146  uint32_t cr1;
147  uint32_t cr2;
148  uint32_t cr3;
149  uint32_t emr;
150  uint32_t ctcr;
151} lpc_timer;
152
153/** @} */
154
155#ifdef __cplusplus
156}
157#endif /* __cplusplus */
158
159#endif /* LIBBSP_ARM_SHARED_LPC_TIMER_H */
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