[c468f18b] | 1 | /** |
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| 2 | * @file |
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| 3 | * |
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[7a6f8d0] | 4 | * @ingroup lpc_timer |
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[c468f18b] | 5 | * |
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| 6 | * @brief Timer API. |
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| 7 | */ |
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| 8 | |
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| 9 | /* |
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| 10 | * Copyright (c) 2009 |
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| 11 | * embedded brains GmbH |
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| 12 | * Obere Lagerstr. 30 |
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| 13 | * D-82178 Puchheim |
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| 14 | * Germany |
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| 15 | * <rtems@embedded-brains.de> |
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| 16 | * |
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| 17 | * The license and distribution terms for this file may be |
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| 18 | * found in the file LICENSE in this distribution or at |
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| 19 | * http://www.rtems.com/license/LICENSE. |
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| 20 | */ |
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| 21 | |
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| 22 | #ifndef LIBBSP_ARM_SHARED_LPC_TIMER_H |
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| 23 | #define LIBBSP_ARM_SHARED_LPC_TIMER_H |
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| 24 | |
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| 25 | #include <stdint.h> |
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| 26 | |
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| 27 | #ifdef __cplusplus |
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| 28 | extern "C" { |
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| 29 | #endif |
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| 30 | |
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[7a6f8d0] | 31 | /** |
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| 32 | * @defgroup lpc_timer Timer Support |
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| 33 | * |
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| 34 | * @ingroup lpc |
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| 35 | * |
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| 36 | * @brief Timer support. |
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| 37 | * |
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| 38 | * @{ |
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| 39 | */ |
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| 40 | |
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| 41 | /** |
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| 42 | * @name Interrupt Register Defines |
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| 43 | * |
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| 44 | * @{ |
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| 45 | */ |
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| 46 | |
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[c468f18b] | 47 | #define LPC_TIMER_IR_MR0 0x1U |
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| 48 | #define LPC_TIMER_IR_MR1 0x2U |
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| 49 | #define LPC_TIMER_IR_MR2 0x4U |
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| 50 | #define LPC_TIMER_IR_MR3 0x8U |
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| 51 | #define LPC_TIMER_IR_CR0 0x10U |
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| 52 | #define LPC_TIMER_IR_CR1 0x20U |
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| 53 | #define LPC_TIMER_IR_CR2 0x40U |
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| 54 | #define LPC_TIMER_IR_CR3 0x80U |
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| 55 | #define LPC_TIMER_IR_ALL 0xffU |
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| 56 | |
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[7a6f8d0] | 57 | /** @} */ |
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| 58 | |
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| 59 | /** |
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| 60 | * @name Timer Control Register Defines |
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| 61 | * |
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| 62 | * @{ |
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| 63 | */ |
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| 64 | |
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[c468f18b] | 65 | #define LPC_TIMER_TCR_EN 0x1U |
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| 66 | #define LPC_TIMER_TCR_RST 0x2U |
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| 67 | |
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[7a6f8d0] | 68 | /** @} */ |
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| 69 | |
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| 70 | /** |
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| 71 | * @name Match Control Register Defines |
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| 72 | * |
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| 73 | * @{ |
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| 74 | */ |
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| 75 | |
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[c468f18b] | 76 | #define LPC_TIMER_MCR_MR0_INTR 0x1U |
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| 77 | #define LPC_TIMER_MCR_MR0_RST 0x2U |
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| 78 | #define LPC_TIMER_MCR_MR0_STOP 0x4U |
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| 79 | #define LPC_TIMER_MCR_MR1_INTR 0x8U |
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| 80 | #define LPC_TIMER_MCR_MR1_RST 0x10U |
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| 81 | #define LPC_TIMER_MCR_MR1_STOP 0x20U |
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| 82 | #define LPC_TIMER_MCR_MR2_INTR 0x40U |
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| 83 | #define LPC_TIMER_MCR_MR2_RST 0x80U |
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| 84 | #define LPC_TIMER_MCR_MR2_STOP 0x100U |
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| 85 | #define LPC_TIMER_MCR_MR3_INTR 0x200U |
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| 86 | #define LPC_TIMER_MCR_MR3_RST 0x400U |
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| 87 | #define LPC_TIMER_MCR_MR3_STOP 0x800U |
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| 88 | |
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[7a6f8d0] | 89 | /** @} */ |
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| 90 | |
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| 91 | /** |
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| 92 | * @name Capture Control Register Defines |
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| 93 | * |
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| 94 | * @{ |
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| 95 | */ |
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| 96 | |
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[c468f18b] | 97 | #define LPC_TIMER_CCR_CAP0_RE 0x1U |
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| 98 | #define LPC_TIMER_CCR_CAP0_FE 0x2U |
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| 99 | #define LPC_TIMER_CCR_CAP0_INTR 0x4U |
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| 100 | #define LPC_TIMER_CCR_CAP1_RE 0x8U |
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| 101 | #define LPC_TIMER_CCR_CAP1_FE 0x10U |
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| 102 | #define LPC_TIMER_CCR_CAP1_INTR 0x20U |
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| 103 | #define LPC_TIMER_CCR_CAP2_RE 0x40U |
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| 104 | #define LPC_TIMER_CCR_CAP2_FE 0x80U |
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| 105 | #define LPC_TIMER_CCR_CAP2_INTR 0x100U |
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| 106 | #define LPC_TIMER_CCR_CAP3_RE 0x200U |
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| 107 | #define LPC_TIMER_CCR_CAP3_FE 0x400U |
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| 108 | #define LPC_TIMER_CCR_CAP3_INTR 0x800U |
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| 109 | |
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[7a6f8d0] | 110 | /** @} */ |
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| 111 | |
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| 112 | /** |
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| 113 | * @name External Match Register Defines |
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| 114 | * |
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| 115 | * @{ |
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| 116 | */ |
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| 117 | |
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[c468f18b] | 118 | #define LPC_TIMER_EMR_EM0_RE 0x1U |
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| 119 | #define LPC_TIMER_EMR_EM1_FE 0x2U |
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| 120 | #define LPC_TIMER_EMR_EM2_INTR 0x4U |
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| 121 | #define LPC_TIMER_EMR_EM3_RE 0x8U |
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| 122 | #define LPC_TIMER_EMR_EMC0_FE 0x10U |
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| 123 | #define LPC_TIMER_EMR_EMC1_INTR 0x20U |
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| 124 | #define LPC_TIMER_EMR_EMC2_RE 0x40U |
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| 125 | #define LPC_TIMER_EMR_EMC3_FE 0x80U |
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| 126 | |
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[7a6f8d0] | 127 | /** @} */ |
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| 128 | |
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| 129 | /** |
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| 130 | * @brief Timer control block. |
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| 131 | */ |
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[c468f18b] | 132 | typedef struct { |
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| 133 | uint32_t ir; |
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| 134 | uint32_t tcr; |
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| 135 | uint32_t tc; |
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| 136 | uint32_t pr; |
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| 137 | uint32_t pc; |
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| 138 | uint32_t mcr; |
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| 139 | uint32_t mr0; |
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| 140 | uint32_t mr1; |
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| 141 | uint32_t mr2; |
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| 142 | uint32_t mr3; |
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| 143 | uint32_t ccr; |
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| 144 | uint32_t cr0; |
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| 145 | uint32_t cr1; |
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| 146 | uint32_t cr2; |
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| 147 | uint32_t cr3; |
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| 148 | uint32_t emr; |
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| 149 | uint32_t ctcr; |
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| 150 | } lpc_timer; |
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| 151 | |
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[7a6f8d0] | 152 | /** @} */ |
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| 153 | |
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[c468f18b] | 154 | #ifdef __cplusplus |
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| 155 | } |
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| 156 | #endif /* __cplusplus */ |
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| 157 | |
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| 158 | #endif /* LIBBSP_ARM_SHARED_LPC_TIMER_H */ |
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