1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup lpc_lcd |
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5 | * |
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6 | * @brief LCD support API. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2011 embedded brains GmbH. All rights reserved. |
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11 | * |
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12 | * embedded brains GmbH |
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13 | * Obere Lagerstr. 30 |
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14 | * 82178 Puchheim |
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15 | * Germany |
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16 | * <rtems@embedded-brains.de> |
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17 | * |
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18 | * The license and distribution terms for this file may be |
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19 | * found in the file LICENSE in this distribution or at |
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20 | * http://www.rtems.org/license/LICENSE. |
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21 | */ |
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22 | |
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23 | #ifndef LIBBSP_ARM_SHARED_LPC_LCD_H |
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24 | #define LIBBSP_ARM_SHARED_LPC_LCD_H |
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25 | |
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26 | #include <bsp/utility.h> |
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27 | |
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28 | #ifdef __cplusplus |
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29 | extern "C" { |
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30 | #endif |
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31 | |
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32 | /** |
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33 | * @defgroup lpc_lcd LCD Support |
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34 | * |
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35 | * @ingroup lpc |
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36 | * @ingroup arm_lpc32xx |
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37 | * |
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38 | * @brief LCD support. |
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39 | * |
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40 | * @{ |
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41 | */ |
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42 | |
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43 | typedef struct { |
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44 | uint8_t img [1024]; |
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45 | uint32_t ctrl; |
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46 | uint32_t cfg; |
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47 | uint32_t pal0; |
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48 | uint32_t pal1; |
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49 | uint32_t xy; |
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50 | uint32_t clip; |
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51 | uint32_t intmsk; |
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52 | uint32_t intclr; |
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53 | uint32_t intraw; |
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54 | uint32_t intstat; |
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55 | } lpc_cursor; |
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56 | |
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57 | typedef struct { |
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58 | uint32_t timh; |
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59 | uint32_t timv; |
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60 | uint32_t pol; |
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61 | uint32_t le; |
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62 | uint32_t upbase; |
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63 | uint32_t lpbase; |
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64 | uint32_t ctrl; |
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65 | uint32_t intmsk; |
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66 | uint32_t intraw; |
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67 | uint32_t intstat; |
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68 | uint32_t intclr; |
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69 | uint32_t upcurr; |
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70 | uint32_t lpcurr; |
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71 | uint8_t reserved_0 [0x200 - 0x034]; |
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72 | uint16_t pal [256]; |
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73 | uint8_t reserved_1 [0x800 - 0x400]; |
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74 | lpc_cursor crsr; |
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75 | } lpc_lcd; |
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76 | |
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77 | /** |
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78 | * @name LCD Configuration Register |
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79 | * |
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80 | * @{ |
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81 | */ |
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82 | |
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83 | #define LCD_CFG_CLKDIV(val) BSP_FLD32(val, 0, 4) |
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84 | #define LCD_CFG_HCLK_ENABLE BSP_BIT32(5) |
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85 | #define LCD_CFG_MODE_SELECT(val) BSP_FLD32(val, 6, 7) |
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86 | #define LCD_CFG_DISPLAY_TYPE BSP_BIT32(8) |
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87 | |
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88 | /** @} */ |
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89 | |
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90 | /** |
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91 | * @name LCD Horizontal Timing Register |
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92 | * |
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93 | * @{ |
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94 | */ |
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95 | |
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96 | #define LCD_TIMH_PPL(val) BSP_FLD32(val, 2, 7) |
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97 | #define LCD_TIMH_PPL_GET(reg) BSP_FLD32GET(reg, 2, 7) |
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98 | #define LCD_TIMH_HSW(val) BSP_FLD32(val, 8, 15) |
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99 | #define LCD_TIMH_HSW_GET(reg) BSP_FLD32GET(reg, 8, 15) |
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100 | #define LCD_TIMH_HFP(val) BSP_FLD32(val, 16, 23) |
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101 | #define LCD_TIMH_HFP_GET(reg) BSP_FLD32GET(reg, 16, 23) |
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102 | #define LCD_TIMH_HBP(val) BSP_FLD32(val, 24, 31) |
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103 | #define LCD_TIMH_HBP_GET(reg) BSP_FLD32GET(reg, 24, 31) |
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104 | |
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105 | /** @} */ |
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106 | |
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107 | /** |
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108 | * @name LCD Vertical Timing Register |
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109 | * |
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110 | * @{ |
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111 | */ |
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112 | |
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113 | #define LCD_TIMV_LPP(val) BSP_FLD32(val, 0, 9) |
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114 | #define LCD_TIMV_LPP_GET(reg) BSP_FLD32GET(reg, 0, 9) |
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115 | #define LCD_TIMV_VSW(val) BSP_FLD32(val, 10, 15) |
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116 | #define LCD_TIMV_VSW_GET(reg) BSP_FLD32GET(reg, 10, 15) |
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117 | #define LCD_TIMV_VFP(val) BSP_FLD32(val, 16, 23) |
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118 | #define LCD_TIMV_VFP_GET(reg) BSP_FLD32GET(reg, 16, 23) |
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119 | #define LCD_TIMV_VBP(val) BSP_FLD32(val, 24, 31) |
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120 | #define LCD_TIMV_VBP_GET(reg) BSP_FLD32GET(reg, 24, 31) |
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121 | |
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122 | /** @} */ |
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123 | |
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124 | /** |
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125 | * @name LCD Clock and Signal Polarity Register |
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126 | * |
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127 | * @{ |
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128 | */ |
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129 | |
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130 | #define LCD_POL_PCD_LO(val) BSP_FLD32(val, 0, 4) |
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131 | #define LCD_POL_PCD_LO_GET(reg) BSP_FLD32GET(reg, 0, 4) |
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132 | #define LCD_POL_CLKSEL BSP_BIT32(5) |
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133 | #define LCD_POL_ACB(val) BSP_FLD32(val, 6, 10) |
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134 | #define LCD_POL_ACB_GET(reg) BSP_FLD32GET(reg, 6, 10) |
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135 | #define LCD_POL_IVS BSP_BIT32(11) |
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136 | #define LCD_POL_IHS BSP_BIT32(12) |
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137 | #define LCD_POL_IPC BSP_BIT32(13) |
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138 | #define LCD_POL_IOE BSP_BIT32(14) |
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139 | #define LCD_POL_CPL(val) BSP_FLD32(val, 16, 25) |
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140 | #define LCD_POL_CPL_GET(reg) BSP_FLD32GET(reg, 16, 25) |
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141 | #define LCD_POL_BCD BSP_BIT32(26) |
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142 | #define LCD_POL_PCD_HI(val) BSP_FLD32(val, 27, 31) |
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143 | #define LCD_POL_PCD_HI_GET(reg) BSP_FLD32GET(reg, 27, 31) |
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144 | |
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145 | /** @} */ |
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146 | |
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147 | /** |
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148 | * @name LCD Line End Control Register |
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149 | * |
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150 | * @{ |
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151 | */ |
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152 | |
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153 | #define LCD_LE_LED(val) BSP_FLD32(val, 0, 6) |
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154 | #define LCD_LE_LEE BSP_BIT32(16) |
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155 | |
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156 | /** @} */ |
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157 | |
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158 | /** |
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159 | * @name LCD Control Register |
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160 | * |
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161 | * @{ |
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162 | */ |
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163 | |
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164 | #define LCD_CTRL_LCDEN BSP_BIT32(0) |
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165 | #define LCD_CTRL_LCDBPP(val) BSP_FLD32(val, 1, 3) |
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166 | #define LCD_CTRL_LCDBPP_GET(reg) BSP_FLD32GET(reg, 1, 3) |
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167 | #define LCD_CTRL_LCDBW BSP_BIT32(4) |
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168 | #define LCD_CTRL_LCDTFT BSP_BIT32(5) |
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169 | #define LCD_CTRL_LCDMONO8 BSP_BIT32(6) |
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170 | #define LCD_CTRL_LCDDUAL BSP_BIT32(7) |
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171 | #define LCD_CTRL_BGR BSP_BIT32(8) |
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172 | #define LCD_CTRL_BEBO BSP_BIT32(9) |
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173 | #define LCD_CTRL_BEPO BSP_BIT32(10) |
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174 | #define LCD_CTRL_LCDPWR BSP_BIT32(11) |
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175 | #define LCD_CTRL_LCDVCOMP(val) BSP_FLD32(val, 12, 13) |
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176 | #define LCD_CTRL_LCDVCOMP_GET(reg) BSP_FLD32GET(reg, 12, 13) |
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177 | #define LCD_CTRL_WATERMARK BSP_BIT32(16) |
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178 | |
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179 | /** @} */ |
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180 | |
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181 | /** |
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182 | * @name LCD Interrupt Registers |
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183 | * |
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184 | * @{ |
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185 | */ |
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186 | |
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187 | #define LCD_INT_FUF BSP_BIT32(1) |
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188 | #define LCD_INT_LNBU BSP_BIT32(2) |
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189 | #define LCD_INT_VCOMP BSP_BIT32(3) |
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190 | #define LCD_INT_BER BSP_BIT32(4) |
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191 | |
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192 | /** @} */ |
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193 | |
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194 | /** |
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195 | * @name LCD Color Palette Register |
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196 | * |
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197 | * @{ |
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198 | */ |
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199 | |
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200 | #define LCD_PAL_R(val) BSP_FLD16(val, 0, 4) |
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201 | #define LCD_PAL_G(val) BSP_FLD16(val, 5, 9) |
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202 | #define LCD_PAL_B(val) BSP_FLD16(val, 10, 14) |
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203 | #define LCD_PAL_I BSP_BIT16(15) |
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204 | |
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205 | /** @} */ |
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206 | |
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207 | /** @} */ |
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208 | |
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209 | #ifdef __cplusplus |
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210 | } |
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211 | #endif /* __cplusplus */ |
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212 | |
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213 | #endif /* LIBBSP_ARM_SHARED_LPC_LCD_H */ |
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