source: rtems/c/src/lib/libbsp/arm/shared/lpc/include/lpc-lcd.h @ 991fdb33

4.115
Last change on this file since 991fdb33 was c499856, checked in by Chris Johns <chrisj@…>, on Mar 20, 2014 at 9:10:47 PM

Change all references of rtems.com to rtems.org.

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File size: 4.4 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup lpc_lcd
5 *
6 * @brief LCD support API.
7 */
8
9/*
10 * Copyright (c) 2011 embedded brains GmbH.  All rights reserved.
11 *
12 *  embedded brains GmbH
13 *  Obere Lagerstr. 30
14 *  82178 Puchheim
15 *  Germany
16 *  <rtems@embedded-brains.de>
17 *
18 * The license and distribution terms for this file may be
19 * found in the file LICENSE in this distribution or at
20 * http://www.rtems.org/license/LICENSE.
21 */
22
23#ifndef LIBBSP_ARM_SHARED_LPC_LCD_H
24#define LIBBSP_ARM_SHARED_LPC_LCD_H
25
26#include <bsp/utility.h>
27
28#ifdef __cplusplus
29extern "C" {
30#endif
31
32/**
33 * @defgroup lpc_lcd LCD Support
34 *
35 * @ingroup lpc
36 * @ingroup arm_lpc32xx
37 *
38 * @brief LCD support.
39 *
40 * @{
41 */
42
43typedef struct {
44  uint8_t img [1024];
45  uint32_t ctrl;
46  uint32_t cfg;
47  uint32_t pal0;
48  uint32_t pal1;
49  uint32_t xy;
50  uint32_t clip;
51  uint32_t intmsk;
52  uint32_t intclr;
53  uint32_t intraw;
54  uint32_t intstat;
55} lpc_cursor;
56
57typedef struct {
58  uint32_t timh;
59  uint32_t timv;
60  uint32_t pol;
61  uint32_t le;
62  uint32_t upbase;
63  uint32_t lpbase;
64  uint32_t ctrl;
65  uint32_t intmsk;
66  uint32_t intraw;
67  uint32_t intstat;
68  uint32_t intclr;
69  uint32_t upcurr;
70  uint32_t lpcurr;
71  uint8_t reserved_0 [0x200 - 0x034];
72  uint16_t pal [256];
73  uint8_t reserved_1 [0x800 - 0x400];
74  lpc_cursor crsr;
75} lpc_lcd;
76
77/**
78 * @name LCD Configuration Register
79 *
80 * @{
81 */
82
83#define LCD_CFG_CLKDIV(val) BSP_FLD32(val, 0, 4)
84#define LCD_CFG_HCLK_ENABLE BSP_BIT32(5)
85#define LCD_CFG_MODE_SELECT(val) BSP_FLD32(val, 6, 7)
86#define LCD_CFG_DISPLAY_TYPE BSP_BIT32(8)
87
88/** @} */
89
90/**
91 * @name LCD Horizontal Timing Register
92 *
93 * @{
94 */
95
96#define LCD_TIMH_PPL(val) BSP_FLD32(val, 2, 7)
97#define LCD_TIMH_PPL_GET(reg) BSP_FLD32GET(reg, 2, 7)
98#define LCD_TIMH_HSW(val) BSP_FLD32(val, 8, 15)
99#define LCD_TIMH_HSW_GET(reg) BSP_FLD32GET(reg, 8, 15)
100#define LCD_TIMH_HFP(val) BSP_FLD32(val, 16, 23)
101#define LCD_TIMH_HFP_GET(reg) BSP_FLD32GET(reg, 16, 23)
102#define LCD_TIMH_HBP(val) BSP_FLD32(val, 24, 31)
103#define LCD_TIMH_HBP_GET(reg) BSP_FLD32GET(reg, 24, 31)
104
105/** @} */
106
107/**
108 * @name LCD Vertical Timing Register
109 *
110 * @{
111 */
112
113#define LCD_TIMV_LPP(val) BSP_FLD32(val, 0, 9)
114#define LCD_TIMV_LPP_GET(reg) BSP_FLD32GET(reg, 0, 9)
115#define LCD_TIMV_VSW(val) BSP_FLD32(val, 10, 15)
116#define LCD_TIMV_VSW_GET(reg) BSP_FLD32GET(reg, 10, 15)
117#define LCD_TIMV_VFP(val) BSP_FLD32(val, 16, 23)
118#define LCD_TIMV_VFP_GET(reg) BSP_FLD32GET(reg, 16, 23)
119#define LCD_TIMV_VBP(val) BSP_FLD32(val, 24, 31)
120#define LCD_TIMV_VBP_GET(reg) BSP_FLD32GET(reg, 24, 31)
121
122/** @} */
123
124/**
125 * @name LCD Clock and Signal Polarity Register
126 *
127 * @{
128 */
129
130#define LCD_POL_PCD_LO(val) BSP_FLD32(val, 0, 4)
131#define LCD_POL_PCD_LO_GET(reg) BSP_FLD32GET(reg, 0, 4)
132#define LCD_POL_CLKSEL BSP_BIT32(5)
133#define LCD_POL_ACB(val) BSP_FLD32(val, 6, 10)
134#define LCD_POL_ACB_GET(reg) BSP_FLD32GET(reg, 6, 10)
135#define LCD_POL_IVS BSP_BIT32(11)
136#define LCD_POL_IHS BSP_BIT32(12)
137#define LCD_POL_IPC BSP_BIT32(13)
138#define LCD_POL_IOE BSP_BIT32(14)
139#define LCD_POL_CPL(val) BSP_FLD32(val, 16, 25)
140#define LCD_POL_CPL_GET(reg) BSP_FLD32GET(reg, 16, 25)
141#define LCD_POL_BCD BSP_BIT32(26)
142#define LCD_POL_PCD_HI(val) BSP_FLD32(val, 27, 31)
143#define LCD_POL_PCD_HI_GET(reg) BSP_FLD32GET(reg, 27, 31)
144
145/** @} */
146
147/**
148 * @name LCD Line End Control Register
149 *
150 * @{
151 */
152
153#define LCD_LE_LED(val) BSP_FLD32(val, 0, 6)
154#define LCD_LE_LEE BSP_BIT32(16)
155
156/** @} */
157
158/**
159 * @name LCD Control Register
160 *
161 * @{
162 */
163
164#define LCD_CTRL_LCDEN BSP_BIT32(0)
165#define LCD_CTRL_LCDBPP(val) BSP_FLD32(val, 1, 3)
166#define LCD_CTRL_LCDBPP_GET(reg) BSP_FLD32GET(reg, 1, 3)
167#define LCD_CTRL_LCDBW BSP_BIT32(4)
168#define LCD_CTRL_LCDTFT BSP_BIT32(5)
169#define LCD_CTRL_LCDMONO8 BSP_BIT32(6)
170#define LCD_CTRL_LCDDUAL BSP_BIT32(7)
171#define LCD_CTRL_BGR BSP_BIT32(8)
172#define LCD_CTRL_BEBO BSP_BIT32(9)
173#define LCD_CTRL_BEPO BSP_BIT32(10)
174#define LCD_CTRL_LCDPWR BSP_BIT32(11)
175#define LCD_CTRL_LCDVCOMP(val) BSP_FLD32(val, 12, 13)
176#define LCD_CTRL_LCDVCOMP_GET(reg) BSP_FLD32GET(reg, 12, 13)
177#define LCD_CTRL_WATERMARK BSP_BIT32(16)
178
179/** @} */
180
181/**
182 * @name LCD Interrupt Registers
183 *
184 * @{
185 */
186
187#define LCD_INT_FUF BSP_BIT32(1)
188#define LCD_INT_LNBU BSP_BIT32(2)
189#define LCD_INT_VCOMP BSP_BIT32(3)
190#define LCD_INT_BER BSP_BIT32(4)
191
192/** @} */
193
194/**
195 * @name LCD Color Palette Register
196 *
197 * @{
198 */
199
200#define LCD_PAL_R(val) BSP_FLD16(val, 0, 4)
201#define LCD_PAL_G(val) BSP_FLD16(val, 5, 9)
202#define LCD_PAL_B(val) BSP_FLD16(val, 10, 14)
203#define LCD_PAL_I BSP_BIT16(15)
204
205/** @} */
206
207/** @} */
208
209#ifdef __cplusplus
210}
211#endif /* __cplusplus */
212
213#endif /* LIBBSP_ARM_SHARED_LPC_LCD_H */
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