source: rtems/c/src/lib/libbsp/arm/shared/lpc/include/lpc-i2s.h @ f68401e

4.115
Last change on this file since f68401e was 2d6543d4, checked in by Daniel Ramirez <javamonn@…>, on 11/30/13 at 02:18:44

doxygen: refactored doxygen in libbsp/arm/lpc32xx

This patch refactors a lot of the existing doxygen within libbsp/arm/lpc32xx.
Much of this refactoring was just renaming of existing groups to conform to a
more consistent naming structure. With the addition of a doxygen header for
tm27.h, all files within lpc32xx belong to doxygen group now. lpc32xx should
be used a reference for adding doxygen to other bsps.
  • Property mode set to 100644
File size: 2.3 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup lpc_i2s
5 *
6 * @brief I2S API.
7 */
8
9/*
10 * Copyright (c) 2010 embedded brains GmbH.  All rights reserved.
11 *
12 *  embedded brains GmbH
13 *  Obere Lagerstr. 30
14 *  82178 Puchheim
15 *  Germany
16 *  <rtems@embedded-brains.de>
17 *
18 * The license and distribution terms for this file may be
19 * found in the file LICENSE in this distribution or at
20 * http://www.rtems.com/license/LICENSE.
21 */
22
23#ifndef LIBBSP_ARM_SHARED_LPC_I2S_H
24#define LIBBSP_ARM_SHARED_LPC_I2S_H
25
26#include <bsp/utility.h>
27
28#ifdef __cplusplus
29extern "C" {
30#endif
31
32/**
33 * @defgroup lpc_i2s I2S Support
34 *
35 * @ingroup arm_lpc24xx
36 * @ingroup arm_lpc32xx
37 *
38 * @brief I2S support.
39 *
40 * @{
41 */
42
43/**
44 * @brief I2S control block.
45 */
46typedef struct {
47  uint32_t dao;
48  uint32_t dai;
49  uint32_t txfifo;
50  uint32_t rxfifo;
51  uint32_t state;
52  uint32_t dma [2];
53  uint32_t irq;
54  uint32_t txrate;
55  uint32_t rxrate;
56} lpc_i2s;
57
58/**
59 * @name I2S Digital Audio Input and Output
60 *
61 * @{
62 */
63
64#define I2S_DAIO_WORDWIDTH(val) BSP_FLD32(val, 0, 1)
65#define I2S_DAIO_MONO BSP_BIT32(2)
66#define I2S_DAIO_STOP BSP_BIT32(3)
67#define I2S_DAIO_RESET BSP_BIT32(4)
68#define I2S_DAIO_WS_SEL BSP_BIT32(5)
69#define I2S_DAIO_WS_HALFPERIOD(val) BSP_FLD32(val, 6, 14)
70#define I2S_DAIO_MUTE BSP_BIT32(15)
71
72/** @} */
73
74/**
75 * @name I2S Status Feedback
76 *
77 * @{
78 */
79
80#define I2S_STATE_IRQ BSP_BIT32(0)
81#define I2S_STATE_DMAREQ_0 BSP_BIT32(1)
82#define I2S_STATE_DMAREQ_1 BSP_BIT32(2)
83#define I2S_STATE_RX_LEVEL_GET(reg) BSP_FLD32GET(reg, 8, 11)
84#define I2S_STATE_TX_LEVEL_GET(reg) BSP_FLD32GET(reg, 16, 19)
85
86/** @} */
87
88/**
89 * @name I2S DMA Configuration
90 *
91 * @{
92 */
93
94#define I2S_DMA_RX_ENABLE BSP_BIT32(0)
95#define I2S_DMA_TX_ENABLE BSP_BIT32(1)
96#define I2S_DMA_RX_DEPTH(val) BSP_FLD32(val, 8, 11)
97#define I2S_DMA_TX_DEPTH(val) BSP_FLD32(val, 16, 19)
98
99/** @} */
100
101/**
102 * @name I2S Interrupt Request Control
103 *
104 * @{
105 */
106
107#define I2S_IRQ_RX BSP_BIT32(0)
108#define I2S_IRQ_TX BSP_BIT32(1)
109#define I2S_IRQ_RX_DEPTH(val) BSP_FLD32(val, 8, 11)
110#define I2S_IRQ_TX_DEPTH(val) BSP_FLD32(val, 16, 19)
111
112/** @} */
113
114/**
115 * @name I2S Transmit and Receive Clock Rate
116 *
117 * @{
118 */
119
120#define LPC24XX_I2S_RATE(val) BSP_FLD32(val, 0, 9)
121#define LPC32XX_I2S_RATE_X_DIVIDER(val) BSP_FLD32(val, 0, 7)
122#define LPC32XX_I2S_RATE_Y_DIVIDER(val) BSP_FLD32(val, 8, 15)
123
124/** @} */
125
126/** @} */
127
128#ifdef __cplusplus
129}
130#endif /* __cplusplus */
131
132#endif /* LIBBSP_ARM_SHARED_LPC_I2S_H */
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