[a3579d3b] | 1 | /** |
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| 2 | * @file |
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| 3 | * |
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| 4 | * @ingroup lpc_i2s |
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| 5 | * |
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| 6 | * @brief I2S API. |
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| 7 | */ |
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| 8 | |
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| 9 | /* |
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| 10 | * Copyright (c) 2010 embedded brains GmbH. All rights reserved. |
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| 11 | * |
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| 12 | * embedded brains GmbH |
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| 13 | * Obere Lagerstr. 30 |
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| 14 | * 82178 Puchheim |
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| 15 | * Germany |
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| 16 | * <rtems@embedded-brains.de> |
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| 17 | * |
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| 18 | * The license and distribution terms for this file may be |
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| 19 | * found in the file LICENSE in this distribution or at |
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[c499856] | 20 | * http://www.rtems.org/license/LICENSE. |
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[a3579d3b] | 21 | */ |
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| 22 | |
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| 23 | #ifndef LIBBSP_ARM_SHARED_LPC_I2S_H |
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| 24 | #define LIBBSP_ARM_SHARED_LPC_I2S_H |
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| 25 | |
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| 26 | #include <bsp/utility.h> |
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| 27 | |
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| 28 | #ifdef __cplusplus |
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| 29 | extern "C" { |
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| 30 | #endif |
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| 31 | |
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| 32 | /** |
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[6d4d934] | 33 | * @defgroup lpc_i2s I2S Support |
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[a3579d3b] | 34 | * |
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[2d6543d4] | 35 | * @ingroup arm_lpc24xx |
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| 36 | * @ingroup arm_lpc32xx |
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[a3579d3b] | 37 | * |
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| 38 | * @brief I2S support. |
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| 39 | * |
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| 40 | * @{ |
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| 41 | */ |
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| 42 | |
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| 43 | /** |
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| 44 | * @brief I2S control block. |
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| 45 | */ |
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| 46 | typedef struct { |
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| 47 | uint32_t dao; |
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| 48 | uint32_t dai; |
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| 49 | uint32_t txfifo; |
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| 50 | uint32_t rxfifo; |
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| 51 | uint32_t state; |
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| 52 | uint32_t dma [2]; |
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| 53 | uint32_t irq; |
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| 54 | uint32_t txrate; |
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| 55 | uint32_t rxrate; |
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| 56 | } lpc_i2s; |
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| 57 | |
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| 58 | /** |
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| 59 | * @name I2S Digital Audio Input and Output |
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| 60 | * |
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| 61 | * @{ |
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| 62 | */ |
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| 63 | |
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| 64 | #define I2S_DAIO_WORDWIDTH(val) BSP_FLD32(val, 0, 1) |
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| 65 | #define I2S_DAIO_MONO BSP_BIT32(2) |
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| 66 | #define I2S_DAIO_STOP BSP_BIT32(3) |
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| 67 | #define I2S_DAIO_RESET BSP_BIT32(4) |
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| 68 | #define I2S_DAIO_WS_SEL BSP_BIT32(5) |
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| 69 | #define I2S_DAIO_WS_HALFPERIOD(val) BSP_FLD32(val, 6, 14) |
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| 70 | #define I2S_DAIO_MUTE BSP_BIT32(15) |
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| 71 | |
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| 72 | /** @} */ |
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| 73 | |
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| 74 | /** |
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| 75 | * @name I2S Status Feedback |
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| 76 | * |
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| 77 | * @{ |
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| 78 | */ |
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| 79 | |
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| 80 | #define I2S_STATE_IRQ BSP_BIT32(0) |
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| 81 | #define I2S_STATE_DMAREQ_0 BSP_BIT32(1) |
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| 82 | #define I2S_STATE_DMAREQ_1 BSP_BIT32(2) |
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| 83 | #define I2S_STATE_RX_LEVEL_GET(reg) BSP_FLD32GET(reg, 8, 11) |
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| 84 | #define I2S_STATE_TX_LEVEL_GET(reg) BSP_FLD32GET(reg, 16, 19) |
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| 85 | |
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| 86 | /** @} */ |
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| 87 | |
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| 88 | /** |
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| 89 | * @name I2S DMA Configuration |
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| 90 | * |
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| 91 | * @{ |
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| 92 | */ |
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| 93 | |
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| 94 | #define I2S_DMA_RX_ENABLE BSP_BIT32(0) |
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| 95 | #define I2S_DMA_TX_ENABLE BSP_BIT32(1) |
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| 96 | #define I2S_DMA_RX_DEPTH(val) BSP_FLD32(val, 8, 11) |
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| 97 | #define I2S_DMA_TX_DEPTH(val) BSP_FLD32(val, 16, 19) |
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| 98 | |
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| 99 | /** @} */ |
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| 100 | |
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| 101 | /** |
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| 102 | * @name I2S Interrupt Request Control |
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| 103 | * |
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| 104 | * @{ |
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| 105 | */ |
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| 106 | |
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| 107 | #define I2S_IRQ_RX BSP_BIT32(0) |
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| 108 | #define I2S_IRQ_TX BSP_BIT32(1) |
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| 109 | #define I2S_IRQ_RX_DEPTH(val) BSP_FLD32(val, 8, 11) |
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| 110 | #define I2S_IRQ_TX_DEPTH(val) BSP_FLD32(val, 16, 19) |
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| 111 | |
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| 112 | /** @} */ |
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| 113 | |
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| 114 | /** |
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| 115 | * @name I2S Transmit and Receive Clock Rate |
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| 116 | * |
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| 117 | * @{ |
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| 118 | */ |
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| 119 | |
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| 120 | #define LPC24XX_I2S_RATE(val) BSP_FLD32(val, 0, 9) |
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[6d4d934] | 121 | #define LPC32XX_I2S_RATE_X_DIVIDER(val) BSP_FLD32(val, 0, 7) |
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| 122 | #define LPC32XX_I2S_RATE_Y_DIVIDER(val) BSP_FLD32(val, 8, 15) |
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[a3579d3b] | 123 | |
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| 124 | /** @} */ |
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| 125 | |
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| 126 | /** @} */ |
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| 127 | |
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| 128 | #ifdef __cplusplus |
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| 129 | } |
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| 130 | #endif /* __cplusplus */ |
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| 131 | |
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| 132 | #endif /* LIBBSP_ARM_SHARED_LPC_I2S_H */ |
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