source: rtems/c/src/lib/libbsp/arm/shared/lpc/include/lpc-emc.h @ 991fdb33

4.115
Last change on this file since 991fdb33 was c499856, checked in by Chris Johns <chrisj@…>, on Mar 20, 2014 at 9:10:47 PM

Change all references of rtems.com to rtems.org.

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File size: 3.5 KB
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1/**
2 * @file
3 *
4 * @ingroup lpc_emc
5 *
6 * @brief EMC support API.
7 */
8
9/*
10 * Copyright (c) 2010-2011 embedded brains GmbH.  All rights reserved.
11 *
12 *  embedded brains GmbH
13 *  Obere Lagerstr. 30
14 *  82178 Puchheim
15 *  Germany
16 *  <rtems@embedded-brains.de>
17 *
18 * The license and distribution terms for this file may be
19 * found in the file LICENSE in this distribution or at
20 * http://www.rtems.org/license/LICENSE.
21 */
22
23#ifndef LIBBSP_ARM_SHARED_LPC_EMC_H
24#define LIBBSP_ARM_SHARED_LPC_EMC_H
25
26#include <bsp/utility.h>
27
28#ifdef __cplusplus
29extern "C" {
30#endif /* __cplusplus */
31
32/**
33 * @defgroup lpc_emc EMC Support
34 *
35 * @ingroup arm_lpc24xx
36 * @ingroup arm_lpc32xx
37 *
38 * @brief EMC Support
39 *
40 * @{
41 */
42
43/**
44 * @name EMC Control Register (EMCControl)
45 *
46 * @{
47 */
48
49#define EMC_CTRL_E BSP_BIT32(0)
50#define EMC_CTRL_M BSP_BIT32(0)
51#define EMC_CTRL_L BSP_BIT32(2)
52
53/** @} */
54
55/**
56 * @name EMC Dynamic Memory Control Register (EMCDynamicControl)
57 *
58 * @{
59 */
60
61#define EMC_DYN_CTRL_CE BSP_BIT32(0)
62#define EMC_DYN_CTRL_CS BSP_BIT32(1)
63#define EMC_DYN_CTRL_SR BSP_BIT32(2)
64#define EMC_DYN_CTRL_SRMCC BSP_BIT32(3)
65#define EMC_DYN_CTRL_IMCC BSP_BIT32(4)
66#define EMC_DYN_CTRL_MCC BSP_BIT32(5)
67#define EMC_DYN_CTRL_I_MASK BSP_MSK32(7, 8)
68#define EMC_DYN_CTRL_I_NORMAL BSP_FLD32(0x0, 7, 8)
69#define EMC_DYN_CTRL_I_MODE BSP_FLD32(0x1, 7, 8)
70#define EMC_DYN_CTRL_I_PALL BSP_FLD32(0x2, 7, 8)
71#define EMC_DYN_CTRL_I_NOP BSP_FLD32(0x3, 7, 8)
72#define EMC_DYN_CTRL_DP BSP_BIT32(13)
73
74/** @} */
75
76/**
77 * @name EMC Dynamic Memory Read Configuration Register (EMCDynamicReadConfig)
78 *
79 * @{
80 */
81
82#define EMC_DYN_READ_CONFIG_SDR_STRAT(val) BSP_FLD32(val, 0, 1)
83#define EMC_DYN_READ_CONFIG_SDR_POL_POS BSP_BIT32(4)
84#define EMC_DYN_READ_CONFIG_DDR_STRAT(val) BSP_FLD32(val, 8, 9)
85#define EMC_DYN_READ_CONFIG_DDR_POL_POS BSP_BIT32(12)
86
87/** @} */
88
89/**
90 * @name EMC Dynamic Memory Configuration N Register (EMCDynamicConfigN)
91 *
92 * @{
93 */
94
95#define EMC_DYN_CFG_MD_LPC24XX(val) BSP_FLD32(val, 3, 4)
96#define EMC_DYN_CFG_MD_LPC32XX(val) BSP_FLD32(val, 0, 2)
97#define EMC_DYN_CFG_AM(val) BSP_FLD32(val, 7, 14)
98#define EMC_DYN_CFG_B BSP_BIT32(19)
99#define EMC_DYN_CFG_P BSP_BIT32(20)
100
101/** @} */
102
103/**
104 * @name EMC Dynamic Memory RAS and CAS Delay N Register (EMCDynamicRasCasN)
105 *
106 * @{
107 */
108
109#define EMC_DYN_RASCAS_RAS(val) BSP_FLD32(val, 0, 3)
110#define EMC_DYN_RASCAS_CAS(val, half) BSP_FLD32(((val) << 1) | (half), 7, 10)
111
112/** @} */
113
114#define EMC_DYN_CHIP_COUNT 4
115
116#define EMC_STATIC_CHIP_COUNT 4
117
118typedef struct {
119  uint32_t config;
120  uint32_t rascas;
121  uint32_t reserved_0 [6];
122} lpc_emc_dynamic;
123
124typedef struct {
125  uint32_t config;
126  uint32_t waitwen;
127  uint32_t waitoen;
128  uint32_t waitrd;
129  uint32_t waitpage;
130  uint32_t waitwr;
131  uint32_t waitturn;
132  uint32_t reserved_0 [1];
133} lpc_emc_static;
134
135typedef struct {
136  uint32_t control;
137  uint32_t status;
138  uint32_t config;
139  uint32_t reserved_0 [5];
140  uint32_t dynamiccontrol;
141  uint32_t dynamicrefresh;
142  uint32_t dynamicreadconfig;
143  uint32_t reserved_1;
144  uint32_t dynamictrp;
145  uint32_t dynamictras;
146  uint32_t dynamictsrex;
147  uint32_t dynamictapr;
148  uint32_t dynamictdal;
149  uint32_t dynamictwr;
150  uint32_t dynamictrc;
151  uint32_t dynamictrfc;
152  uint32_t dynamictxsr;
153  uint32_t dynamictrrd;
154  uint32_t dynamictmrd;
155  uint32_t dynamictcdlr;
156  uint32_t reserved_3 [8];
157  uint32_t staticextendedwait;
158  uint32_t reserved_4 [31];
159  lpc_emc_dynamic dynamic [EMC_DYN_CHIP_COUNT];
160  uint32_t reserved_5 [32];
161  lpc_emc_static emcstatic [EMC_STATIC_CHIP_COUNT];
162} lpc_emc;
163
164/** @} */
165
166#ifdef __cplusplus
167}
168#endif /* __cplusplus */
169
170#endif /* LIBBSP_ARM_SHARED_LPC_EMC_H */
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