source: rtems/c/src/lib/libbsp/arm/shared/lpc/include/lpc-dma.h @ 991fdb33

4.115
Last change on this file since 991fdb33 was c499856, checked in by Chris Johns <chrisj@…>, on Mar 20, 2014 at 9:10:47 PM

Change all references of rtems.com to rtems.org.

  • Property mode set to 100644
File size: 5.1 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup lpc_dma
5 *
6 * @brief DMA support API.
7 */
8
9/*
10 * Copyright (c) 2010-2012 embedded brains GmbH.  All rights reserved.
11 *
12 *  embedded brains GmbH
13 *  Obere Lagerstr. 30
14 *  82178 Puchheim
15 *  Germany
16 *  <rtems@embedded-brains.de>
17 *
18 * The license and distribution terms for this file may be
19 * found in the file LICENSE in this distribution or at
20 * http://www.rtems.org/license/LICENSE.
21 */
22
23#ifndef LIBBSP_ARM_SHARED_LPC_DMA_H
24#define LIBBSP_ARM_SHARED_LPC_DMA_H
25
26#include <bspopts.h>
27#include <bsp/utility.h>
28
29#ifdef __cplusplus
30extern "C" {
31#endif
32
33/**
34 * @defgroup lpc_dma DMA Support
35 *
36 * @ingroup arm_lpc24xx
37 * @ingroup arm_lpc32xx
38 *
39 * @brief DMA support.
40 *
41 * @{
42 */
43
44/**
45 * @brief DMA descriptor item.
46 */
47typedef struct {
48  uint32_t src;
49  uint32_t dest;
50  uint32_t lli;
51  uint32_t ctrl;
52} lpc_dma_descriptor;
53
54/**
55 * @brief DMA channel block.
56 */
57typedef struct {
58  lpc_dma_descriptor desc;
59  uint32_t cfg;
60  uint32_t reserved [3];
61} lpc_dma_channel;
62
63/**
64 * @brief DMA control block.
65 */
66typedef struct {
67  uint32_t int_stat;
68  uint32_t int_tc_stat;
69  uint32_t int_tc_clear;
70  uint32_t int_err_stat;
71  uint32_t int_err_clear;
72  uint32_t raw_tc_stat;
73  uint32_t raw_err_stat;
74  uint32_t enabled_channels;
75  uint32_t soft_burst_req;
76  uint32_t soft_single_req;
77  uint32_t soft_last_burst_req;
78  uint32_t soft_last_single_req;
79  uint32_t cfg;
80  uint32_t sync;
81  uint32_t reserved [50];
82  lpc_dma_channel channels [LPC_DMA_CHANNEL_COUNT];
83} lpc_dma;
84
85/**
86 * @name DMA Configuration Register
87 *
88 * @{
89 */
90
91#define DMA_CFG_E BSP_BIT32(0)
92#define DMA_CFG_M_0 BSP_BIT32(1)
93#define DMA_CFG_M_1 BSP_BIT32(2)
94
95/** @} */
96
97/**
98 * @name DMA Channel Control Register
99 *
100 * @{
101 */
102
103#define DMA_CH_CTRL_TSZ(val) BSP_FLD32(val, 0, 11)
104#define DMA_CH_CTRL_TSZ_MAX DMA_CH_CTRL_TSZ(0xfff)
105
106#define DMA_CH_CTRL_SB(val) BSP_FLD32(val, 12, 14)
107#define DMA_CH_CTRL_SB_1 DMA_CH_CTRL_SB(0)
108#define DMA_CH_CTRL_SB_4 DMA_CH_CTRL_SB(1)
109#define DMA_CH_CTRL_SB_8 DMA_CH_CTRL_SB(2)
110#define DMA_CH_CTRL_SB_16 DMA_CH_CTRL_SB(3)
111#define DMA_CH_CTRL_SB_32 DMA_CH_CTRL_SB(4)
112#define DMA_CH_CTRL_SB_64 DMA_CH_CTRL_SB(5)
113#define DMA_CH_CTRL_SB_128 DMA_CH_CTRL_SB(6)
114#define DMA_CH_CTRL_SB_256 DMA_CH_CTRL_SB(7)
115
116#define DMA_CH_CTRL_DB(val) BSP_FLD32(val, 15, 17)
117#define DMA_CH_CTRL_DB_1 DMA_CH_CTRL_DB(0)
118#define DMA_CH_CTRL_DB_4 DMA_CH_CTRL_DB(1)
119#define DMA_CH_CTRL_DB_8 DMA_CH_CTRL_DB(2)
120#define DMA_CH_CTRL_DB_16 DMA_CH_CTRL_DB(3)
121#define DMA_CH_CTRL_DB_32 DMA_CH_CTRL_DB(4)
122#define DMA_CH_CTRL_DB_64 DMA_CH_CTRL_DB(5)
123#define DMA_CH_CTRL_DB_128 DMA_CH_CTRL_DB(6)
124#define DMA_CH_CTRL_DB_256 DMA_CH_CTRL_DB(7)
125
126#define DMA_CH_CTRL_SW(val) BSP_FLD32(val, 18, 20)
127#define DMA_CH_CTRL_SW_8 DMA_CH_CTRL_SW(0)
128#define DMA_CH_CTRL_SW_16 DMA_CH_CTRL_SW(1)
129#define DMA_CH_CTRL_SW_32 DMA_CH_CTRL_SW(2)
130
131#define DMA_CH_CTRL_DW(val) BSP_FLD32(val, 21, 23)
132#define DMA_CH_CTRL_DW_8 DMA_CH_CTRL_DW(0)
133#define DMA_CH_CTRL_DW_16 DMA_CH_CTRL_DW(1)
134#define DMA_CH_CTRL_DW_32 DMA_CH_CTRL_DW(2)
135
136#define DMA_CH_CTRL_S BSP_BIT32(24)
137#define DMA_CH_CTRL_D BSP_BIT32(25)
138#define DMA_CH_CTRL_SI BSP_BIT32(26)
139#define DMA_CH_CTRL_DI BSP_BIT32(27)
140#define DMA_CH_CTRL_PROT(val) BSP_FLD32(val, 28, 30)
141#define DMA_CH_CTRL_I BSP_BIT32(31)
142
143/** @} */
144
145/**
146 * @name DMA Channel Configuration Register
147 *
148 * @{
149 */
150
151#define DMA_CH_CFG_E BSP_BIT32(0)
152#define DMA_CH_CFG_SPER(val) BSP_FLD32(val, 1, 5)
153#define DMA_CH_CFG_DPER(val) BSP_FLD32(val, 6, 10)
154
155#define DMA_CH_CFG_FLOW(val) BSP_FLD32(val, 11, 13)
156#define DMA_CH_CFG_FLOW_MEM_TO_MEM_DMA DMA_CH_CFG_FLOW(0)
157#define DMA_CH_CFG_FLOW_MEM_TO_PER_DMA DMA_CH_CFG_FLOW(1)
158#define DMA_CH_CFG_FLOW_PER_TO_MEM_DMA DMA_CH_CFG_FLOW(2)
159#define DMA_CH_CFG_FLOW_PER_TO_PER_DMA DMA_CH_CFG_FLOW(3)
160#define DMA_CH_CFG_FLOW_PER_TO_PER_DEST DMA_CH_CFG_FLOW(4)
161#define DMA_CH_CFG_FLOW_MEM_TO_PER_PER DMA_CH_CFG_FLOW(5)
162#define DMA_CH_CFG_FLOW_PER_TO_MEM_PER DMA_CH_CFG_FLOW(6)
163#define DMA_CH_CFG_FLOW_PER_TO_PER_SRC DMA_CH_CFG_FLOW(7)
164
165#define DMA_CH_CFG_IE BSP_BIT32(14)
166#define DMA_CH_CFG_ITC BSP_BIT32(15)
167#define DMA_CH_CFG_L BSP_BIT32(16)
168#define DMA_CH_CFG_A BSP_BIT32(17)
169#define DMA_CH_CFG_H BSP_BIT32(18)
170
171/** @} */
172
173/**
174 * @name LPC24XX DMA Peripherals
175 *
176 * @{
177 */
178
179#define LPC24XX_DMA_PER_SSP_0_TX 0
180#define LPC24XX_DMA_PER_SSP_0_RX 1
181#define LPC24XX_DMA_PER_SSP_1_TX 2
182#define LPC24XX_DMA_PER_SSP_1_RX 3
183#define LPC24XX_DMA_PER_SD_MMC 4
184#define LPC24XX_DMA_PER_I2S_CH_0 5
185#define LPC24XX_DMA_PER_I2S_CH_1 6
186
187/** @} */
188
189/**
190 * @name LPC32XX DMA Peripherals
191 *
192 * @{
193 */
194
195#define LPC32XX_DMA_PER_I2S_0_CH_0 0
196#define LPC32XX_DMA_PER_I2S_0_CH_1 13
197#define LPC32XX_DMA_PER_I2S_1_CH_0 2
198#define LPC32XX_DMA_PER_I2S_1_CH_1 10
199#define LPC32XX_DMA_PER_NAND_0 1
200#define LPC32XX_DMA_PER_NAND_1 12
201#define LPC32XX_DMA_PER_SD_MMC 4
202#define LPC32XX_DMA_PER_SSP_0_RX 14
203#define LPC32XX_DMA_PER_SSP_0_TX 15
204#define LPC32XX_DMA_PER_SSP_1_RX 3
205#define LPC32XX_DMA_PER_SSP_1_TX 11
206#define LPC32XX_DMA_PER_UART_1_RX 6
207#define LPC32XX_DMA_PER_UART_1_TX 5
208#define LPC32XX_DMA_PER_UART_2_RX 8
209#define LPC32XX_DMA_PER_UART_2_TX 7
210#define LPC32XX_DMA_PER_UART_7_RX 10
211#define LPC32XX_DMA_PER_UART_7_TX 9
212
213/** @} */
214
215/** @} */
216
217#ifdef __cplusplus
218}
219#endif /* __cplusplus */
220
221#endif /* LIBBSP_ARM_SHARED_LPC_DMA_H */
Note: See TracBrowser for help on using the repository browser.