1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup lpc_dma |
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5 | * |
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6 | * @brief DMA support API. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2010-2012 embedded brains GmbH. All rights reserved. |
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11 | * |
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12 | * embedded brains GmbH |
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13 | * Obere Lagerstr. 30 |
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14 | * 82178 Puchheim |
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15 | * Germany |
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16 | * <rtems@embedded-brains.de> |
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17 | * |
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18 | * The license and distribution terms for this file may be |
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19 | * found in the file LICENSE in this distribution or at |
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20 | * http://www.rtems.com/license/LICENSE. |
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21 | */ |
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22 | |
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23 | #ifndef LIBBSP_ARM_SHARED_LPC_DMA_H |
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24 | #define LIBBSP_ARM_SHARED_LPC_DMA_H |
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25 | |
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26 | #include <bspopts.h> |
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27 | #include <bsp/utility.h> |
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28 | |
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29 | #ifdef __cplusplus |
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30 | extern "C" { |
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31 | #endif |
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32 | |
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33 | /** |
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34 | * @defgroup lpc_dma DMA Support |
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35 | * |
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36 | * @ingroup lpc24xx |
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37 | * @ingroup lpc32xx |
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38 | * |
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39 | * @brief DMA support. |
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40 | * |
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41 | * @{ |
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42 | */ |
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43 | |
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44 | /** |
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45 | * @brief DMA descriptor item. |
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46 | */ |
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47 | typedef struct { |
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48 | uint32_t src; |
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49 | uint32_t dest; |
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50 | uint32_t lli; |
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51 | uint32_t ctrl; |
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52 | } lpc_dma_descriptor; |
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53 | |
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54 | /** |
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55 | * @brief DMA channel block. |
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56 | */ |
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57 | typedef struct { |
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58 | lpc_dma_descriptor desc; |
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59 | uint32_t cfg; |
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60 | uint32_t reserved [3]; |
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61 | } lpc_dma_channel; |
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62 | |
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63 | /** |
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64 | * @brief DMA control block. |
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65 | */ |
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66 | typedef struct { |
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67 | uint32_t int_stat; |
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68 | uint32_t int_tc_stat; |
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69 | uint32_t int_tc_clear; |
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70 | uint32_t int_err_stat; |
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71 | uint32_t int_err_clear; |
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72 | uint32_t raw_tc_stat; |
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73 | uint32_t raw_err_stat; |
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74 | uint32_t enabled_channels; |
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75 | uint32_t soft_burst_req; |
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76 | uint32_t soft_single_req; |
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77 | uint32_t soft_last_burst_req; |
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78 | uint32_t soft_last_single_req; |
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79 | uint32_t cfg; |
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80 | uint32_t sync; |
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81 | uint32_t reserved [50]; |
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82 | lpc_dma_channel channels [LPC_DMA_CHANNEL_COUNT]; |
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83 | } lpc_dma; |
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84 | |
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85 | /** |
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86 | * @name DMA Configuration Register |
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87 | * |
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88 | * @{ |
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89 | */ |
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90 | |
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91 | #define DMA_CFG_E BSP_BIT32(0) |
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92 | #define DMA_CFG_M_0 BSP_BIT32(1) |
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93 | #define DMA_CFG_M_1 BSP_BIT32(2) |
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94 | |
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95 | /** @} */ |
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96 | |
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97 | /** |
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98 | * @name DMA Channel Control Register |
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99 | * |
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100 | * @{ |
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101 | */ |
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102 | |
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103 | #define DMA_CH_CTRL_TSZ(val) BSP_FLD32(val, 0, 11) |
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104 | #define DMA_CH_CTRL_TSZ_MAX DMA_CH_CTRL_TSZ(0xfff) |
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105 | |
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106 | #define DMA_CH_CTRL_SB(val) BSP_FLD32(val, 12, 14) |
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107 | #define DMA_CH_CTRL_SB_1 DMA_CH_CTRL_SB(0) |
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108 | #define DMA_CH_CTRL_SB_4 DMA_CH_CTRL_SB(1) |
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109 | #define DMA_CH_CTRL_SB_8 DMA_CH_CTRL_SB(2) |
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110 | #define DMA_CH_CTRL_SB_16 DMA_CH_CTRL_SB(3) |
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111 | #define DMA_CH_CTRL_SB_32 DMA_CH_CTRL_SB(4) |
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112 | #define DMA_CH_CTRL_SB_64 DMA_CH_CTRL_SB(5) |
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113 | #define DMA_CH_CTRL_SB_128 DMA_CH_CTRL_SB(6) |
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114 | #define DMA_CH_CTRL_SB_256 DMA_CH_CTRL_SB(7) |
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115 | |
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116 | #define DMA_CH_CTRL_DB(val) BSP_FLD32(val, 15, 17) |
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117 | #define DMA_CH_CTRL_DB_1 DMA_CH_CTRL_DB(0) |
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118 | #define DMA_CH_CTRL_DB_4 DMA_CH_CTRL_DB(1) |
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119 | #define DMA_CH_CTRL_DB_8 DMA_CH_CTRL_DB(2) |
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120 | #define DMA_CH_CTRL_DB_16 DMA_CH_CTRL_DB(3) |
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121 | #define DMA_CH_CTRL_DB_32 DMA_CH_CTRL_DB(4) |
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122 | #define DMA_CH_CTRL_DB_64 DMA_CH_CTRL_DB(5) |
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123 | #define DMA_CH_CTRL_DB_128 DMA_CH_CTRL_DB(6) |
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124 | #define DMA_CH_CTRL_DB_256 DMA_CH_CTRL_DB(7) |
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125 | |
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126 | #define DMA_CH_CTRL_SW(val) BSP_FLD32(val, 18, 20) |
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127 | #define DMA_CH_CTRL_SW_8 DMA_CH_CTRL_SW(0) |
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128 | #define DMA_CH_CTRL_SW_16 DMA_CH_CTRL_SW(1) |
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129 | #define DMA_CH_CTRL_SW_32 DMA_CH_CTRL_SW(2) |
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130 | |
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131 | #define DMA_CH_CTRL_DW(val) BSP_FLD32(val, 21, 23) |
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132 | #define DMA_CH_CTRL_DW_8 DMA_CH_CTRL_DW(0) |
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133 | #define DMA_CH_CTRL_DW_16 DMA_CH_CTRL_DW(1) |
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134 | #define DMA_CH_CTRL_DW_32 DMA_CH_CTRL_DW(2) |
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135 | |
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136 | #define DMA_CH_CTRL_S BSP_BIT32(24) |
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137 | #define DMA_CH_CTRL_D BSP_BIT32(25) |
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138 | #define DMA_CH_CTRL_SI BSP_BIT32(26) |
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139 | #define DMA_CH_CTRL_DI BSP_BIT32(27) |
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140 | #define DMA_CH_CTRL_PROT(val) BSP_FLD32(val, 28, 30) |
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141 | #define DMA_CH_CTRL_I BSP_BIT32(31) |
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142 | |
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143 | /** @} */ |
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144 | |
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145 | /** |
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146 | * @name DMA Channel Configuration Register |
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147 | * |
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148 | * @{ |
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149 | */ |
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150 | |
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151 | #define DMA_CH_CFG_E BSP_BIT32(0) |
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152 | #define DMA_CH_CFG_SPER(val) BSP_FLD32(val, 1, 5) |
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153 | #define DMA_CH_CFG_DPER(val) BSP_FLD32(val, 6, 10) |
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154 | |
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155 | #define DMA_CH_CFG_FLOW(val) BSP_FLD32(val, 11, 13) |
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156 | #define DMA_CH_CFG_FLOW_MEM_TO_MEM_DMA DMA_CH_CFG_FLOW(0) |
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157 | #define DMA_CH_CFG_FLOW_MEM_TO_PER_DMA DMA_CH_CFG_FLOW(1) |
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158 | #define DMA_CH_CFG_FLOW_PER_TO_MEM_DMA DMA_CH_CFG_FLOW(2) |
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159 | #define DMA_CH_CFG_FLOW_PER_TO_PER_DMA DMA_CH_CFG_FLOW(3) |
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160 | #define DMA_CH_CFG_FLOW_PER_TO_PER_DEST DMA_CH_CFG_FLOW(4) |
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161 | #define DMA_CH_CFG_FLOW_MEM_TO_PER_PER DMA_CH_CFG_FLOW(5) |
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162 | #define DMA_CH_CFG_FLOW_PER_TO_MEM_PER DMA_CH_CFG_FLOW(6) |
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163 | #define DMA_CH_CFG_FLOW_PER_TO_PER_SRC DMA_CH_CFG_FLOW(7) |
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164 | |
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165 | #define DMA_CH_CFG_IE BSP_BIT32(14) |
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166 | #define DMA_CH_CFG_ITC BSP_BIT32(15) |
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167 | #define DMA_CH_CFG_L BSP_BIT32(16) |
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168 | #define DMA_CH_CFG_A BSP_BIT32(17) |
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169 | #define DMA_CH_CFG_H BSP_BIT32(18) |
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170 | |
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171 | /** @} */ |
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172 | |
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173 | /** |
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174 | * @name LPC24XX DMA Peripherals |
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175 | * |
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176 | * @{ |
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177 | */ |
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178 | |
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179 | #define LPC24XX_DMA_PER_SSP_0_TX 0 |
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180 | #define LPC24XX_DMA_PER_SSP_0_RX 1 |
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181 | #define LPC24XX_DMA_PER_SSP_1_TX 2 |
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182 | #define LPC24XX_DMA_PER_SSP_1_RX 3 |
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183 | #define LPC24XX_DMA_PER_SD_MMC 4 |
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184 | #define LPC24XX_DMA_PER_I2S_CH_0 5 |
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185 | #define LPC24XX_DMA_PER_I2S_CH_1 6 |
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186 | |
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187 | /** @} */ |
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188 | |
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189 | /** |
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190 | * @name LPC32XX DMA Peripherals |
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191 | * |
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192 | * @{ |
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193 | */ |
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194 | |
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195 | #define LPC32XX_DMA_PER_I2S_0_CH_0 0 |
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196 | #define LPC32XX_DMA_PER_I2S_0_CH_1 13 |
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197 | #define LPC32XX_DMA_PER_I2S_1_CH_0 2 |
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198 | #define LPC32XX_DMA_PER_I2S_1_CH_1 10 |
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199 | #define LPC32XX_DMA_PER_NAND_0 1 |
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200 | #define LPC32XX_DMA_PER_NAND_1 12 |
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201 | #define LPC32XX_DMA_PER_SD_MMC 4 |
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202 | #define LPC32XX_DMA_PER_SSP_0_RX 14 |
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203 | #define LPC32XX_DMA_PER_SSP_0_TX 15 |
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204 | #define LPC32XX_DMA_PER_SSP_1_RX 3 |
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205 | #define LPC32XX_DMA_PER_SSP_1_TX 11 |
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206 | #define LPC32XX_DMA_PER_UART_1_RX 6 |
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207 | #define LPC32XX_DMA_PER_UART_1_TX 5 |
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208 | #define LPC32XX_DMA_PER_UART_2_RX 8 |
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209 | #define LPC32XX_DMA_PER_UART_2_TX 7 |
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210 | #define LPC32XX_DMA_PER_UART_7_RX 10 |
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211 | #define LPC32XX_DMA_PER_UART_7_TX 9 |
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212 | |
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213 | /** @} */ |
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214 | |
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215 | /** @} */ |
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216 | |
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217 | #ifdef __cplusplus |
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218 | } |
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219 | #endif /* __cplusplus */ |
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220 | |
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221 | #endif /* LIBBSP_ARM_SHARED_LPC_DMA_H */ |
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