source: rtems/c/src/lib/libbsp/arm/shared/lpc/include/lpc-dma.h @ 7a6f8d0

4.104.11
Last change on this file since 7a6f8d0 was 7a6f8d0, checked in by Thomas Doerfler <Thomas.Doerfler@…>, on Apr 9, 2010 at 12:22:57 PM

added dma header
added thumb support to start.S
updated documentation

  • Property mode set to 100644
File size: 5.4 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup lpc_dma
5 *
6 * @brief DMA API.
7 */
8
9/*
10 * Copyright (c) 2010
11 * embedded brains GmbH
12 * Obere Lagerstr. 30
13 * D-82178 Puchheim
14 * Germany
15 * <rtems@embedded-brains.de>
16 *
17 * The license and distribution terms for this file may be
18 * found in the file LICENSE in this distribution or at
19 * http://www.rtems.com/license/LICENSE.
20 */
21
22#ifndef LIBBSP_ARM_SHARED_LPC_DMA_H
23#define LIBBSP_ARM_SHARED_LPC_DMA_H
24
25#include <stdint.h>
26
27#ifdef __cplusplus
28extern "C" {
29#endif
30
31/**
32 * @defgroup lpc_dma DMA Support
33 *
34 * @ingroup lpc
35 *
36 * @brief DMA support.
37 *
38 * @{
39 */
40
41/**
42 * @brief DMA descriptor item.
43 */
44typedef struct {
45  uint32_t src;
46  uint32_t dest;
47  uint32_t lli;
48  uint32_t ctrl;
49} lpc_dma_descriptor;
50
51/**
52 * @brief DMA channel block.
53 */
54typedef struct {
55  lpc_dma_descriptor desc;
56  uint32_t cfg;
57  uint32_t reserved [3];
58} lpc_dma_channel;
59
60/**
61 * @brief DMA control block.
62 */
63typedef struct {
64  uint32_t int_stat;
65  uint32_t int_tc_stat;
66  uint32_t int_tc_clear;
67  uint32_t int_err_stat;
68  uint32_t int_err_clear;
69  uint32_t raw_tc_stat;
70  uint32_t raw_err_stat;
71  uint32_t enabled_channels;
72  uint32_t soft_burst_req;
73  uint32_t soft_single_req;
74  uint32_t soft_last_burst_req;
75  uint32_t soft_last_single_req;
76  uint32_t cfg;
77  uint32_t sync;
78  uint32_t reserved [50];
79  lpc_dma_channel channels [];
80} lpc_dma;
81
82/**
83 * @name DMA Configuration Register Defines
84 *
85 * @{
86 */
87
88#define LPC_DMA_CFG_EN (1U << 0)
89#define LPC_DMA_CFG_M_0 (1U << 1)
90#define LPC_DMA_CFG_M_1 (1U << 2)
91
92/** @} */
93
94/**
95 * @name DMA Channel Control Register Defines
96 *
97 * @{
98 */
99
100#define LPC_DMA_CH_CTRL_TSZ_MASK 0xfffU
101#define LPC_DMA_CH_CTRL_TSZ_MAX 0xfffU
102
103#define LPC_DMA_CH_CTRL_SB_MASK (0x7U << 12)
104#define LPC_DMA_CH_CTRL_SB_1 (0x0U << 12)
105#define LPC_DMA_CH_CTRL_SB_4 (0x1U << 12)
106#define LPC_DMA_CH_CTRL_SB_8 (0x2U << 12)
107#define LPC_DMA_CH_CTRL_SB_16 (0x3U << 12)
108#define LPC_DMA_CH_CTRL_SB_32 (0x4U << 12)
109#define LPC_DMA_CH_CTRL_SB_64 (0x5U << 12)
110#define LPC_DMA_CH_CTRL_SB_128 (0x6U << 12)
111#define LPC_DMA_CH_CTRL_SB_256 (0x7U << 12)
112
113#define LPC_DMA_CH_CTRL_DB_MASK (0x7U << 15)
114#define LPC_DMA_CH_CTRL_DB_1 (0x0U << 15)
115#define LPC_DMA_CH_CTRL_DB_4 (0x1U << 15)
116#define LPC_DMA_CH_CTRL_DB_8 (0x2U << 15)
117#define LPC_DMA_CH_CTRL_DB_16 (0x3U << 15)
118#define LPC_DMA_CH_CTRL_DB_32 (0x4U << 15)
119#define LPC_DMA_CH_CTRL_DB_64 (0x5U << 15)
120#define LPC_DMA_CH_CTRL_DB_128 (0x6U << 15)
121#define LPC_DMA_CH_CTRL_DB_256 (0x7U << 15)
122
123#define LPC_DMA_CH_CTRL_SW_MASK (0x7U << 18)
124#define LPC_DMA_CH_CTRL_SW_8 (0x0U << 18)
125#define LPC_DMA_CH_CTRL_SW_16 (0x1U << 18)
126#define LPC_DMA_CH_CTRL_SW_32 (0x2U << 18)
127
128#define LPC_DMA_CH_CTRL_DW_MASK (0x7U << 21)
129#define LPC_DMA_CH_CTRL_DW_8 (0x0U << 21)
130#define LPC_DMA_CH_CTRL_DW_16 (0x1U << 21)
131#define LPC_DMA_CH_CTRL_DW_32 (0x2U << 21)
132
133#define LPC_DMA_CH_CTRL_SM_0 (0U << 24)
134#define LPC_DMA_CH_CTRL_SM_1 (1U << 24)
135
136#define LPC_DMA_CH_CTRL_DM_0 (0U << 25)
137#define LPC_DMA_CH_CTRL_DM_1 (1U << 25)
138
139#define LPC_DMA_CH_CTRL_SI (1U << 26)
140#define LPC_DMA_CH_CTRL_DI (1U << 27)
141#define LPC_DMA_CH_CTRL_ITC (1U << 31)
142
143/** @} */
144
145/**
146 * @name DMA Channel Configuration Register Defines
147 *
148 * @{
149 */
150
151#define LPC_DMA_CH_CFG_EN (1U << 0)
152
153#define LPC_DMA_CH_CFG_SPER_MASK (0xfU << 1)
154#define LPC_DMA_CH_CFG_SPER_SHIFT 1
155#define LPC_DMA_CH_CFG_SPER_0 (0x0U << 1)
156#define LPC_DMA_CH_CFG_SPER_1 (0x1U << 1)
157#define LPC_DMA_CH_CFG_SPER_2 (0x2U << 1)
158#define LPC_DMA_CH_CFG_SPER_3 (0x3U << 1)
159#define LPC_DMA_CH_CFG_SPER_4 (0x4U << 1)
160#define LPC_DMA_CH_CFG_SPER_5 (0x5U << 1)
161#define LPC_DMA_CH_CFG_SPER_6 (0x6U << 1)
162#define LPC_DMA_CH_CFG_SPER_7 (0x7U << 1)
163#define LPC_DMA_CH_CFG_SPER_8 (0x8U << 1)
164#define LPC_DMA_CH_CFG_SPER_9 (0x9U << 1)
165#define LPC_DMA_CH_CFG_SPER_10 (0xaU << 1)
166#define LPC_DMA_CH_CFG_SPER_11 (0xbU << 1)
167#define LPC_DMA_CH_CFG_SPER_12 (0xcU << 1)
168#define LPC_DMA_CH_CFG_SPER_13 (0xdU << 1)
169#define LPC_DMA_CH_CFG_SPER_14 (0xeU << 1)
170#define LPC_DMA_CH_CFG_SPER_15 (0xfU << 1)
171
172#define LPC_DMA_CH_CFG_DPER_MASK (0xfU << 6)
173#define LPC_DMA_CH_CFG_DPER_SHIFT 6
174#define LPC_DMA_CH_CFG_DPER_0 (0x0U << 6)
175#define LPC_DMA_CH_CFG_DPER_1 (0x1U << 6)
176#define LPC_DMA_CH_CFG_DPER_2 (0x2U << 6)
177#define LPC_DMA_CH_CFG_DPER_3 (0x3U << 6)
178#define LPC_DMA_CH_CFG_DPER_4 (0x4U << 6)
179#define LPC_DMA_CH_CFG_DPER_5 (0x5U << 6)
180#define LPC_DMA_CH_CFG_DPER_6 (0x6U << 6)
181#define LPC_DMA_CH_CFG_DPER_7 (0x7U << 6)
182#define LPC_DMA_CH_CFG_DPER_8 (0x8U << 6)
183#define LPC_DMA_CH_CFG_DPER_9 (0x9U << 6)
184#define LPC_DMA_CH_CFG_DPER_10 (0xaU << 6)
185#define LPC_DMA_CH_CFG_DPER_11 (0xbU << 6)
186#define LPC_DMA_CH_CFG_DPER_12 (0xcU << 6)
187#define LPC_DMA_CH_CFG_DPER_13 (0xdU << 6)
188#define LPC_DMA_CH_CFG_DPER_14 (0xeU << 6)
189#define LPC_DMA_CH_CFG_DPER_15 (0xfU << 6)
190
191#define LPC_DMA_CH_CFG_FLOW_MASK (0x7U << 11)
192#define LPC_DMA_CH_CFG_FLOW_MEM_TO_MEM_DMA (0x0U << 11)
193#define LPC_DMA_CH_CFG_FLOW_MEM_TO_PER_DMA (0x1U << 11)
194#define LPC_DMA_CH_CFG_FLOW_PER_TO_MEM_DMA (0x2U << 11)
195#define LPC_DMA_CH_CFG_FLOW_PER_TO_PER_DMA (0x3U << 11)
196#define LPC_DMA_CH_CFG_FLOW_PER_TO_PER_DEST (0x4U << 11)
197#define LPC_DMA_CH_CFG_FLOW_MEM_TO_PER_PER (0x5U << 11)
198#define LPC_DMA_CH_CFG_FLOW_PER_TO_MEM_PER (0x6U << 11)
199#define LPC_DMA_CH_CFG_FLOW_PER_TO_PER_SRC (0x7U << 11)
200
201#define LPC_DMA_CH_CFG_IE (1U << 14)
202#define LPC_DMA_CH_CFG_ITC (1U << 15)
203#define LPC_DMA_CH_CFG_LOCK (1U << 16)
204#define LPC_DMA_CH_CFG_ACTIVE (1U << 17)
205#define LPC_DMA_CH_CFG_HALT (1U << 18)
206
207/** @} */
208
209/** @} */
210
211#ifdef __cplusplus
212}
213#endif /* __cplusplus */
214
215#endif /* LIBBSP_ARM_SHARED_LPC_DMA_H */
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