[7a6f8d0] | 1 | /** |
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| 2 | * @file |
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| 3 | * |
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| 4 | * @ingroup lpc_dma |
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| 5 | * |
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| 6 | * @brief DMA API. |
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| 7 | */ |
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| 8 | |
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| 9 | /* |
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| 10 | * Copyright (c) 2010 |
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| 11 | * embedded brains GmbH |
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| 12 | * Obere Lagerstr. 30 |
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| 13 | * D-82178 Puchheim |
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| 14 | * Germany |
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| 15 | * <rtems@embedded-brains.de> |
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| 16 | * |
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| 17 | * The license and distribution terms for this file may be |
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| 18 | * found in the file LICENSE in this distribution or at |
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| 19 | * http://www.rtems.com/license/LICENSE. |
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| 20 | */ |
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| 21 | |
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| 22 | #ifndef LIBBSP_ARM_SHARED_LPC_DMA_H |
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| 23 | #define LIBBSP_ARM_SHARED_LPC_DMA_H |
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| 24 | |
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| 25 | #include <stdint.h> |
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| 26 | |
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| 27 | #ifdef __cplusplus |
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| 28 | extern "C" { |
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| 29 | #endif |
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| 30 | |
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| 31 | /** |
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| 32 | * @defgroup lpc_dma DMA Support |
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| 33 | * |
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| 34 | * @ingroup lpc |
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| 35 | * |
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| 36 | * @brief DMA support. |
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| 37 | * |
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| 38 | * @{ |
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| 39 | */ |
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| 40 | |
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| 41 | /** |
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| 42 | * @brief DMA descriptor item. |
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| 43 | */ |
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| 44 | typedef struct { |
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| 45 | uint32_t src; |
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| 46 | uint32_t dest; |
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| 47 | uint32_t lli; |
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| 48 | uint32_t ctrl; |
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| 49 | } lpc_dma_descriptor; |
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| 50 | |
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| 51 | /** |
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| 52 | * @brief DMA channel block. |
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| 53 | */ |
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| 54 | typedef struct { |
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| 55 | lpc_dma_descriptor desc; |
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| 56 | uint32_t cfg; |
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| 57 | uint32_t reserved [3]; |
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| 58 | } lpc_dma_channel; |
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| 59 | |
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| 60 | /** |
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| 61 | * @brief DMA control block. |
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| 62 | */ |
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| 63 | typedef struct { |
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| 64 | uint32_t int_stat; |
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| 65 | uint32_t int_tc_stat; |
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| 66 | uint32_t int_tc_clear; |
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| 67 | uint32_t int_err_stat; |
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| 68 | uint32_t int_err_clear; |
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| 69 | uint32_t raw_tc_stat; |
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| 70 | uint32_t raw_err_stat; |
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| 71 | uint32_t enabled_channels; |
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| 72 | uint32_t soft_burst_req; |
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| 73 | uint32_t soft_single_req; |
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| 74 | uint32_t soft_last_burst_req; |
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| 75 | uint32_t soft_last_single_req; |
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| 76 | uint32_t cfg; |
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| 77 | uint32_t sync; |
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| 78 | uint32_t reserved [50]; |
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| 79 | lpc_dma_channel channels []; |
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| 80 | } lpc_dma; |
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| 81 | |
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| 82 | /** |
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| 83 | * @name DMA Configuration Register Defines |
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| 84 | * |
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| 85 | * @{ |
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| 86 | */ |
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| 87 | |
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| 88 | #define LPC_DMA_CFG_EN (1U << 0) |
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| 89 | #define LPC_DMA_CFG_M_0 (1U << 1) |
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| 90 | #define LPC_DMA_CFG_M_1 (1U << 2) |
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| 91 | |
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| 92 | /** @} */ |
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| 93 | |
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| 94 | /** |
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| 95 | * @name DMA Channel Control Register Defines |
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| 96 | * |
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| 97 | * @{ |
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| 98 | */ |
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| 99 | |
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| 100 | #define LPC_DMA_CH_CTRL_TSZ_MASK 0xfffU |
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| 101 | #define LPC_DMA_CH_CTRL_TSZ_MAX 0xfffU |
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| 102 | |
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| 103 | #define LPC_DMA_CH_CTRL_SB_MASK (0x7U << 12) |
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| 104 | #define LPC_DMA_CH_CTRL_SB_1 (0x0U << 12) |
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| 105 | #define LPC_DMA_CH_CTRL_SB_4 (0x1U << 12) |
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| 106 | #define LPC_DMA_CH_CTRL_SB_8 (0x2U << 12) |
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| 107 | #define LPC_DMA_CH_CTRL_SB_16 (0x3U << 12) |
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| 108 | #define LPC_DMA_CH_CTRL_SB_32 (0x4U << 12) |
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| 109 | #define LPC_DMA_CH_CTRL_SB_64 (0x5U << 12) |
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| 110 | #define LPC_DMA_CH_CTRL_SB_128 (0x6U << 12) |
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| 111 | #define LPC_DMA_CH_CTRL_SB_256 (0x7U << 12) |
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| 112 | |
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| 113 | #define LPC_DMA_CH_CTRL_DB_MASK (0x7U << 15) |
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| 114 | #define LPC_DMA_CH_CTRL_DB_1 (0x0U << 15) |
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| 115 | #define LPC_DMA_CH_CTRL_DB_4 (0x1U << 15) |
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| 116 | #define LPC_DMA_CH_CTRL_DB_8 (0x2U << 15) |
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| 117 | #define LPC_DMA_CH_CTRL_DB_16 (0x3U << 15) |
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| 118 | #define LPC_DMA_CH_CTRL_DB_32 (0x4U << 15) |
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| 119 | #define LPC_DMA_CH_CTRL_DB_64 (0x5U << 15) |
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| 120 | #define LPC_DMA_CH_CTRL_DB_128 (0x6U << 15) |
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| 121 | #define LPC_DMA_CH_CTRL_DB_256 (0x7U << 15) |
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| 122 | |
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| 123 | #define LPC_DMA_CH_CTRL_SW_MASK (0x7U << 18) |
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| 124 | #define LPC_DMA_CH_CTRL_SW_8 (0x0U << 18) |
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| 125 | #define LPC_DMA_CH_CTRL_SW_16 (0x1U << 18) |
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| 126 | #define LPC_DMA_CH_CTRL_SW_32 (0x2U << 18) |
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| 127 | |
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| 128 | #define LPC_DMA_CH_CTRL_DW_MASK (0x7U << 21) |
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| 129 | #define LPC_DMA_CH_CTRL_DW_8 (0x0U << 21) |
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| 130 | #define LPC_DMA_CH_CTRL_DW_16 (0x1U << 21) |
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| 131 | #define LPC_DMA_CH_CTRL_DW_32 (0x2U << 21) |
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| 132 | |
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| 133 | #define LPC_DMA_CH_CTRL_SM_0 (0U << 24) |
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| 134 | #define LPC_DMA_CH_CTRL_SM_1 (1U << 24) |
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| 135 | |
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| 136 | #define LPC_DMA_CH_CTRL_DM_0 (0U << 25) |
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| 137 | #define LPC_DMA_CH_CTRL_DM_1 (1U << 25) |
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| 138 | |
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| 139 | #define LPC_DMA_CH_CTRL_SI (1U << 26) |
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| 140 | #define LPC_DMA_CH_CTRL_DI (1U << 27) |
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| 141 | #define LPC_DMA_CH_CTRL_ITC (1U << 31) |
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| 142 | |
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| 143 | /** @} */ |
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| 144 | |
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| 145 | /** |
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| 146 | * @name DMA Channel Configuration Register Defines |
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| 147 | * |
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| 148 | * @{ |
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| 149 | */ |
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| 150 | |
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| 151 | #define LPC_DMA_CH_CFG_EN (1U << 0) |
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| 152 | |
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| 153 | #define LPC_DMA_CH_CFG_SPER_MASK (0xfU << 1) |
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| 154 | #define LPC_DMA_CH_CFG_SPER_SHIFT 1 |
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| 155 | #define LPC_DMA_CH_CFG_SPER_0 (0x0U << 1) |
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| 156 | #define LPC_DMA_CH_CFG_SPER_1 (0x1U << 1) |
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| 157 | #define LPC_DMA_CH_CFG_SPER_2 (0x2U << 1) |
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| 158 | #define LPC_DMA_CH_CFG_SPER_3 (0x3U << 1) |
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| 159 | #define LPC_DMA_CH_CFG_SPER_4 (0x4U << 1) |
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| 160 | #define LPC_DMA_CH_CFG_SPER_5 (0x5U << 1) |
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| 161 | #define LPC_DMA_CH_CFG_SPER_6 (0x6U << 1) |
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| 162 | #define LPC_DMA_CH_CFG_SPER_7 (0x7U << 1) |
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| 163 | #define LPC_DMA_CH_CFG_SPER_8 (0x8U << 1) |
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| 164 | #define LPC_DMA_CH_CFG_SPER_9 (0x9U << 1) |
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| 165 | #define LPC_DMA_CH_CFG_SPER_10 (0xaU << 1) |
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| 166 | #define LPC_DMA_CH_CFG_SPER_11 (0xbU << 1) |
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| 167 | #define LPC_DMA_CH_CFG_SPER_12 (0xcU << 1) |
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| 168 | #define LPC_DMA_CH_CFG_SPER_13 (0xdU << 1) |
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| 169 | #define LPC_DMA_CH_CFG_SPER_14 (0xeU << 1) |
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| 170 | #define LPC_DMA_CH_CFG_SPER_15 (0xfU << 1) |
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| 171 | |
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| 172 | #define LPC_DMA_CH_CFG_DPER_MASK (0xfU << 6) |
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| 173 | #define LPC_DMA_CH_CFG_DPER_SHIFT 6 |
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| 174 | #define LPC_DMA_CH_CFG_DPER_0 (0x0U << 6) |
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| 175 | #define LPC_DMA_CH_CFG_DPER_1 (0x1U << 6) |
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| 176 | #define LPC_DMA_CH_CFG_DPER_2 (0x2U << 6) |
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| 177 | #define LPC_DMA_CH_CFG_DPER_3 (0x3U << 6) |
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| 178 | #define LPC_DMA_CH_CFG_DPER_4 (0x4U << 6) |
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| 179 | #define LPC_DMA_CH_CFG_DPER_5 (0x5U << 6) |
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| 180 | #define LPC_DMA_CH_CFG_DPER_6 (0x6U << 6) |
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| 181 | #define LPC_DMA_CH_CFG_DPER_7 (0x7U << 6) |
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| 182 | #define LPC_DMA_CH_CFG_DPER_8 (0x8U << 6) |
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| 183 | #define LPC_DMA_CH_CFG_DPER_9 (0x9U << 6) |
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| 184 | #define LPC_DMA_CH_CFG_DPER_10 (0xaU << 6) |
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| 185 | #define LPC_DMA_CH_CFG_DPER_11 (0xbU << 6) |
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| 186 | #define LPC_DMA_CH_CFG_DPER_12 (0xcU << 6) |
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| 187 | #define LPC_DMA_CH_CFG_DPER_13 (0xdU << 6) |
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| 188 | #define LPC_DMA_CH_CFG_DPER_14 (0xeU << 6) |
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| 189 | #define LPC_DMA_CH_CFG_DPER_15 (0xfU << 6) |
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| 190 | |
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| 191 | #define LPC_DMA_CH_CFG_FLOW_MASK (0x7U << 11) |
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| 192 | #define LPC_DMA_CH_CFG_FLOW_MEM_TO_MEM_DMA (0x0U << 11) |
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| 193 | #define LPC_DMA_CH_CFG_FLOW_MEM_TO_PER_DMA (0x1U << 11) |
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| 194 | #define LPC_DMA_CH_CFG_FLOW_PER_TO_MEM_DMA (0x2U << 11) |
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| 195 | #define LPC_DMA_CH_CFG_FLOW_PER_TO_PER_DMA (0x3U << 11) |
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| 196 | #define LPC_DMA_CH_CFG_FLOW_PER_TO_PER_DEST (0x4U << 11) |
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| 197 | #define LPC_DMA_CH_CFG_FLOW_MEM_TO_PER_PER (0x5U << 11) |
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| 198 | #define LPC_DMA_CH_CFG_FLOW_PER_TO_MEM_PER (0x6U << 11) |
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| 199 | #define LPC_DMA_CH_CFG_FLOW_PER_TO_PER_SRC (0x7U << 11) |
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| 200 | |
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| 201 | #define LPC_DMA_CH_CFG_IE (1U << 14) |
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| 202 | #define LPC_DMA_CH_CFG_ITC (1U << 15) |
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| 203 | #define LPC_DMA_CH_CFG_LOCK (1U << 16) |
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| 204 | #define LPC_DMA_CH_CFG_ACTIVE (1U << 17) |
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| 205 | #define LPC_DMA_CH_CFG_HALT (1U << 18) |
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| 206 | |
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| 207 | /** @} */ |
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| 208 | |
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| 209 | /** @} */ |
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| 210 | |
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| 211 | #ifdef __cplusplus |
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| 212 | } |
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| 213 | #endif /* __cplusplus */ |
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| 214 | |
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| 215 | #endif /* LIBBSP_ARM_SHARED_LPC_DMA_H */ |
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