1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup lpc_clock |
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5 | * |
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6 | * @brief Clock driver configuration. |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2009-2012 embedded brains GmbH. All rights reserved. |
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11 | * |
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12 | * embedded brains GmbH |
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13 | * Obere Lagerstr. 30 |
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14 | * 82178 Puchheim |
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15 | * Germany |
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16 | * <rtems@embedded-brains.de> |
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17 | * |
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18 | * The license and distribution terms for this file may be |
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19 | * found in the file LICENSE in this distribution or at |
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20 | * http://www.rtems.org/license/LICENSE. |
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21 | */ |
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22 | |
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23 | #include <rtems.h> |
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24 | |
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25 | #include <bsp/lpc-clock-config.h> |
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26 | #include <bsp/lpc-timer.h> |
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27 | |
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28 | #ifdef ARM_MULTILIB_ARCH_V4 |
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29 | |
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30 | /* This is defined in ../../../shared/clockdrv_shell.h */ |
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31 | void Clock_isr(rtems_irq_hdl_param arg); |
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32 | |
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33 | static volatile lpc_timer *const lpc_clock = |
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34 | (volatile lpc_timer *) LPC_CLOCK_TIMER_BASE; |
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35 | |
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36 | static void lpc_clock_at_tick(void) |
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37 | { |
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38 | lpc_clock->ir = LPC_TIMER_IR_MR0; |
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39 | } |
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40 | |
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41 | static void lpc_clock_handler_install(void) |
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42 | { |
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43 | rtems_status_code sc = RTEMS_SUCCESSFUL; |
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44 | |
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45 | sc = rtems_interrupt_handler_install( |
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46 | LPC_CLOCK_INTERRUPT, |
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47 | "Clock", |
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48 | RTEMS_INTERRUPT_UNIQUE, |
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49 | (rtems_interrupt_handler) Clock_isr, |
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50 | NULL |
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51 | ); |
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52 | if (sc != RTEMS_SUCCESSFUL) { |
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53 | rtems_fatal_error_occurred(0xdeadbeef); |
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54 | } |
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55 | } |
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56 | |
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57 | static void lpc_clock_initialize(void) |
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58 | { |
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59 | uint64_t interval = ((uint64_t) LPC_CLOCK_REFERENCE |
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60 | * (uint64_t) rtems_configuration_get_microseconds_per_tick()) / 1000000; |
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61 | |
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62 | /* Enable module */ |
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63 | LPC_CLOCK_MODULE_ENABLE(); |
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64 | |
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65 | /* Reset timer */ |
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66 | lpc_clock->tcr = LPC_TIMER_TCR_RST; |
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67 | |
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68 | /* Clear interrupt flags */ |
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69 | lpc_clock->ir = LPC_TIMER_IR_ALL; |
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70 | |
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71 | /* Set timer mode */ |
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72 | lpc_clock->ccr = 0; |
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73 | |
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74 | /* Timer is incremented every PERIPH_CLK tick */ |
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75 | lpc_clock->pr = 0; |
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76 | |
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77 | /* Set match registers */ |
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78 | lpc_clock->mr0 = (uint32_t) interval; |
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79 | |
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80 | /* Generate interrupt and reset counter on match with MR0 */ |
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81 | lpc_clock->mcr = LPC_TIMER_MCR_MR0_INTR | LPC_TIMER_MCR_MR0_RST; |
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82 | |
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83 | /* No external match */ |
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84 | lpc_clock->emr = 0x0; |
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85 | |
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86 | /* Enable timer */ |
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87 | lpc_clock->tcr = LPC_TIMER_TCR_EN; |
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88 | } |
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89 | |
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90 | static void lpc_clock_cleanup(void) |
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91 | { |
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92 | rtems_status_code sc = RTEMS_SUCCESSFUL; |
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93 | |
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94 | /* Disable timer */ |
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95 | lpc_clock->tcr = 0x0; |
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96 | |
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97 | /* Remove interrupt handler */ |
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98 | sc = rtems_interrupt_handler_remove( |
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99 | LPC_CLOCK_INTERRUPT, |
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100 | (rtems_interrupt_handler) Clock_isr, |
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101 | NULL |
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102 | ); |
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103 | if (sc != RTEMS_SUCCESSFUL) { |
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104 | rtems_fatal_error_occurred(0xdeadbeef); |
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105 | } |
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106 | } |
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107 | |
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108 | static uint32_t lpc_clock_nanoseconds_since_last_tick(void) |
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109 | { |
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110 | uint64_t k = (1000000000ULL << 32) / LPC_CLOCK_REFERENCE; |
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111 | uint64_t c = lpc_clock->tc; |
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112 | |
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113 | if ((lpc_clock->ir & LPC_TIMER_IR_MR0) != 0) { |
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114 | c = lpc_clock->tc + lpc_clock->mr0; |
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115 | } |
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116 | |
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117 | return (uint32_t) ((c * k) >> 32); |
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118 | } |
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119 | |
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120 | #define Clock_driver_support_at_tick() lpc_clock_at_tick() |
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121 | #define Clock_driver_support_initialize_hardware() lpc_clock_initialize() |
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122 | #define Clock_driver_support_install_isr(isr, old_isr) \ |
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123 | do { \ |
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124 | lpc_clock_handler_install(); \ |
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125 | old_isr = NULL; \ |
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126 | } while (0) |
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127 | |
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128 | #define Clock_driver_support_shutdown_hardware() lpc_clock_cleanup() |
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129 | #define Clock_driver_nanoseconds_since_last_tick \ |
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130 | lpc_clock_nanoseconds_since_last_tick |
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131 | |
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132 | /* Include shared source clock driver code */ |
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133 | #include "../../../../shared/clockdrv_shell.h" |
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134 | |
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135 | #endif /* ARM_MULTILIB_ARCH_V4 */ |
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