1 | /* irq_asm.S |
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2 | * |
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3 | * This file contains the implementation of the IRQ handler |
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4 | * |
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5 | * Copyright (c) 2002 Advent Networks, Inc. |
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6 | * Jay Monkman <jmonkman@adventnetworks.com> |
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7 | * |
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8 | * CopyRight (C) 2000 Canon Research France SA. |
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9 | * Emmanuel Raguet, mailto:raguet@crf.canon.fr |
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10 | * |
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11 | * Modified Andy Dachs <a.dachs@sstl.co.uk> |
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12 | * Copyright (c) 2001 Surrey Satellite Technolgy Limited |
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13 | * |
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14 | * The license and distribution terms for this file may be |
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15 | * found in found in the file LICENSE in this distribution or at |
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16 | * http://www.OARcorp.com/rtems/license.html. |
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17 | * |
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18 | * $Id$ |
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19 | */ |
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20 | |
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21 | #include "asm.h" |
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22 | #define __asm__ |
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23 | |
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24 | .globl _ISR_Handler |
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25 | _ISR_Handler: |
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26 | stmdb sp!, {r0, r1, r2, r3} /* save regs on INT stack */ |
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27 | stmdb sp!, {lr} /* now safe to call C funcs */ |
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28 | |
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29 | |
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30 | /* one nest level deeper */ |
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31 | ldr r0, =_ISR_Nest_level |
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32 | ldr r1, [r0] |
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33 | add r1, r1,#1 |
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34 | str r1, [r0] |
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35 | |
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36 | /* disable multitasking */ |
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37 | ldr r0, =_Thread_Dispatch_disable_level |
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38 | ldr r1, [r0] |
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39 | add r1, r1,#1 |
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40 | str r1, [r0] |
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41 | |
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42 | /* BSP specific function to INT handler */ |
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43 | /* FIXME: I'm not sure why I can't save just r12. I'm also */ |
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44 | /* not sure which of r1-r3 are important. */ |
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45 | stmdb sp!, {r0-r12} |
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46 | bl ExecuteITHandler |
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47 | ldmia sp!, {r0-r12} |
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48 | |
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49 | /* one less nest level */ |
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50 | ldr r0, =_ISR_Nest_level |
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51 | ldr r1, [r0] |
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52 | sub r1, r1,#1 |
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53 | str r1, [r0] |
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54 | |
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55 | /* unnest multitasking */ |
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56 | ldr r0, =_Thread_Dispatch_disable_level |
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57 | ldr r1, [r0] |
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58 | sub r1, r1,#1 |
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59 | str r1, [r0] |
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60 | |
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61 | /* If thread dispatching is disabled, exit */ |
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62 | cmp r1, #0 |
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63 | bne exitit |
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64 | |
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65 | /* If a task switch is necessary, call scheduler */ |
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66 | ldr r0, =_Context_Switch_necessary |
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67 | ldr r1, [r0] |
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68 | cmp r1, #0 |
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69 | |
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70 | /* since bframe is going to clear _ISR_Signals_to_thread_executing, */ |
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71 | /* we need to load it here */ |
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72 | ldr r0, =_ISR_Signals_to_thread_executing |
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73 | ldr r1, [r0] |
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74 | bne bframe |
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75 | |
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76 | /* If a signals to be sent (_ISR_Signals_to_thread_executing != 0), */ |
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77 | /* call scheduler */ |
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78 | cmp r1, #0 |
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79 | beq exitit |
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80 | |
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81 | /* _ISR_Signals_to_thread_executing = FALSE */ |
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82 | mov r1, #0 |
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83 | str r1, [r0] |
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84 | |
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85 | bframe: |
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86 | |
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87 | /* Now we need to set up the return from this ISR to be _ISR_Dispatch */ |
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88 | /* To do that, we need to save the current lr_int and spsr_int on the */ |
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89 | /* SVC stack */ |
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90 | mrs r0, spsr |
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91 | ldmia sp!, {r1} /* get lr off stack */ |
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92 | stmdb sp!, {r1} |
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93 | mrs r2, cpsr |
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94 | orr r3, r2, #0x1 /* change to SVC mode */ |
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95 | msr cpsr_c, r3 |
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96 | |
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97 | /* now in SVC mode */ |
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98 | stmdb sp!, {r0, r1} /* put spsr_int and lr_int on SVC stack */ |
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99 | msr cpsr_c, r2 /* change back to INT mode */ |
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100 | |
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101 | /* now in INT mode */ |
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102 | |
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103 | /* replace lr with address of _ISR_Dispatch */ |
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104 | ldr lr, =_ISR_Dispatch |
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105 | add lr, lr, #0x4 /* On entry to an ISR, the lr is */ |
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106 | /* the return address + 4, so */ |
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107 | /* we have to emulate that */ |
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108 | ldmia sp!, {r0} /* out with the old */ |
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109 | stmdb sp!, {lr} /* in with the new (lr) */ |
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110 | |
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111 | |
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112 | mrs r0, spsr |
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113 | orr r0, r0, #0xc0 |
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114 | msr spsr, r0 |
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115 | |
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116 | exitit: |
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117 | ldmia sp!, {lr} /* restore regs from INT stack */ |
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118 | ldmia sp!, {r0, r1, r2, r3} /* restore regs from INT stack */ |
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119 | subs pc, lr, #4 /* return */ |
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120 | |
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121 | |
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122 | |
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123 | /* on entry to _ISR_Dispatch, we're in SVC mode */ |
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124 | .globl _ISR_Dispatch |
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125 | _ISR_Dispatch: |
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126 | stmdb sp!, {r0-r12,lr} /* save regs on SVC stack */ |
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127 | /* (now safe to call C funcs) */ |
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128 | /* we don't save lr, since */ |
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129 | /* it's just going to get */ |
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130 | /* overwritten */ |
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131 | |
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132 | bl _Thread_Dispatch |
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133 | ldmia sp!, {r0-r12, lr} |
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134 | |
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135 | stmdb sp!, {r0-r2} |
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136 | /* Now we have to screw with the stack */ |
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137 | mov r0, sp /* copy the SVC stack pointer */ |
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138 | |
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139 | mrs r1, cpsr |
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140 | bic r2, r1, #0x1 /* change to INT mode */ |
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141 | orr r2, r2, #0xc0 /* disable interrupts */ |
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142 | msr cpsr_c, r2 |
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143 | |
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144 | /* now in INT mode */ |
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145 | stmdb sp!, {r4, r5, r6} /* save temp vars on INT stack */ |
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146 | ldmia r0!, {r4, r5, r6} /* Get r0-r3 from SVC stack */ |
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147 | stmdb sp!, {r4, r5, r6} /* and save them on INT stack */ |
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148 | |
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149 | ldmia r0!, {r4, r5} /* get saved values from SVC stack */ |
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150 | /* r4=spsr, r5=lr */ |
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151 | mov lr, r5 /* restore lr_int */ |
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152 | msr spsr, r4 /* restore spsr_int */ |
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153 | |
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154 | /* switch to SVC mode, update sp, then return to INT mode */ |
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155 | msr cpsr_c, r1 /* switch to SVC mode */ |
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156 | mov sp, r0 /* update sp_svc */ |
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157 | msr cpsr_c, r2 /* switch back to INT mode */ |
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158 | |
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159 | /* pop all the registers from the stack */ |
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160 | ldmia sp!, {r0, r1, r2} |
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161 | ldmia sp!, {r4, r5, r6} |
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162 | |
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163 | /* Finally, we can return to the interrupted task */ |
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164 | subs pc, lr, #4 |
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165 | |
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166 | |
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167 | |
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168 | |
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169 | |
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