source: rtems/c/src/lib/libbsp/arm/shared/irq/irq_asm.S @ 8c408ed4

4.104.114.84.95
Last change on this file since 8c408ed4 was 8c408ed4, checked in by Joel Sherrill <joel.sherrill@…>, on Jul 30, 2002 at 11:20:19 PM

2002-07-30 Jay Monkman <jtm@…>

  • irq/irq_asm.S: ARM port works well enough to run all sptests, tmtests, and ttcp. In addition to general cleanup, there has been considerable optimization to interrupt disable/enable, endian swapping, and context switching.
  • Property mode set to 100644
File size: 5.6 KB
Line 
1/* irq_asm.S
2 *
3 *  This file contains the implementation of the IRQ handler
4 *
5 *  Copyright (c) 2002 Advent Networks, Inc.
6 *      Jay Monkman <jmonkman@adventnetworks.com>
7 *
8 *  CopyRight (C) 2000 Canon Research France SA.
9 *  Emmanuel Raguet,  mailto:raguet@crf.canon.fr
10 *
11 *  Modified Andy Dachs <a.dachs@sstl.co.uk>
12 *  Copyright (c) 2001 Surrey Satellite Technolgy Limited
13 *
14 *  The license and distribution terms for this file may be
15 *  found in found in the file LICENSE in this distribution or at
16 *  http://www.OARcorp.com/rtems/license.html.
17 *
18 *  $Id$
19 */
20
21#include "asm.h"
22#define __asm__
23
24        .globl _ISR_Handler
25_ISR_Handler:
26        stmdb   sp!, {r0, r1, r2, r3, r12}   /* save regs on INT stack */
27        stmdb   sp!, {lr}               /*    now safe to call C funcs */
28       
29
30/* one nest level deeper */
31        ldr     r0, =_ISR_Nest_level
32        ldr     r1, [r0]
33        add     r1, r1,#1
34        str     r1, [r0]
35       
36/* disable multitasking */
37        ldr     r0, =_Thread_Dispatch_disable_level         
38        ldr     r1, [r0]
39        add     r1, r1,#1
40        str     r1, [r0]
41
42/* BSP specific function to INT handler */
43        /* FIXME: I'm not sure why I can't save just r12. I'm also  */
44        /*     not sure which of r1-r3 are important.               */
45        bl      ExecuteITHandler
46
47/* one less nest level  */     
48        ldr     r0, =_ISR_Nest_level
49        ldr     r1, [r0]
50        sub     r1, r1,#1
51        str     r1, [r0]
52       
53/* unnest multitasking */
54        ldr     r0, =_Thread_Dispatch_disable_level
55        ldr     r1, [r0]
56        sub     r1, r1,#1
57        str     r1, [r0]
58
59/* If thread dispatching is disabled, exit */
60        cmp     r1, #0
61        bne     exitit
62
63/* If a task switch is necessary, call scheduler */
64        ldr     r0, =_Context_Switch_necessary
65        ldr     r1, [r0]
66        cmp     r1, #0
67       
68        /* since bframe is going to clear _ISR_Signals_to_thread_executing, */
69        /*    we need to load it here */
70        ldr     r0, =_ISR_Signals_to_thread_executing   
71        ldr     r1, [r0]
72        bne     bframe
73       
74/* If a signals to be sent (_ISR_Signals_to_thread_executing != 0),        */
75/*  call scheduler */
76        cmp     r1, #0
77        beq     exitit
78       
79/* _ISR_Signals_to_thread_executing = FALSE */
80        mov     r1, #0
81        str     r1, [r0]
82
83bframe:
84
85/* Now we need to set up the return from this ISR to be _ISR_Dispatch */
86/* To do that, we need to save the current lr_int and spsr_int on the */
87/* SVC stack                                                          */
88        mrs     r0, spsr
89        ldmia   sp!, {r1}       /* get lr off stack */
90        stmdb   sp!, {r1}
91        mrs     r2, cpsr   
92        orr     r3, r2, #0x1    /* change to SVC mode */
93        msr     cpsr_c, r3
94
95        /* now in SVC mode */
96        stmdb   sp!, {r0, r1}   /* put spsr_int and lr_int on SVC stack */
97        msr     cpsr_c, r2      /* change back to INT mode */
98
99        /* now in INT mode */
100
101        /* replace lr with address of _ISR_Dispatch */
102        ldr     lr, =_ISR_Dispatch_p_4    /* On entry to an ISR, the lr is */
103                                          /*    the return address + 4, so */
104                                          /*    we have to emulate that    */
105        ldmia   sp!, {r1}                 /* out with the old          */
106        stmdb   sp!, {lr}                 /*    in with the new (lr) */
107
108       
109        orr     r0, r0, #0xc0
110        msr     spsr, r0
111                                       
112exitit:
113        ldmia   sp!, {lr}                     /* restore regs from INT stack */
114        ldmia   sp!, {r0, r1, r2, r3, r12}    /* restore regs from INT stack */
115        subs    pc, lr, #4                /* return */
116
117
118
119        /* on entry to _ISR_Dispatch, we're in SVC mode */     
120        .globl _ISR_Dispatch
121_ISR_Dispatch:
122        stmdb   sp!, {r0-r3, r12,lr}      /* save regs on SVC stack */
123                                          /*    (now safe to call C funcs) */
124                                          /*    we don't save lr, since  */
125                                          /*    it's just going to get   */
126                                          /*    overwritten              */
127_ISR_Dispatch_p_4:     
128        bl      _Thread_Dispatch
129        ldmia   sp!, {r0-r3, r12, lr}
130
131        stmdb   sp!, {r0-r2}
132        /* Now we have to screw with the stack */
133        mov     r0, sp                  /* copy the SVC stack pointer */
134       
135        mrs     r1, cpsr   
136        bic     r2, r1, #0x1            /* change to INT mode */
137        orr     r2, r2, #0xc0           /* disable interrupts */
138        msr     cpsr_c, r2
139
140        /* now in INT mode */
141        stmdb   sp!, {r4, r5, r6}   /* save temp vars on INT stack */
142        ldmia   r0!, {r4, r5, r6}   /* Get r0-r3 from SVC stack */
143        stmdb   sp!, {r4, r5, r6}   /*    and save them on INT stack */
144       
145        ldmia   r0!, {r4, r5}           /* get saved values from SVC stack */
146                                        /*      r4=spsr, r5=lr */
147        mov     lr,   r5                /* restore lr_int */
148        msr     spsr, r4                /* restore spsr_int */
149
150        /* switch to SVC mode, update sp, then return to INT mode */
151        msr     cpsr_c, r1              /* switch to SVC mode */
152        mov     sp, r0                  /* update sp_svc */
153        msr     cpsr_c, r2              /* switch back to INT mode */
154
155        /* pop all the registers from the stack */
156        ldmia   sp!, {r0, r1, r2}
157        ldmia   sp!, {r4, r5, r6}
158
159        /* Finally, we can return to the interrupted task */
160        subs    pc, lr, #4
161
162
163
164
165
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