1 | /* irq_asm.S |
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2 | * |
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3 | * This file contains the implementation of the IRQ handler |
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4 | * |
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5 | * CopyRight (C) 2000 Canon Research France SA. |
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6 | * Emmanuel Raguet, mailto:raguet@crf.canon.fr |
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7 | * |
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8 | * The license and distribution terms for this file may be |
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9 | * found in found in the file LICENSE in this distribution or at |
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10 | * http://www.OARcorp.com/rtems/license.html. |
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11 | * |
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12 | * $Id$ |
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13 | */ |
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14 | |
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15 | #include "asm.h" |
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16 | #define __asm__ |
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17 | #include <registers.h> |
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18 | |
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19 | |
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20 | /* |
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21 | * WARNING : register r5 is important. If you need to use it, |
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22 | * to forget to save it !!!!!!!!!! |
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23 | */ |
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24 | |
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25 | .globl _ISR_Handler |
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26 | _ISR_Handler: |
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27 | stmdb sp!, {r4,r5,lr} /* save regs on INT stack */ |
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28 | mrs r4, cpsr /* save current CSPR */ |
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29 | mov r5, r4 /* copy CSPR */ |
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30 | orr r4, r4, #3 |
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31 | msr cpsr, r4 /* switch to SVC mode */ |
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32 | |
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33 | stmdb sp!, {r0-r3,r12,r14} /* save scratch regs on SVC stack */ |
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34 | |
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35 | msr cpsr, r5 /* switch back to INT mode */ |
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36 | |
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37 | ldr r0, =_ISR_Nest_level /* one nest level deeper */ |
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38 | ldr r1, [r0] |
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39 | add r1, r1,#1 |
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40 | str r1, [r0] |
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41 | |
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42 | ldr r0, =_Thread_Dispatch_disable_level /* disable multitasking */ |
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43 | ldr r1, [r0] |
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44 | add r1, r1,#1 |
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45 | str r1, [r0] |
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46 | |
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47 | b ExecuteITHandler /* BSP specific function to INT handler */ |
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48 | |
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49 | .globl ReturnFromHandler |
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50 | ReturnFromHandler : |
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51 | ldr r0, =_ISR_Nest_level /* one less nest level */ |
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52 | ldr r1, [r0] |
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53 | sub r1, r1,#1 |
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54 | str r1, [r0] |
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55 | |
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56 | ldr r0, =_Thread_Dispatch_disable_level /* unnest multitasking */ |
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57 | ldr r1, [r0] |
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58 | sub r1, r1,#1 |
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59 | str r1, [r0] |
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60 | |
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61 | cmp r1, #0 /* is dispatch enabled */ |
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62 | bne exitit /* Yes, then exit */ |
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63 | |
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64 | ldr r0, =_Context_Switch_necessary /* task switch necessary ? */ |
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65 | ldr r1, [r0] |
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66 | cmp r1, #0 |
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67 | bne schedule /* yes, call scheduler */ |
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68 | |
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69 | ldr r0, =_ISR_Signals_to_thread_executing |
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70 | ldr r1, [r0] /* signals sent to Run_thread */ |
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71 | cmp r1, #0 /* while in interrupt handler ? */ |
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72 | beq exitit /* No, exit */ |
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73 | |
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74 | bframe: |
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75 | mov r1, #0 /* _ISR_Signals_to_thread_executing = FALSE */ |
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76 | str r1, [r0] |
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77 | /* |
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78 | * At this point, we need a complete exception context for the |
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79 | * current thread. We need to complete the interrupt exception |
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80 | * with the "not-yet-saved" registers |
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81 | */ |
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82 | /* |
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83 | * currently exception context = interrupt handler |
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84 | * it needs to be optimized |
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85 | */ |
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86 | bl _ThreadProcessSignalsFromIrq |
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87 | b exitit |
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88 | |
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89 | schedule: |
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90 | /* |
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91 | * the scratch registers have already been saved and we are already |
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92 | * back on the thread system stack. So we can call _Thread_Displatch |
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93 | * directly |
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94 | */ |
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95 | bl _Thread_Dispatch |
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96 | /* |
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97 | * fall through exit to restore complete contex (scratch registers |
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98 | * eip, CS, Flags). |
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99 | */ |
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100 | exitit: |
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101 | b AckControler /* BSP specific function to ack PIC */ |
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102 | |
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103 | .globl ReturnFromAck |
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104 | ReturnFromAck : |
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105 | ldmia sp!, {r0-r3,r12,r14} /* restore regs from SVC stack */ |
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106 | msr cpsr, r5 /* switch back to INT mode */ |
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107 | ldmia sp!, {r4,r5,lr} /* restore regs from INT stack */ |
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108 | subs pc,r14,#4 /* return */ |
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109 | |
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