source: rtems/c/src/lib/libbsp/arm/shared/include/arm-pl011-regs.h @ b7212b9

4.115
Last change on this file since b7212b9 was b7212b9, checked in by Szkocsovszki Zsolt <zsoltisharkboy@…>, on 12/23/13 at 02:07:02

libbsp/arm: add doxygen to arm shared headers
  • Property mode set to 100644
File size: 4.6 KB
Line 
1/**
2 *  @file
3 *
4 *  @ingroup arm_shared
5 *
6 *  @brief ARM PL011 Register definitions
7 */
8
9/*
10 * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
11 *
12 *  embedded brains GmbH
13 *  Dornierstr. 4
14 *  82178 Puchheim
15 *  Germany
16 *  <info@embedded-brains.de>
17 *
18 * The license and distribution terms for this file may be
19 * found in the file LICENSE in this distribution or at
20 * http://www.rtems.com/license/LICENSE.
21 */
22
23#ifndef LIBBSP_ARM_SHARED_ARM_PL011_REGS_H
24#define LIBBSP_ARM_SHARED_ARM_PL011_REGS_H
25
26#include <bsp/utility.h>
27
28typedef struct {
29  uint32_t uartdr;
30#define PL011_UARTDR_OE BSP_BIT32(11)
31#define PL011_UARTDR_BE BSP_BIT32(10)
32#define PL011_UARTDR_PE BSP_BIT32(9)
33#define PL011_UARTDR_FE BSP_BIT32(8)
34#define PL011_UARTDR_DATA(val) BSP_FLD32(val, 0, 7)
35#define PL011_UARTDR_DATA_GET(reg) BSP_FLD32GET(reg, 0, 7)
36#define PL011_UARTDR_DATA_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
37  uint32_t uartrsr_uartecr;
38#define PL011_UARTRSR_UARTECR_OE BSP_BIT32(3)
39#define PL011_UARTRSR_UARTECR_BE BSP_BIT32(2)
40#define PL011_UARTRSR_UARTECR_PE BSP_BIT32(1)
41#define PL011_UARTRSR_UARTECR_FE BSP_BIT32(0)
42  uint32_t reserved_08[4];
43  uint32_t uartfr;
44#define PL011_UARTFR_RI BSP_BIT32(8)
45#define PL011_UARTFR_TXFE BSP_BIT32(7)
46#define PL011_UARTFR_RXFF BSP_BIT32(6)
47#define PL011_UARTFR_TXFF BSP_BIT32(5)
48#define PL011_UARTFR_RXFE BSP_BIT32(4)
49#define PL011_UARTFR_BUSY BSP_BIT32(3)
50#define PL011_UARTFR_DCD BSP_BIT32(2)
51#define PL011_UARTFR_DSR BSP_BIT32(1)
52#define PL011_UARTFR_CTS BSP_BIT32(0)
53  uint32_t reserved_1c;
54  uint32_t uartilpr;
55#define PL011_UARTILPR_ILPDVSR(val) BSP_FLD32(val, 0, 7)
56#define PL011_UARTILPR_ILPDVSR_GET(reg) BSP_FLD32GET(reg, 0, 7)
57#define PL011_UARTILPR_ILPDVSR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
58  uint32_t uartibrd;
59#define PL011_UARTIBRD_BAUD_DIVINT(val) BSP_FLD32(val, 0, 15)
60#define PL011_UARTIBRD_BAUD_DIVINT_GET(reg) BSP_FLD32GET(reg, 0, 15)
61#define PL011_UARTIBRD_BAUD_DIVINT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15)
62  uint32_t uartfbrd;
63#define PL011_UARTFBRD_BAUD_DIVFRAC(val) BSP_FLD32(val, 0, 5)
64#define PL011_UARTFBRD_BAUD_DIVFRAC_GET(reg) BSP_FLD32GET(reg, 0, 5)
65#define PL011_UARTFBRD_BAUD_DIVFRAC_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5)
66  uint32_t uartlcr_h;
67#define PL011_UARTLCR_H_SPS BSP_BIT32(7)
68#define PL011_UARTLCR_H_WLEN(val) BSP_FLD32(val, 5, 6)
69#define PL011_UARTLCR_H_WLEN_GET(reg) BSP_FLD32GET(reg, 5, 6)
70#define PL011_UARTLCR_H_WLEN_SET(reg, val) BSP_FLD32SET(reg, val, 5, 6)
71#define PL011_UARTLCR_H_WLEN_5 0x00U
72#define PL011_UARTLCR_H_WLEN_6 0x01U
73#define PL011_UARTLCR_H_WLEN_7 0x02U
74#define PL011_UARTLCR_H_WLEN_8 0x03U
75#define PL011_UARTLCR_H_FEN BSP_BIT32(4)
76#define PL011_UARTLCR_H_STP2 BSP_BIT32(3)
77#define PL011_UARTLCR_H_EPS BSP_BIT32(2)
78#define PL011_UARTLCR_H_PEN BSP_BIT32(1)
79#define PL011_UARTLCR_H_BRK BSP_BIT32(0)
80  uint32_t uartcr;
81#define PL011_UARTCR_CTSEN BSP_BIT32(15)
82#define PL011_UARTCR_RTSEN BSP_BIT32(14)
83#define PL011_UARTCR_OUT2 BSP_BIT32(13)
84#define PL011_UARTCR_OUT1 BSP_BIT32(12)
85#define PL011_UARTCR_RTS BSP_BIT32(11)
86#define PL011_UARTCR_DTR BSP_BIT32(10)
87#define PL011_UARTCR_RXE BSP_BIT32(9)
88#define PL011_UARTCR_TXE BSP_BIT32(8)
89#define PL011_UARTCR_LBE BSP_BIT32(7)
90#define PL011_UARTCR_SIRLP BSP_BIT32(3)
91#define PL011_UARTCR_SIREN BSP_BIT32(2)
92#define PL011_UARTCR_UARTEN BSP_BIT32(1)
93  uint32_t uartifls;
94#define PL011_UARTIFLS_RXIFLSEL(val) BSP_FLD32(val, 3, 5)
95#define PL011_UARTIFLS_RXIFLSEL_GET(reg) BSP_FLD32GET(reg, 3, 5)
96#define PL011_UARTIFLS_RXIFLSEL_SET(reg, val) BSP_FLD32SET(reg, val, 3, 5)
97#define PL011_UARTIFLS_TXIFLSEL(val) BSP_FLD32(val, 0, 2)
98#define PL011_UARTIFLS_TXIFLSEL_GET(reg) BSP_FLD32GET(reg, 0, 2)
99#define PL011_UARTIFLS_TXIFLSEL_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2)
100  uint32_t uartimsc;
101  uint32_t uartris;
102  uint32_t uartmis;
103  uint32_t uarticr;
104#define PL011_UARTI_OEI BSP_BIT32(10)
105#define PL011_UARTI_BEI BSP_BIT32(9)
106#define PL011_UARTI_PEI BSP_BIT32(8)
107#define PL011_UARTI_FEI BSP_BIT32(7)
108#define PL011_UARTI_RTI BSP_BIT32(6)
109#define PL011_UARTI_TXI BSP_BIT32(5)
110#define PL011_UARTI_RXI BSP_BIT32(4)
111#define PL011_UARTI_DSRMI BSP_BIT32(3)
112#define PL011_UARTI_DCDMI BSP_BIT32(2)
113#define PL011_UARTI_CTSMI BSP_BIT32(1)
114#define PL011_UARTI_RIMI BSP_BIT32(0)
115  uint32_t uartdmacr;
116#define PL011_UARTDMACR_DMAONERR BSP_BIT32(2)
117#define PL011_UARTDMACR_TXDMAE BSP_BIT32(1)
118#define PL011_UARTDMACR_RXDMAE BSP_BIT32(0)
119  uint32_t reserved_4c[997];
120  uint32_t uartperiphid0;
121  uint32_t uartperiphid1;
122  uint32_t uartperiphid2;
123  uint32_t uartperiphid3;
124  uint32_t uartpcellid0;
125  uint32_t uartpcellid1;
126  uint32_t uartpcellid2;
127  uint32_t uartpcellid3;
128} pl011;
129
130#endif /* LIBBSP_ARM_SHARED_ARM_PL011_REGS_H */
Note: See TracBrowser for help on using the repository browser.