source: rtems/c/src/lib/libbsp/arm/shared/include/arm-pl011-regs.h @ a91dc98b

4.115
Last change on this file since a91dc98b was a91dc98b, checked in by Sebastian Huber <sebastian.huber@…>, on 04/26/13 at 13:06:32

bsp/realview-pbx-a9: New BSP
  • Property mode set to 100644
File size: 4.5 KB
Line 
1/*
2 * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
3 *
4 *  embedded brains GmbH
5 *  Dornierstr. 4
6 *  82178 Puchheim
7 *  Germany
8 *  <info@embedded-brains.de>
9 *
10 * The license and distribution terms for this file may be
11 * found in the file LICENSE in this distribution or at
12 * http://www.rtems.com/license/LICENSE.
13 */
14
15#ifndef LIBBSP_ARM_SHARED_ARM_PL011_REGS_H
16#define LIBBSP_ARM_SHARED_ARM_PL011_REGS_H
17
18#include <bsp/utility.h>
19
20typedef struct {
21  uint32_t uartdr;
22#define PL011_UARTDR_OE BSP_BIT32(11)
23#define PL011_UARTDR_BE BSP_BIT32(10)
24#define PL011_UARTDR_PE BSP_BIT32(9)
25#define PL011_UARTDR_FE BSP_BIT32(8)
26#define PL011_UARTDR_DATA(val) BSP_FLD32(val, 0, 7)
27#define PL011_UARTDR_DATA_GET(reg) BSP_FLD32GET(reg, 0, 7)
28#define PL011_UARTDR_DATA_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
29  uint32_t uartrsr_uartecr;
30#define PL011_UARTRSR_UARTECR_OE BSP_BIT32(3)
31#define PL011_UARTRSR_UARTECR_BE BSP_BIT32(2)
32#define PL011_UARTRSR_UARTECR_PE BSP_BIT32(1)
33#define PL011_UARTRSR_UARTECR_FE BSP_BIT32(0)
34  uint32_t reserved_08[4];
35  uint32_t uartfr;
36#define PL011_UARTFR_RI BSP_BIT32(8)
37#define PL011_UARTFR_TXFE BSP_BIT32(7)
38#define PL011_UARTFR_RXFF BSP_BIT32(6)
39#define PL011_UARTFR_TXFF BSP_BIT32(5)
40#define PL011_UARTFR_RXFE BSP_BIT32(4)
41#define PL011_UARTFR_BUSY BSP_BIT32(3)
42#define PL011_UARTFR_DCD BSP_BIT32(2)
43#define PL011_UARTFR_DSR BSP_BIT32(1)
44#define PL011_UARTFR_CTS BSP_BIT32(0)
45  uint32_t reserved_1c;
46  uint32_t uartilpr;
47#define PL011_UARTILPR_ILPDVSR(val) BSP_FLD32(val, 0, 7)
48#define PL011_UARTILPR_ILPDVSR_GET(reg) BSP_FLD32GET(reg, 0, 7)
49#define PL011_UARTILPR_ILPDVSR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7)
50  uint32_t uartibrd;
51#define PL011_UARTIBRD_BAUD_DIVINT(val) BSP_FLD32(val, 0, 15)
52#define PL011_UARTIBRD_BAUD_DIVINT_GET(reg) BSP_FLD32GET(reg, 0, 15)
53#define PL011_UARTIBRD_BAUD_DIVINT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15)
54  uint32_t uartfbrd;
55#define PL011_UARTFBRD_BAUD_DIVFRAC(val) BSP_FLD32(val, 0, 5)
56#define PL011_UARTFBRD_BAUD_DIVFRAC_GET(reg) BSP_FLD32GET(reg, 0, 5)
57#define PL011_UARTFBRD_BAUD_DIVFRAC_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5)
58  uint32_t uartlcr_h;
59#define PL011_UARTLCR_H_SPS BSP_BIT32(7)
60#define PL011_UARTLCR_H_WLEN(val) BSP_FLD32(val, 5, 6)
61#define PL011_UARTLCR_H_WLEN_GET(reg) BSP_FLD32GET(reg, 5, 6)
62#define PL011_UARTLCR_H_WLEN_SET(reg, val) BSP_FLD32SET(reg, val, 5, 6)
63#define PL011_UARTLCR_H_WLEN_5 0x00U
64#define PL011_UARTLCR_H_WLEN_6 0x01U
65#define PL011_UARTLCR_H_WLEN_7 0x02U
66#define PL011_UARTLCR_H_WLEN_8 0x03U
67#define PL011_UARTLCR_H_FEN BSP_BIT32(4)
68#define PL011_UARTLCR_H_STP2 BSP_BIT32(3)
69#define PL011_UARTLCR_H_EPS BSP_BIT32(2)
70#define PL011_UARTLCR_H_PEN BSP_BIT32(1)
71#define PL011_UARTLCR_H_BRK BSP_BIT32(0)
72  uint32_t uartcr;
73#define PL011_UARTCR_CTSEN BSP_BIT32(15)
74#define PL011_UARTCR_RTSEN BSP_BIT32(14)
75#define PL011_UARTCR_OUT2 BSP_BIT32(13)
76#define PL011_UARTCR_OUT1 BSP_BIT32(12)
77#define PL011_UARTCR_RTS BSP_BIT32(11)
78#define PL011_UARTCR_DTR BSP_BIT32(10)
79#define PL011_UARTCR_RXE BSP_BIT32(9)
80#define PL011_UARTCR_TXE BSP_BIT32(8)
81#define PL011_UARTCR_LBE BSP_BIT32(7)
82#define PL011_UARTCR_SIRLP BSP_BIT32(3)
83#define PL011_UARTCR_SIREN BSP_BIT32(2)
84#define PL011_UARTCR_UARTEN BSP_BIT32(1)
85  uint32_t uartifls;
86#define PL011_UARTIFLS_RXIFLSEL(val) BSP_FLD32(val, 3, 5)
87#define PL011_UARTIFLS_RXIFLSEL_GET(reg) BSP_FLD32GET(reg, 3, 5)
88#define PL011_UARTIFLS_RXIFLSEL_SET(reg, val) BSP_FLD32SET(reg, val, 3, 5)
89#define PL011_UARTIFLS_TXIFLSEL(val) BSP_FLD32(val, 0, 2)
90#define PL011_UARTIFLS_TXIFLSEL_GET(reg) BSP_FLD32GET(reg, 0, 2)
91#define PL011_UARTIFLS_TXIFLSEL_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2)
92  uint32_t uartimsc;
93  uint32_t uartris;
94  uint32_t uartmis;
95  uint32_t uarticr;
96#define PL011_UARTI_OEI BSP_BIT32(10)
97#define PL011_UARTI_BEI BSP_BIT32(9)
98#define PL011_UARTI_PEI BSP_BIT32(8)
99#define PL011_UARTI_FEI BSP_BIT32(7)
100#define PL011_UARTI_RTI BSP_BIT32(6)
101#define PL011_UARTI_TXI BSP_BIT32(5)
102#define PL011_UARTI_RXI BSP_BIT32(4)
103#define PL011_UARTI_DSRMI BSP_BIT32(3)
104#define PL011_UARTI_DCDMI BSP_BIT32(2)
105#define PL011_UARTI_CTSMI BSP_BIT32(1)
106#define PL011_UARTI_RIMI BSP_BIT32(0)
107  uint32_t uartdmacr;
108#define PL011_UARTDMACR_DMAONERR BSP_BIT32(2)
109#define PL011_UARTDMACR_TXDMAE BSP_BIT32(1)
110#define PL011_UARTDMACR_RXDMAE BSP_BIT32(0)
111  uint32_t reserved_4c[997];
112  uint32_t uartperiphid0;
113  uint32_t uartperiphid1;
114  uint32_t uartperiphid2;
115  uint32_t uartperiphid3;
116  uint32_t uartpcellid0;
117  uint32_t uartpcellid1;
118  uint32_t uartpcellid2;
119  uint32_t uartpcellid3;
120} pl011;
121
122#endif /* LIBBSP_ARM_SHARED_ARM_PL011_REGS_H */
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