1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup arm_shared |
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5 | * |
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6 | * @brief ARM PL011 Register definitions |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2013 embedded brains GmbH. All rights reserved. |
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11 | * |
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12 | * embedded brains GmbH |
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13 | * Dornierstr. 4 |
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14 | * 82178 Puchheim |
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15 | * Germany |
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16 | * <info@embedded-brains.de> |
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17 | * |
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18 | * The license and distribution terms for this file may be |
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19 | * found in the file LICENSE in this distribution or at |
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20 | * http://www.rtems.org/license/LICENSE. |
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21 | */ |
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22 | |
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23 | #ifndef LIBBSP_ARM_SHARED_ARM_PL011_REGS_H |
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24 | #define LIBBSP_ARM_SHARED_ARM_PL011_REGS_H |
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25 | |
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26 | #include <bsp/utility.h> |
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27 | |
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28 | typedef struct { |
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29 | uint32_t uartdr; |
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30 | #define PL011_UARTDR_OE BSP_BIT32(11) |
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31 | #define PL011_UARTDR_BE BSP_BIT32(10) |
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32 | #define PL011_UARTDR_PE BSP_BIT32(9) |
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33 | #define PL011_UARTDR_FE BSP_BIT32(8) |
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34 | #define PL011_UARTDR_DATA(val) BSP_FLD32(val, 0, 7) |
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35 | #define PL011_UARTDR_DATA_GET(reg) BSP_FLD32GET(reg, 0, 7) |
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36 | #define PL011_UARTDR_DATA_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) |
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37 | uint32_t uartrsr_uartecr; |
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38 | #define PL011_UARTRSR_UARTECR_OE BSP_BIT32(3) |
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39 | #define PL011_UARTRSR_UARTECR_BE BSP_BIT32(2) |
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40 | #define PL011_UARTRSR_UARTECR_PE BSP_BIT32(1) |
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41 | #define PL011_UARTRSR_UARTECR_FE BSP_BIT32(0) |
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42 | uint32_t reserved_08[4]; |
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43 | uint32_t uartfr; |
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44 | #define PL011_UARTFR_RI BSP_BIT32(8) |
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45 | #define PL011_UARTFR_TXFE BSP_BIT32(7) |
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46 | #define PL011_UARTFR_RXFF BSP_BIT32(6) |
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47 | #define PL011_UARTFR_TXFF BSP_BIT32(5) |
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48 | #define PL011_UARTFR_RXFE BSP_BIT32(4) |
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49 | #define PL011_UARTFR_BUSY BSP_BIT32(3) |
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50 | #define PL011_UARTFR_DCD BSP_BIT32(2) |
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51 | #define PL011_UARTFR_DSR BSP_BIT32(1) |
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52 | #define PL011_UARTFR_CTS BSP_BIT32(0) |
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53 | uint32_t reserved_1c; |
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54 | uint32_t uartilpr; |
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55 | #define PL011_UARTILPR_ILPDVSR(val) BSP_FLD32(val, 0, 7) |
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56 | #define PL011_UARTILPR_ILPDVSR_GET(reg) BSP_FLD32GET(reg, 0, 7) |
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57 | #define PL011_UARTILPR_ILPDVSR_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) |
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58 | uint32_t uartibrd; |
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59 | #define PL011_UARTIBRD_BAUD_DIVINT(val) BSP_FLD32(val, 0, 15) |
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60 | #define PL011_UARTIBRD_BAUD_DIVINT_GET(reg) BSP_FLD32GET(reg, 0, 15) |
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61 | #define PL011_UARTIBRD_BAUD_DIVINT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 15) |
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62 | uint32_t uartfbrd; |
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63 | #define PL011_UARTFBRD_BAUD_DIVFRAC(val) BSP_FLD32(val, 0, 5) |
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64 | #define PL011_UARTFBRD_BAUD_DIVFRAC_GET(reg) BSP_FLD32GET(reg, 0, 5) |
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65 | #define PL011_UARTFBRD_BAUD_DIVFRAC_SET(reg, val) BSP_FLD32SET(reg, val, 0, 5) |
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66 | uint32_t uartlcr_h; |
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67 | #define PL011_UARTLCR_H_SPS BSP_BIT32(7) |
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68 | #define PL011_UARTLCR_H_WLEN(val) BSP_FLD32(val, 5, 6) |
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69 | #define PL011_UARTLCR_H_WLEN_GET(reg) BSP_FLD32GET(reg, 5, 6) |
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70 | #define PL011_UARTLCR_H_WLEN_SET(reg, val) BSP_FLD32SET(reg, val, 5, 6) |
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71 | #define PL011_UARTLCR_H_WLEN_5 0x00U |
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72 | #define PL011_UARTLCR_H_WLEN_6 0x01U |
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73 | #define PL011_UARTLCR_H_WLEN_7 0x02U |
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74 | #define PL011_UARTLCR_H_WLEN_8 0x03U |
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75 | #define PL011_UARTLCR_H_FEN BSP_BIT32(4) |
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76 | #define PL011_UARTLCR_H_STP2 BSP_BIT32(3) |
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77 | #define PL011_UARTLCR_H_EPS BSP_BIT32(2) |
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78 | #define PL011_UARTLCR_H_PEN BSP_BIT32(1) |
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79 | #define PL011_UARTLCR_H_BRK BSP_BIT32(0) |
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80 | uint32_t uartcr; |
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81 | #define PL011_UARTCR_CTSEN BSP_BIT32(15) |
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82 | #define PL011_UARTCR_RTSEN BSP_BIT32(14) |
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83 | #define PL011_UARTCR_OUT2 BSP_BIT32(13) |
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84 | #define PL011_UARTCR_OUT1 BSP_BIT32(12) |
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85 | #define PL011_UARTCR_RTS BSP_BIT32(11) |
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86 | #define PL011_UARTCR_DTR BSP_BIT32(10) |
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87 | #define PL011_UARTCR_RXE BSP_BIT32(9) |
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88 | #define PL011_UARTCR_TXE BSP_BIT32(8) |
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89 | #define PL011_UARTCR_LBE BSP_BIT32(7) |
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90 | #define PL011_UARTCR_SIRLP BSP_BIT32(3) |
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91 | #define PL011_UARTCR_SIREN BSP_BIT32(2) |
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92 | #define PL011_UARTCR_UARTEN BSP_BIT32(1) |
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93 | uint32_t uartifls; |
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94 | #define PL011_UARTIFLS_RXIFLSEL(val) BSP_FLD32(val, 3, 5) |
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95 | #define PL011_UARTIFLS_RXIFLSEL_GET(reg) BSP_FLD32GET(reg, 3, 5) |
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96 | #define PL011_UARTIFLS_RXIFLSEL_SET(reg, val) BSP_FLD32SET(reg, val, 3, 5) |
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97 | #define PL011_UARTIFLS_TXIFLSEL(val) BSP_FLD32(val, 0, 2) |
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98 | #define PL011_UARTIFLS_TXIFLSEL_GET(reg) BSP_FLD32GET(reg, 0, 2) |
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99 | #define PL011_UARTIFLS_TXIFLSEL_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2) |
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100 | uint32_t uartimsc; |
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101 | uint32_t uartris; |
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102 | uint32_t uartmis; |
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103 | uint32_t uarticr; |
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104 | #define PL011_UARTI_OEI BSP_BIT32(10) |
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105 | #define PL011_UARTI_BEI BSP_BIT32(9) |
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106 | #define PL011_UARTI_PEI BSP_BIT32(8) |
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107 | #define PL011_UARTI_FEI BSP_BIT32(7) |
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108 | #define PL011_UARTI_RTI BSP_BIT32(6) |
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109 | #define PL011_UARTI_TXI BSP_BIT32(5) |
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110 | #define PL011_UARTI_RXI BSP_BIT32(4) |
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111 | #define PL011_UARTI_DSRMI BSP_BIT32(3) |
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112 | #define PL011_UARTI_DCDMI BSP_BIT32(2) |
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113 | #define PL011_UARTI_CTSMI BSP_BIT32(1) |
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114 | #define PL011_UARTI_RIMI BSP_BIT32(0) |
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115 | uint32_t uartdmacr; |
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116 | #define PL011_UARTDMACR_DMAONERR BSP_BIT32(2) |
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117 | #define PL011_UARTDMACR_TXDMAE BSP_BIT32(1) |
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118 | #define PL011_UARTDMACR_RXDMAE BSP_BIT32(0) |
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119 | uint32_t reserved_4c[997]; |
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120 | uint32_t uartperiphid0; |
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121 | uint32_t uartperiphid1; |
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122 | uint32_t uartperiphid2; |
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123 | uint32_t uartperiphid3; |
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124 | uint32_t uartpcellid0; |
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125 | uint32_t uartpcellid1; |
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126 | uint32_t uartpcellid2; |
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127 | uint32_t uartpcellid3; |
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128 | } pl011; |
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129 | |
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130 | #endif /* LIBBSP_ARM_SHARED_ARM_PL011_REGS_H */ |
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