1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup arm_gic |
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5 | * |
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6 | * @brief ARM GIC Support |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2013 embedded brains GmbH. All rights reserved. |
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11 | * |
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12 | * embedded brains GmbH |
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13 | * Dornierstr. 4 |
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14 | * 82178 Puchheim |
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15 | * Germany |
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16 | * <info@embedded-brains.de> |
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17 | * |
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18 | * The license and distribution terms for this file may be |
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19 | * found in the file LICENSE in this distribution or at |
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20 | * http://www.rtems.org/license/LICENSE. |
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21 | */ |
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22 | |
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23 | #ifndef LIBBSP_ARM_SHARED_ARM_GIC_H |
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24 | #define LIBBSP_ARM_SHARED_ARM_GIC_H |
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25 | |
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26 | #include <bsp/arm-gic-regs.h> |
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27 | |
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28 | #include <stdbool.h> |
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29 | |
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30 | #ifdef __cplusplus |
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31 | extern "C" { |
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32 | #endif /* __cplusplus */ |
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33 | |
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34 | /** |
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35 | * @defgroup arm_gic ARM GIC |
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36 | * |
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37 | * @ingroup arm_shared |
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38 | * |
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39 | * @brief ARM_GIC Support Package |
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40 | */ |
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41 | |
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42 | #define GIC_ID_TO_ONE_BIT_REG_INDEX(id) ((id) >> 5) |
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43 | #define GIC_ID_TO_ONE_BIT_REG_BIT(id) (1U << ((id) & 0x1fU)) |
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44 | |
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45 | #define GIC_ID_TO_TWO_BITS_REG_INDEX(id) ((id) >> 4) |
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46 | #define GIC_ID_TO_TWO_BITS_REG_OFFSET(id) ((id) & 0xfU) |
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47 | |
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48 | static inline bool gic_id_is_enabled(volatile gic_dist *dist, uint32_t id) |
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49 | { |
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50 | uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id); |
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51 | uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id); |
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52 | |
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53 | return (dist->icdiser[i] & bit) != 0; |
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54 | } |
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55 | |
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56 | static inline void gic_id_enable(volatile gic_dist *dist, uint32_t id) |
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57 | { |
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58 | uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id); |
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59 | uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id); |
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60 | |
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61 | dist->icdiser[i] = bit; |
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62 | } |
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63 | |
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64 | static inline void gic_id_disable(volatile gic_dist *dist, uint32_t id) |
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65 | { |
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66 | uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id); |
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67 | uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id); |
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68 | |
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69 | dist->icdicer[i] = bit; |
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70 | } |
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71 | |
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72 | static inline bool gic_id_is_pending(volatile gic_dist *dist, uint32_t id) |
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73 | { |
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74 | uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id); |
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75 | uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id); |
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76 | |
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77 | return (dist->icdispr[i] & bit) != 0; |
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78 | } |
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79 | |
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80 | static inline void gic_id_set_pending(volatile gic_dist *dist, uint32_t id) |
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81 | { |
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82 | uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id); |
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83 | uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id); |
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84 | |
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85 | dist->icdispr[i] = bit; |
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86 | } |
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87 | |
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88 | static inline void gic_id_clear_pending(volatile gic_dist *dist, uint32_t id) |
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89 | { |
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90 | uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id); |
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91 | uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id); |
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92 | |
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93 | dist->icdicpr[i] = bit; |
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94 | } |
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95 | |
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96 | static inline bool gic_id_is_active(volatile gic_dist *dist, uint32_t id) |
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97 | { |
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98 | uint32_t i = GIC_ID_TO_ONE_BIT_REG_INDEX(id); |
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99 | uint32_t bit = GIC_ID_TO_ONE_BIT_REG_BIT(id); |
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100 | |
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101 | return (dist->icdabr[i] & bit) != 0; |
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102 | } |
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103 | |
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104 | static inline void gic_id_set_priority( |
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105 | volatile gic_dist *dist, |
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106 | uint32_t id, |
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107 | uint8_t priority |
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108 | ) |
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109 | { |
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110 | dist->icdipr[id] = priority; |
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111 | } |
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112 | |
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113 | static inline uint8_t gic_id_get_priority(volatile gic_dist *dist, uint32_t id) |
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114 | { |
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115 | return dist->icdipr[id]; |
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116 | } |
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117 | |
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118 | static inline void gic_id_set_targets( |
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119 | volatile gic_dist *dist, |
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120 | uint32_t id, |
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121 | uint8_t targets |
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122 | ) |
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123 | { |
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124 | dist->icdiptr[id] = targets; |
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125 | } |
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126 | |
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127 | static inline uint8_t gic_id_get_targets(volatile gic_dist *dist, uint32_t id) |
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128 | { |
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129 | return dist->icdiptr[id]; |
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130 | } |
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131 | |
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132 | typedef enum { |
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133 | GIC_LEVEL_SENSITIVE, |
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134 | GIC_EDGE_TRIGGERED |
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135 | } gic_trigger_mode; |
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136 | |
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137 | static inline gic_trigger_mode gic_id_get_trigger_mode( |
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138 | volatile gic_dist *dist, |
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139 | uint32_t id |
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140 | ) |
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141 | { |
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142 | uint32_t i = GIC_ID_TO_TWO_BITS_REG_INDEX(id); |
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143 | uint32_t o = GIC_ID_TO_TWO_BITS_REG_OFFSET(id) + 1; |
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144 | uint32_t bit = 1U << o; |
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145 | |
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146 | return (dist->icdicfr[i] & bit) != 0 ? |
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147 | GIC_EDGE_TRIGGERED : GIC_LEVEL_SENSITIVE; |
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148 | } |
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149 | |
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150 | static inline void gic_id_set_trigger_mode( |
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151 | volatile gic_dist *dist, |
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152 | uint32_t id, |
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153 | gic_trigger_mode mode |
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154 | ) |
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155 | { |
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156 | uint32_t i = GIC_ID_TO_TWO_BITS_REG_INDEX(id); |
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157 | uint32_t o = GIC_ID_TO_TWO_BITS_REG_OFFSET(id) + 1; |
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158 | uint32_t bit = mode << o; |
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159 | uint32_t mask = 1U << o; |
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160 | uint32_t icdicfr = dist->icdicfr[i]; |
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161 | |
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162 | icdicfr &= ~mask; |
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163 | icdicfr |= bit; |
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164 | |
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165 | dist->icdicfr[i] = icdicfr; |
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166 | } |
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167 | |
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168 | typedef enum { |
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169 | GIC_N_TO_N, |
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170 | GIC_1_TO_N |
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171 | } gic_handling_model; |
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172 | |
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173 | static inline gic_handling_model gic_id_get_handling_model( |
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174 | volatile gic_dist *dist, |
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175 | uint32_t id |
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176 | ) |
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177 | { |
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178 | uint32_t i = GIC_ID_TO_TWO_BITS_REG_INDEX(id); |
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179 | uint32_t o = GIC_ID_TO_TWO_BITS_REG_OFFSET(id); |
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180 | uint32_t bit = 1U << o; |
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181 | |
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182 | return (dist->icdicfr[i] & bit) != 0 ? GIC_1_TO_N : GIC_N_TO_N; |
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183 | } |
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184 | |
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185 | static inline void gic_id_set_handling_model( |
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186 | volatile gic_dist *dist, |
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187 | uint32_t id, |
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188 | gic_handling_model model |
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189 | ) |
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190 | { |
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191 | uint32_t i = GIC_ID_TO_TWO_BITS_REG_INDEX(id); |
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192 | uint32_t o = GIC_ID_TO_TWO_BITS_REG_OFFSET(id); |
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193 | uint32_t bit = model << o; |
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194 | uint32_t mask = 1U << o; |
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195 | uint32_t icdicfr = dist->icdicfr[i]; |
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196 | |
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197 | icdicfr &= ~mask; |
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198 | icdicfr |= bit; |
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199 | |
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200 | dist->icdicfr[i] = icdicfr; |
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201 | } |
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202 | |
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203 | #ifdef __cplusplus |
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204 | } |
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205 | #endif /* __cplusplus */ |
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206 | |
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207 | #endif /* LIBBSP_ARM_SHARED_ARM_GIC_H */ |
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