[a91dc98b] | 1 | /* |
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| 2 | * Copyright (c) 2013 embedded brains GmbH. All rights reserved. |
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| 3 | * |
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| 4 | * embedded brains GmbH |
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| 5 | * Dornierstr. 4 |
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| 6 | * 82178 Puchheim |
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| 7 | * Germany |
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| 8 | * <info@embedded-brains.de> |
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| 9 | * |
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| 10 | * The license and distribution terms for this file may be |
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| 11 | * found in the file LICENSE in this distribution or at |
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| 12 | * http://www.rtems.com/license/LICENSE. |
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| 13 | */ |
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| 14 | |
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| 15 | #ifndef LIBBSP_ARM_SHARED_ARM_GIC_REGS_H |
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| 16 | #define LIBBSP_ARM_SHARED_ARM_GIC_REGS_H |
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| 17 | |
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| 18 | #include <bsp/utility.h> |
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| 19 | |
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| 20 | typedef struct { |
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| 21 | uint32_t iccicr; |
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| 22 | #define GIC_CPUIF_ICCICR_ENABLE BSP_BIT32(0) |
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| 23 | uint32_t iccpmr; |
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| 24 | #define GIC_CPUIF_ICCPMR_PRIORITY(val) BSP_FLD32(val, 0, 7) |
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| 25 | #define GIC_CPUIF_ICCPMR_PRIORITY_GET(reg) BSP_FLD32GET(reg, 0, 7) |
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| 26 | #define GIC_CPUIF_ICCPMR_PRIORITY_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) |
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| 27 | uint32_t iccbpr; |
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| 28 | #define GIC_CPUIF_ICCBPR_BINARY_POINT(val) BSP_FLD32(val, 0, 2) |
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| 29 | #define GIC_CPUIF_ICCBPR_BINARY_POINT_GET(reg) BSP_FLD32GET(reg, 0, 2) |
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| 30 | #define GIC_CPUIF_ICCBPR_BINARY_POINT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2) |
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| 31 | uint32_t icciar; |
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| 32 | #define GIC_CPUIF_ICCIAR_CPUID(val) BSP_FLD32(val, 10, 12) |
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| 33 | #define GIC_CPUIF_ICCIAR_CPUID_GET(reg) BSP_FLD32GET(reg, 10, 12) |
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| 34 | #define GIC_CPUIF_ICCIAR_CPUID_SET(reg, val) BSP_FLD32SET(reg, val, 10, 12) |
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| 35 | #define GIC_CPUIF_ICCIAR_ACKINTID(val) BSP_FLD32(val, 0, 9) |
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| 36 | #define GIC_CPUIF_ICCIAR_ACKINTID_GET(reg) BSP_FLD32GET(reg, 0, 9) |
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| 37 | #define GIC_CPUIF_ICCIAR_ACKINTID_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9) |
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| 38 | uint32_t icceoir; |
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| 39 | #define GIC_CPUIF_ICCEOIR_CPUID(val) BSP_FLD32(val, 10, 12) |
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| 40 | #define GIC_CPUIF_ICCEOIR_CPUID_GET(reg) BSP_FLD32GET(reg, 10, 12) |
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| 41 | #define GIC_CPUIF_ICCEOIR_CPUID_SET(reg, val) BSP_FLD32SET(reg, val, 10, 12) |
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| 42 | #define GIC_CPUIF_ICCEOIR_EOIINTID(val) BSP_FLD32(val, 0, 9) |
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| 43 | #define GIC_CPUIF_ICCEOIR_EOIINTID_GET(reg) BSP_FLD32GET(reg, 0, 9) |
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| 44 | #define GIC_CPUIF_ICCEOIR_EOIINTID_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9) |
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| 45 | uint32_t iccrpr; |
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| 46 | #define GIC_CPUIF_ICCRPR_PRIORITY(val) BSP_FLD32(val, 0, 7) |
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| 47 | #define GIC_CPUIF_ICCRPR_PRIORITY_GET(reg) BSP_FLD32GET(reg, 0, 7) |
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| 48 | #define GIC_CPUIF_ICCRPR_PRIORITY_SET(reg, val) BSP_FLD32SET(reg, val, 0, 7) |
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| 49 | uint32_t icchpir; |
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| 50 | #define GIC_CPUIF_ICCHPIR_CPUID(val) BSP_FLD32(val, 10, 12) |
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| 51 | #define GIC_CPUIF_ICCHPIR_CPUID_GET(reg) BSP_FLD32GET(reg, 10, 12) |
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| 52 | #define GIC_CPUIF_ICCHPIR_CPUID_SET(reg, val) BSP_FLD32SET(reg, val, 10, 12) |
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| 53 | #define GIC_CPUIF_ICCHPIR_PENDINTID(val) BSP_FLD32(val, 0, 9) |
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| 54 | #define GIC_CPUIF_ICCHPIR_PENDINTID_GET(reg) BSP_FLD32GET(reg, 0, 9) |
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| 55 | #define GIC_CPUIF_ICCHPIR_PENDINTID_SET(reg, val) BSP_FLD32SET(reg, val, 0, 9) |
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| 56 | uint32_t iccabpr; |
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| 57 | #define GIC_CPUIF_ICCABPR_BINARY_POINT(val) BSP_FLD32(val, 0, 2) |
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| 58 | #define GIC_CPUIF_ICCABPR_BINARY_POINT_GET(reg) BSP_FLD32GET(reg, 0, 2) |
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| 59 | #define GIC_CPUIF_ICCABPR_BINARY_POINT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 2) |
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| 60 | uint32_t reserved_20[55]; |
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| 61 | uint32_t icciidr; |
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| 62 | #define GIC_CPUIF_ICCIIDR_PRODUCT_ID(val) BSP_FLD32(val, 24, 31) |
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| 63 | #define GIC_CPUIF_ICCIIDR_PRODUCT_ID_GET(reg) BSP_FLD32GET(reg, 24, 31) |
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| 64 | #define GIC_CPUIF_ICCIIDR_PRODUCT_ID_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31) |
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| 65 | #define GIC_CPUIF_ICCIIDR_ARCH_VERSION(val) BSP_FLD32(val, 16, 19) |
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| 66 | #define GIC_CPUIF_ICCIIDR_ARCH_VERSION_GET(reg) BSP_FLD32GET(reg, 16, 19) |
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| 67 | #define GIC_CPUIF_ICCIIDR_ARCH_VERSION_SET(reg, val) BSP_FLD32SET(reg, val, 16, 19) |
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| 68 | #define GIC_CPUIF_ICCIIDR_REVISION(val) BSP_FLD32(val, 12, 15) |
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| 69 | #define GIC_CPUIF_ICCIIDR_REVISION_GET(reg) BSP_FLD32GET(reg, 12, 15) |
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| 70 | #define GIC_CPUIF_ICCIIDR_REVISION_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15) |
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| 71 | #define GIC_CPUIF_ICCIIDR_IMPLEMENTER(val) BSP_FLD32(val, 0, 11) |
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| 72 | #define GIC_CPUIF_ICCIIDR_IMPLEMENTER_GET(reg) BSP_FLD32GET(reg, 0, 11) |
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| 73 | #define GIC_CPUIF_ICCIIDR_IMPLEMENTER_SET(reg, val) BSP_FLD32SET(reg, val, 0, 11) |
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| 74 | } gic_cpuif; |
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| 75 | |
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| 76 | typedef struct { |
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| 77 | uint32_t icddcr; |
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| 78 | #define GIC_DIST_ICDDCR_ENABLE BSP_BIT32(0) |
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| 79 | uint32_t icdictr; |
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| 80 | #define GIC_DIST_ICDICTR_LSPI(val) BSP_FLD32(val, 11, 15) |
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| 81 | #define GIC_DIST_ICDICTR_LSPI_GET(reg) BSP_FLD32GET(reg, 11, 15) |
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| 82 | #define GIC_DIST_ICDICTR_LSPI_SET(reg, val) BSP_FLD32SET(reg, val, 11, 15) |
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| 83 | #define GIC_DIST_ICDICTR_SECURITY_EXTN BSP_BIT32(10) |
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| 84 | #define GIC_DIST_ICDICTR_CPU_NUMBER(val) BSP_FLD32(val, 5, 7) |
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| 85 | #define GIC_DIST_ICDICTR_CPU_NUMBER_GET(reg) BSP_FLD32GET(reg, 5, 7) |
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| 86 | #define GIC_DIST_ICDICTR_CPU_NUMBER_SET(reg, val) BSP_FLD32SET(reg, val, 5, 7) |
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| 87 | #define GIC_DIST_ICDICTR_IT_LINES_NUMBER(val) BSP_FLD32(val, 0, 4) |
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| 88 | #define GIC_DIST_ICDICTR_IT_LINES_NUMBER_GET(reg) BSP_FLD32GET(reg, 0, 4) |
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| 89 | #define GIC_DIST_ICDICTR_IT_LINES_NUMBER_SET(reg, val) BSP_FLD32SET(reg, val, 0, 4) |
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| 90 | uint32_t icdiidr; |
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| 91 | #define GIC_DIST_ICDIIDR_PRODUCT_ID(val) BSP_FLD32(val, 24, 31) |
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| 92 | #define GIC_DIST_ICDIIDR_PRODUCT_ID_GET(reg) BSP_FLD32GET(reg, 24, 31) |
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| 93 | #define GIC_DIST_ICDIIDR_PRODUCT_ID_SET(reg, val) BSP_FLD32SET(reg, val, 24, 31) |
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| 94 | #define GIC_DIST_ICDIIDR_VARIANT(val) BSP_FLD32(val, 16, 19) |
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| 95 | #define GIC_DIST_ICDIIDR_VARIANT_GET(reg) BSP_FLD32GET(reg, 16, 19) |
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| 96 | #define GIC_DIST_ICDIIDR_VARIANT_SET(reg, val) BSP_FLD32SET(reg, val, 16, 19) |
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| 97 | #define GIC_DIST_ICDIIDR_REVISION(val) BSP_FLD32(val, 12, 15) |
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| 98 | #define GIC_DIST_ICDIIDR_REVISION_GET(reg) BSP_FLD32GET(reg, 12, 15) |
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| 99 | #define GIC_DIST_ICDIIDR_REVISION_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15) |
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| 100 | #define GIC_DIST_ICDIIDR_IMPLEMENTER(val) BSP_FLD32(val, 0, 11) |
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| 101 | #define GIC_DIST_ICDIIDR_IMPLEMENTER_GET(reg) BSP_FLD32GET(reg, 0, 11) |
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| 102 | #define GIC_DIST_ICDIIDR_IMPLEMENTER_SET(reg, val) BSP_FLD32SET(reg, val, 0, 11) |
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| 103 | uint32_t reserved_0c[29]; |
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| 104 | uint32_t icdisr[32]; |
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| 105 | uint32_t icdiser[32]; |
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| 106 | uint32_t icdicer[32]; |
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| 107 | uint32_t icdispr[32]; |
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| 108 | uint32_t icdicpr[32]; |
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| 109 | uint32_t icdabr[32]; |
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| 110 | uint32_t reserved_380[32]; |
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| 111 | uint8_t icdipr[256]; |
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| 112 | uint32_t reserved_500[192]; |
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| 113 | uint8_t icdiptr[256]; |
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| 114 | uint32_t reserved_900[192]; |
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| 115 | uint32_t icdicfr[64]; |
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| 116 | uint32_t reserved_d00[128]; |
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| 117 | uint32_t icdsgir; |
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| 118 | #define GIC_DIST_ICDSGIR_TARGET_LIST_FILTER(val) BSP_FLD32(val, 24, 25) |
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| 119 | #define GIC_DIST_ICDSGIR_TARGET_LIST_FILTER_GET(reg) BSP_FLD32GET(reg, 24, 25) |
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| 120 | #define GIC_DIST_ICDSGIR_TARGET_LIST_FILTER_SET(reg, val) BSP_FLD32SET(reg, val, 24, 25) |
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| 121 | #define GIC_DIST_ICDSGIR_CPU_TARGET_LIST(val) BSP_FLD32(val, 16, 23) |
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| 122 | #define GIC_DIST_ICDSGIR_CPU_TARGET_LIST_GET(reg) BSP_FLD32GET(reg, 16, 23) |
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| 123 | #define GIC_DIST_ICDSGIR_CPU_TARGET_LIST_SET(reg, val) BSP_FLD32SET(reg, val, 16, 23) |
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| 124 | #define GIC_DIST_ICDSGIR_SATT BSP_BIT32(15) |
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| 125 | #define GIC_DIST_ICDSGIR_SGIINTID(val) BSP_FLD32(val, 0, 3) |
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| 126 | #define GIC_DIST_ICDSGIR_SGIINTID_GET(reg) BSP_FLD32GET(reg, 0, 3) |
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| 127 | #define GIC_DIST_ICDSGIR_SGIINTID_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) |
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| 128 | } gic_dist; |
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| 129 | |
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| 130 | #endif /* LIBBSP_ARM_SHARED_ARM_GIC_REGS_H */ |
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