source: rtems/c/src/lib/libbsp/arm/shared/include/arm-gic-irq.h @ e19da87

5
Last change on this file since e19da87 was e19da87, checked in by Sebastian Huber <sebastian.huber@…>, on Jul 12, 2017 at 8:55:59 AM

bsps: Include missing header file

Update #3071.

  • Property mode set to 100644
File size: 2.5 KB
Line 
1/**
2 *  @file
3 *
4 *  @ingroup arm_gic
5 *
6 *  @brief ARM GIC IRQ
7 */
8
9/*
10 * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
11 *
12 *  embedded brains GmbH
13 *  Dornierstr. 4
14 *  82178 Puchheim
15 *  Germany
16 *  <info@embedded-brains.de>
17 *
18 * The license and distribution terms for this file may be
19 * found in the file LICENSE in this distribution or at
20 * http://www.rtems.org/license/LICENSE.
21 */
22
23#ifndef LIBBSP_ARM_SHARED_ARM_GIC_IRQ_H
24#define LIBBSP_ARM_SHARED_ARM_GIC_IRQ_H
25
26#include <bsp.h>
27#include <bsp/arm-gic.h>
28#include <rtems/score/processormask.h>
29
30#ifdef __cplusplus
31extern "C" {
32#endif /* __cplusplus */
33
34#define ARM_GIC_IRQ_SGI_0 0
35#define ARM_GIC_IRQ_SGI_1 1
36#define ARM_GIC_IRQ_SGI_2 2
37#define ARM_GIC_IRQ_SGI_3 3
38#define ARM_GIC_IRQ_SGI_5 5
39#define ARM_GIC_IRQ_SGI_6 6
40#define ARM_GIC_IRQ_SGI_7 7
41#define ARM_GIC_IRQ_SGI_8 8
42#define ARM_GIC_IRQ_SGI_9 9
43#define ARM_GIC_IRQ_SGI_10 10
44#define ARM_GIC_IRQ_SGI_11 11
45#define ARM_GIC_IRQ_SGI_12 12
46#define ARM_GIC_IRQ_SGI_13 13
47#define ARM_GIC_IRQ_SGI_14 14
48#define ARM_GIC_IRQ_SGI_15 15
49
50#define ARM_GIC_DIST ((volatile gic_dist *) BSP_ARM_GIC_DIST_BASE)
51
52rtems_status_code arm_gic_irq_set_priority(
53  rtems_vector_number vector,
54  uint8_t priority
55);
56
57rtems_status_code arm_gic_irq_get_priority(
58  rtems_vector_number vector,
59  uint8_t *priority
60);
61
62void bsp_interrupt_set_affinity(
63  rtems_vector_number vector,
64  const Processor_mask *affinity
65);
66
67void bsp_interrupt_get_affinity(
68  rtems_vector_number vector,
69  Processor_mask *affinity
70);
71
72typedef enum {
73  ARM_GIC_IRQ_SOFTWARE_IRQ_TO_ALL_IN_LIST,
74  ARM_GIC_IRQ_SOFTWARE_IRQ_TO_ALL_EXCEPT_SELF,
75  ARM_GIC_IRQ_SOFTWARE_IRQ_TO_SELF
76} arm_gic_irq_software_irq_target_filter;
77
78static inline rtems_status_code arm_gic_irq_generate_software_irq(
79  rtems_vector_number vector,
80  arm_gic_irq_software_irq_target_filter filter,
81  uint8_t targets
82)
83{
84  rtems_status_code sc = RTEMS_SUCCESSFUL;
85
86  if (vector <= ARM_GIC_IRQ_SGI_15) {
87    volatile gic_dist *dist = ARM_GIC_DIST;
88
89    dist->icdsgir = GIC_DIST_ICDSGIR_TARGET_LIST_FILTER(filter)
90      | GIC_DIST_ICDSGIR_CPU_TARGET_LIST(targets)
91      | GIC_DIST_ICDSGIR_SGIINTID(vector);
92  } else {
93    sc = RTEMS_INVALID_ID;
94  }
95
96  return sc;
97}
98
99static inline uint32_t arm_gic_irq_processor_count(void)
100{
101  volatile gic_dist *dist = ARM_GIC_DIST;
102
103  return GIC_DIST_ICDICTR_CPU_NUMBER_GET(dist->icdictr) + 1;
104}
105
106void arm_gic_irq_initialize_secondary_cpu(void);
107
108#ifdef __cplusplus
109}
110#endif /* __cplusplus */
111
112#endif /* LIBBSP_ARM_SHARED_ARM_GIC_IRQ_H */
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