1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup arm_gic |
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5 | * |
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6 | * @brief ARM GIC IRQ |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2013 embedded brains GmbH. All rights reserved. |
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11 | * |
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12 | * embedded brains GmbH |
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13 | * Dornierstr. 4 |
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14 | * 82178 Puchheim |
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15 | * Germany |
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16 | * <info@embedded-brains.de> |
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17 | * |
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18 | * The license and distribution terms for this file may be |
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19 | * found in the file LICENSE in this distribution or at |
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20 | * http://www.rtems.com/license/LICENSE. |
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21 | */ |
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22 | |
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23 | #ifndef LIBBSP_ARM_SHARED_ARM_GIC_IRQ_H |
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24 | #define LIBBSP_ARM_SHARED_ARM_GIC_IRQ_H |
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25 | |
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26 | #include <bsp.h> |
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27 | #include <bsp/arm-gic.h> |
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28 | |
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29 | #ifdef __cplusplus |
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30 | extern "C" { |
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31 | #endif /* __cplusplus */ |
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32 | |
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33 | #define ARM_GIC_IRQ_SGI_0 0 |
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34 | #define ARM_GIC_IRQ_SGI_1 1 |
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35 | #define ARM_GIC_IRQ_SGI_2 2 |
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36 | #define ARM_GIC_IRQ_SGI_3 3 |
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37 | #define ARM_GIC_IRQ_SGI_5 5 |
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38 | #define ARM_GIC_IRQ_SGI_6 6 |
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39 | #define ARM_GIC_IRQ_SGI_7 7 |
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40 | #define ARM_GIC_IRQ_SGI_8 8 |
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41 | #define ARM_GIC_IRQ_SGI_9 9 |
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42 | #define ARM_GIC_IRQ_SGI_10 10 |
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43 | #define ARM_GIC_IRQ_SGI_11 11 |
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44 | #define ARM_GIC_IRQ_SGI_12 12 |
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45 | #define ARM_GIC_IRQ_SGI_13 13 |
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46 | #define ARM_GIC_IRQ_SGI_14 14 |
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47 | #define ARM_GIC_IRQ_SGI_15 15 |
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48 | |
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49 | #define ARM_GIC_DIST ((volatile gic_dist *) BSP_ARM_GIC_DIST_BASE) |
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50 | |
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51 | rtems_status_code arm_gic_irq_set_priority( |
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52 | rtems_vector_number vector, |
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53 | uint8_t priority |
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54 | ); |
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55 | |
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56 | rtems_status_code arm_gic_irq_get_priority( |
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57 | rtems_vector_number vector, |
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58 | uint8_t *priority |
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59 | ); |
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60 | |
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61 | typedef enum { |
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62 | ARM_GIC_IRQ_SOFTWARE_IRQ_TO_ALL_IN_LIST, |
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63 | ARM_GIC_IRQ_SOFTWARE_IRQ_TO_ALL_EXCEPT_SELF, |
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64 | ARM_GIC_IRQ_SOFTWARE_IRQ_TO_SELF |
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65 | } arm_gic_irq_software_irq_target_filter; |
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66 | |
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67 | static inline rtems_status_code arm_gic_irq_generate_software_irq( |
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68 | rtems_vector_number vector, |
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69 | arm_gic_irq_software_irq_target_filter filter, |
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70 | uint8_t targets |
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71 | ) |
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72 | { |
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73 | rtems_status_code sc = RTEMS_SUCCESSFUL; |
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74 | |
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75 | if (vector <= ARM_GIC_IRQ_SGI_15) { |
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76 | volatile gic_dist *dist = ARM_GIC_DIST; |
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77 | |
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78 | dist->icdsgir = GIC_DIST_ICDSGIR_TARGET_LIST_FILTER(filter) |
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79 | | GIC_DIST_ICDSGIR_CPU_TARGET_LIST(targets) |
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80 | | GIC_DIST_ICDSGIR_SGIINTID(vector); |
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81 | } else { |
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82 | sc = RTEMS_INVALID_ID; |
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83 | } |
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84 | |
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85 | return sc; |
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86 | } |
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87 | |
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88 | static inline uint32_t arm_gic_irq_processor_count(void) |
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89 | { |
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90 | volatile gic_dist *dist = ARM_GIC_DIST; |
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91 | |
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92 | return GIC_DIST_ICDICTR_CPU_NUMBER_GET(dist->icdictr) + 1; |
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93 | } |
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94 | |
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95 | void arm_gic_irq_initialize_secondary_cpu(void); |
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96 | |
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97 | #ifdef __cplusplus |
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98 | } |
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99 | #endif /* __cplusplus */ |
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100 | |
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101 | #endif /* LIBBSP_ARM_SHARED_ARM_GIC_IRQ_H */ |
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