source: rtems/c/src/lib/libbsp/arm/shared/include/arm-gic-irq.h @ af207fa9

5
Last change on this file since af207fa9 was af207fa9, checked in by Sebastian Huber <sebastian.huber@…>, on Jul 11, 2017 at 9:54:30 AM

Add interrupt vector set/get affinity

Close #3071.

  • Property mode set to 100644
File size: 2.4 KB
Line 
1/**
2 *  @file
3 *
4 *  @ingroup arm_gic
5 *
6 *  @brief ARM GIC IRQ
7 */
8
9/*
10 * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
11 *
12 *  embedded brains GmbH
13 *  Dornierstr. 4
14 *  82178 Puchheim
15 *  Germany
16 *  <info@embedded-brains.de>
17 *
18 * The license and distribution terms for this file may be
19 * found in the file LICENSE in this distribution or at
20 * http://www.rtems.org/license/LICENSE.
21 */
22
23#ifndef LIBBSP_ARM_SHARED_ARM_GIC_IRQ_H
24#define LIBBSP_ARM_SHARED_ARM_GIC_IRQ_H
25
26#include <bsp.h>
27#include <bsp/arm-gic.h>
28
29#ifdef __cplusplus
30extern "C" {
31#endif /* __cplusplus */
32
33#define ARM_GIC_IRQ_SGI_0 0
34#define ARM_GIC_IRQ_SGI_1 1
35#define ARM_GIC_IRQ_SGI_2 2
36#define ARM_GIC_IRQ_SGI_3 3
37#define ARM_GIC_IRQ_SGI_5 5
38#define ARM_GIC_IRQ_SGI_6 6
39#define ARM_GIC_IRQ_SGI_7 7
40#define ARM_GIC_IRQ_SGI_8 8
41#define ARM_GIC_IRQ_SGI_9 9
42#define ARM_GIC_IRQ_SGI_10 10
43#define ARM_GIC_IRQ_SGI_11 11
44#define ARM_GIC_IRQ_SGI_12 12
45#define ARM_GIC_IRQ_SGI_13 13
46#define ARM_GIC_IRQ_SGI_14 14
47#define ARM_GIC_IRQ_SGI_15 15
48
49#define ARM_GIC_DIST ((volatile gic_dist *) BSP_ARM_GIC_DIST_BASE)
50
51rtems_status_code arm_gic_irq_set_priority(
52  rtems_vector_number vector,
53  uint8_t priority
54);
55
56rtems_status_code arm_gic_irq_get_priority(
57  rtems_vector_number vector,
58  uint8_t *priority
59);
60
61void bsp_interrupt_set_affinity(
62  rtems_vector_number vector,
63  const Processor_mask *affinity
64);
65
66void bsp_interrupt_get_affinity(
67  rtems_vector_number vector,
68  Processor_mask *affinity
69);
70
71typedef enum {
72  ARM_GIC_IRQ_SOFTWARE_IRQ_TO_ALL_IN_LIST,
73  ARM_GIC_IRQ_SOFTWARE_IRQ_TO_ALL_EXCEPT_SELF,
74  ARM_GIC_IRQ_SOFTWARE_IRQ_TO_SELF
75} arm_gic_irq_software_irq_target_filter;
76
77static inline rtems_status_code arm_gic_irq_generate_software_irq(
78  rtems_vector_number vector,
79  arm_gic_irq_software_irq_target_filter filter,
80  uint8_t targets
81)
82{
83  rtems_status_code sc = RTEMS_SUCCESSFUL;
84
85  if (vector <= ARM_GIC_IRQ_SGI_15) {
86    volatile gic_dist *dist = ARM_GIC_DIST;
87
88    dist->icdsgir = GIC_DIST_ICDSGIR_TARGET_LIST_FILTER(filter)
89      | GIC_DIST_ICDSGIR_CPU_TARGET_LIST(targets)
90      | GIC_DIST_ICDSGIR_SGIINTID(vector);
91  } else {
92    sc = RTEMS_INVALID_ID;
93  }
94
95  return sc;
96}
97
98static inline uint32_t arm_gic_irq_processor_count(void)
99{
100  volatile gic_dist *dist = ARM_GIC_DIST;
101
102  return GIC_DIST_ICDICTR_CPU_NUMBER_GET(dist->icdictr) + 1;
103}
104
105void arm_gic_irq_initialize_secondary_cpu(void);
106
107#ifdef __cplusplus
108}
109#endif /* __cplusplus */
110
111#endif /* LIBBSP_ARM_SHARED_ARM_GIC_IRQ_H */
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