1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup arm_start |
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5 | * |
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6 | * @brief Arm CP15 start. |
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7 | */ |
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8 | |
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9 | |
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10 | /* |
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11 | * Copyright (c) 2013 Hesham AL-Matary. |
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12 | * Copyright (c) 2009-2014 embedded brains GmbH. All rights reserved. |
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13 | * |
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14 | * embedded brains GmbH |
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15 | * Dornierstr. 4 |
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16 | * 82178 Puchheim |
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17 | * Germany |
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18 | * <info@embedded-brains.de> |
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19 | * |
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20 | * The license and distribution terms for this file may be |
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21 | * found in the file LICENSE in this distribution or at |
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22 | * http://www.rtems.org/license/LICENSE. |
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23 | */ |
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24 | |
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25 | #ifndef LIBBSP_ARM_SHARED_ARM_CP15_START_H |
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26 | #define LIBBSP_ARM_SHARED_ARM_CP15_START_H |
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27 | |
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28 | #include <libcpu/arm-cp15.h> |
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29 | #include <bsp/start.h> |
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30 | #include <bsp/linker-symbols.h> |
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31 | |
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32 | #ifdef __cplusplus |
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33 | extern "C" { |
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34 | #endif /* __cplusplus */ |
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35 | |
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36 | typedef struct { |
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37 | uint32_t begin; |
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38 | uint32_t end; |
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39 | uint32_t flags; |
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40 | } arm_cp15_start_section_config; |
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41 | |
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42 | #define ARMV7_CP15_START_DEFAULT_SECTIONS \ |
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43 | { \ |
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44 | .begin = (uint32_t) bsp_section_fast_text_begin, \ |
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45 | .end = (uint32_t) bsp_section_fast_text_end, \ |
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46 | .flags = ARMV7_MMU_CODE_CACHED \ |
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47 | }, { \ |
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48 | .begin = (uint32_t) bsp_section_fast_data_begin, \ |
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49 | .end = (uint32_t) bsp_section_fast_data_end, \ |
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50 | .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED \ |
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51 | }, { \ |
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52 | .begin = (uint32_t) bsp_section_start_begin, \ |
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53 | .end = (uint32_t) bsp_section_start_end, \ |
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54 | .flags = ARMV7_MMU_CODE_CACHED \ |
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55 | }, { \ |
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56 | .begin = (uint32_t) bsp_section_vector_begin, \ |
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57 | .end = (uint32_t) bsp_section_vector_end, \ |
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58 | .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED \ |
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59 | }, { \ |
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60 | .begin = (uint32_t) bsp_section_text_begin, \ |
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61 | .end = (uint32_t) bsp_section_text_end, \ |
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62 | .flags = ARMV7_MMU_CODE_CACHED \ |
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63 | }, { \ |
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64 | .begin = (uint32_t) bsp_section_rodata_begin, \ |
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65 | .end = (uint32_t) bsp_section_rodata_end, \ |
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66 | .flags = ARMV7_MMU_DATA_READ_ONLY_CACHED \ |
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67 | }, { \ |
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68 | .begin = (uint32_t) bsp_section_data_begin, \ |
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69 | .end = (uint32_t) bsp_section_data_end, \ |
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70 | .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED \ |
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71 | }, { \ |
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72 | .begin = (uint32_t) bsp_section_bss_begin, \ |
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73 | .end = (uint32_t) bsp_section_bss_end, \ |
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74 | .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED \ |
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75 | }, { \ |
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76 | .begin = (uint32_t) bsp_section_work_begin, \ |
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77 | .end = (uint32_t) bsp_section_work_end, \ |
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78 | .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED \ |
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79 | }, { \ |
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80 | .begin = (uint32_t) bsp_section_stack_begin, \ |
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81 | .end = (uint32_t) bsp_section_stack_end, \ |
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82 | .flags = ARMV7_MMU_DATA_READ_WRITE_CACHED \ |
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83 | }, { \ |
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84 | .begin = (uint32_t) bsp_section_nocache_begin, \ |
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85 | .end = (uint32_t) bsp_section_nocache_end, \ |
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86 | .flags = ARMV7_MMU_DEVICE \ |
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87 | }, { \ |
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88 | .begin = (uint32_t) bsp_section_nocachenoload_begin, \ |
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89 | .end = (uint32_t) bsp_section_nocachenoload_end, \ |
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90 | .flags = ARMV7_MMU_DEVICE \ |
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91 | } |
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92 | |
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93 | BSP_START_DATA_SECTION extern const arm_cp15_start_section_config |
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94 | arm_cp15_start_mmu_config_table[]; |
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95 | |
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96 | BSP_START_DATA_SECTION extern const size_t |
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97 | arm_cp15_start_mmu_config_table_size; |
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98 | |
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99 | BSP_START_TEXT_SECTION static inline void |
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100 | arm_cp15_start_set_translation_table_entries( |
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101 | uint32_t *ttb, |
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102 | const arm_cp15_start_section_config *config |
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103 | ) |
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104 | { |
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105 | uint32_t i = ARM_MMU_SECT_GET_INDEX(config->begin); |
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106 | uint32_t iend = |
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107 | ARM_MMU_SECT_GET_INDEX(ARM_MMU_SECT_MVA_ALIGN_UP(config->end)); |
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108 | uint32_t index_mask = (1U << (32 - ARM_MMU_SECT_BASE_SHIFT)) - 1U; |
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109 | |
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110 | if (config->begin != config->end) { |
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111 | while (i != iend) { |
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112 | ttb [i] = (i << ARM_MMU_SECT_BASE_SHIFT) | config->flags; |
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113 | i = (i + 1U) & index_mask; |
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114 | } |
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115 | } |
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116 | } |
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117 | |
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118 | BSP_START_TEXT_SECTION static inline void |
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119 | arm_cp15_start_setup_translation_table( |
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120 | uint32_t *ttb, |
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121 | uint32_t client_domain, |
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122 | const arm_cp15_start_section_config *config_table, |
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123 | size_t config_count |
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124 | ) |
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125 | { |
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126 | uint32_t dac = ARM_CP15_DAC_DOMAIN(client_domain, ARM_CP15_DAC_CLIENT); |
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127 | size_t i; |
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128 | |
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129 | arm_cp15_set_domain_access_control(dac); |
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130 | arm_cp15_set_translation_table_base(ttb); |
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131 | |
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132 | /* Initialize translation table with invalid entries */ |
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133 | for (i = 0; i < ARM_MMU_TRANSLATION_TABLE_ENTRY_COUNT; ++i) { |
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134 | ttb [i] = 0; |
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135 | } |
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136 | |
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137 | for (i = 0; i < config_count; ++i) { |
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138 | arm_cp15_start_set_translation_table_entries(ttb, &config_table [i]); |
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139 | } |
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140 | } |
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141 | |
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142 | BSP_START_TEXT_SECTION static inline void |
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143 | arm_cp15_start_setup_translation_table_and_enable_mmu_and_cache( |
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144 | uint32_t ctrl, |
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145 | uint32_t *ttb, |
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146 | uint32_t client_domain, |
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147 | const arm_cp15_start_section_config *config_table, |
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148 | size_t config_count |
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149 | ) |
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150 | { |
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151 | arm_cp15_start_setup_translation_table( |
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152 | ttb, |
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153 | client_domain, |
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154 | config_table, |
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155 | config_count |
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156 | ); |
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157 | |
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158 | /* Enable MMU and cache */ |
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159 | ctrl |= ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M; |
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160 | |
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161 | arm_cp15_set_control(ctrl); |
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162 | } |
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163 | |
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164 | BSP_START_TEXT_SECTION static inline uint32_t |
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165 | arm_cp15_start_setup_mmu_and_cache(uint32_t ctrl_clear, uint32_t ctrl_set) |
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166 | { |
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167 | uint32_t ctrl = arm_cp15_get_control(); |
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168 | |
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169 | ctrl &= ~ctrl_clear; |
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170 | ctrl |= ctrl_set; |
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171 | |
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172 | arm_cp15_set_control(ctrl); |
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173 | |
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174 | arm_cp15_tlb_invalidate(); |
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175 | |
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176 | return ctrl; |
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177 | } |
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178 | |
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179 | #ifdef __cplusplus |
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180 | } |
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181 | #endif /* __cplusplus */ |
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182 | |
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183 | #endif /* LIBBSP_ARM_SHARED_ARM_CP15_START_H */ |
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