source: rtems/c/src/lib/libbsp/arm/shared/include/arm-cp15-start.h @ 0f874ee

4.115
Last change on this file since 0f874ee was 0f874ee, checked in by Sebastian Huber <sebastian.huber@…>, on 10/27/13 at 17:51:53

bsps/arm: Init trans tbl with invalid entries

  • Property mode set to 100644
File size: 3.2 KB
Line 
1/*
2 * Copyright (c) 2013 Hesham AL-Matary.
3 * Copyright (c) 2009-2013 embedded brains GmbH.  All rights reserved.
4 *
5 *  embedded brains GmbH
6 *  Dornierstr. 4
7 *  82178 Puchheim
8 *  Germany
9 *  <info@embedded-brains.de>
10 *
11 * The license and distribution terms for this file may be
12 * found in the file LICENSE in this distribution or at
13 * http://www.rtems.com/license/LICENSE.
14 */
15
16#ifndef LIBBSP_ARM_SHARED_ARM_CP15_START_H
17#define LIBBSP_ARM_SHARED_ARM_CP15_START_H
18
19#include <libcpu/arm-cp15.h>
20#include <bsp/start.h>
21
22#ifdef __cplusplus
23extern "C" {
24#endif /* __cplusplus */
25
26typedef struct {
27  uint32_t begin;
28  uint32_t end;
29  uint32_t flags;
30} arm_cp15_start_section_config;
31
32extern const arm_cp15_start_section_config bsp_mm_config_table[];
33extern const size_t bsp_mm_config_table_size;
34
35BSP_START_TEXT_SECTION static inline void
36arm_cp15_set_domain_access_control(uint32_t val);
37
38BSP_START_TEXT_SECTION static inline void
39arm_cp15_set_translation_table_base(uint32_t *base);
40
41BSP_START_TEXT_SECTION static inline void
42arm_cp15_set_control(uint32_t val);
43
44BSP_START_TEXT_SECTION static inline uint32_t
45arm_cp15_get_control(void);
46
47BSP_START_TEXT_SECTION static inline void
48arm_cp15_cache_invalidate(void);
49
50BSP_START_TEXT_SECTION static inline void
51arm_cp15_tlb_invalidate(void);
52
53BSP_START_TEXT_SECTION static inline uint32_t
54arm_cp15_get_multiprocessor_affinity(void);
55
56BSP_START_TEXT_SECTION static inline uint32_t
57arm_cortex_a9_get_multiprocessor_cpu_id(void);
58
59BSP_START_TEXT_SECTION static inline void
60arm_cp15_start_set_translation_table_entries(
61  uint32_t *ttb,
62  const arm_cp15_start_section_config *config
63)
64{
65  uint32_t i = ARM_MMU_SECT_GET_INDEX(config->begin);
66  uint32_t iend =
67    ARM_MMU_SECT_GET_INDEX(ARM_MMU_SECT_MVA_ALIGN_UP(config->end));
68  uint32_t index_mask = (1U << (32 - ARM_MMU_SECT_BASE_SHIFT)) - 1U;
69
70  if (config->begin != config->end) {
71    while (i != iend) {
72      ttb [i] = (i << ARM_MMU_SECT_BASE_SHIFT) | config->flags;
73      i = (i + 1U) & index_mask;
74    }
75  }
76}
77
78BSP_START_TEXT_SECTION static inline void
79arm_cp15_start_setup_translation_table_and_enable_mmu_and_cache(
80  uint32_t ctrl,
81  uint32_t *ttb,
82  uint32_t client_domain,
83  const arm_cp15_start_section_config *config_table,
84  size_t config_count
85)
86{
87  uint32_t dac = ARM_CP15_DAC_DOMAIN(client_domain, ARM_CP15_DAC_CLIENT);
88  size_t i;
89
90  arm_cp15_set_domain_access_control(dac);
91  arm_cp15_set_translation_table_base(ttb);
92
93  /* Initialize translation table with invalid entries */
94  for (i = 0; i < ARM_MMU_TRANSLATION_TABLE_ENTRY_COUNT; ++i) {
95    ttb [i] = 0;
96  }
97
98  for (i = 0; i < config_count; ++i) {
99    arm_cp15_start_set_translation_table_entries(ttb, &config_table [i]);
100  }
101
102  /* Enable MMU and cache */
103  ctrl |= ARM_CP15_CTRL_AFE | ARM_CP15_CTRL_S | ARM_CP15_CTRL_I |
104          ARM_CP15_CTRL_C | ARM_CP15_CTRL_M  | ARM_CP15_CTRL_XP;
105
106  arm_cp15_set_control(ctrl);
107}
108
109BSP_START_TEXT_SECTION static inline uint32_t
110arm_cp15_start_setup_mmu_and_cache(uint32_t ctrl_clear, uint32_t ctrl_set)
111{
112  uint32_t ctrl = arm_cp15_get_control();
113
114  ctrl &= ~ctrl_clear;
115  ctrl |= ctrl_set;
116
117  arm_cp15_set_control(ctrl);
118
119  arm_cp15_tlb_invalidate();
120
121  return ctrl;
122}
123
124#ifdef __cplusplus
125}
126#endif /* __cplusplus */
127
128#endif /* LIBBSP_ARM_SHARED_ARM_CP15_START_H */
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