[ecf7dd9] | 1 | /* |
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| 2 | * Copyright (c) 2009-2013 embedded brains GmbH. All rights reserved. |
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| 3 | * |
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| 4 | * embedded brains GmbH |
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| 5 | * Dornierstr. 4 |
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| 6 | * 82178 Puchheim |
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| 7 | * Germany |
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| 8 | * <info@embedded-brains.de> |
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| 9 | * |
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| 10 | * The license and distribution terms for this file may be |
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| 11 | * found in the file LICENSE in this distribution or at |
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| 12 | * http://www.rtems.com/license/LICENSE. |
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| 13 | */ |
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| 14 | |
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| 15 | #ifndef LIBBSP_ARM_SHARED_ARM_CP15_START_H |
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| 16 | #define LIBBSP_ARM_SHARED_ARM_CP15_START_H |
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| 17 | |
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| 18 | #include <libcpu/arm-cp15.h> |
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| 19 | |
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| 20 | #include <bsp/start.h> |
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| 21 | |
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| 22 | #ifdef __cplusplus |
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| 23 | extern "C" { |
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| 24 | #endif /* __cplusplus */ |
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| 25 | |
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| 26 | BSP_START_TEXT_SECTION static inline void |
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| 27 | arm_cp15_set_domain_access_control(uint32_t val); |
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| 28 | |
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| 29 | BSP_START_TEXT_SECTION static inline void |
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| 30 | arm_cp15_set_translation_table_base(uint32_t *base); |
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| 31 | |
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| 32 | BSP_START_TEXT_SECTION static inline void |
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| 33 | arm_cp15_set_control(uint32_t val); |
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| 34 | |
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| 35 | BSP_START_TEXT_SECTION static inline uint32_t |
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| 36 | arm_cp15_get_control(void); |
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| 37 | |
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| 38 | BSP_START_TEXT_SECTION static inline void |
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| 39 | arm_cp15_cache_invalidate(void); |
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| 40 | |
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| 41 | BSP_START_TEXT_SECTION static inline void |
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| 42 | arm_cp15_tlb_invalidate(void); |
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| 43 | |
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[db42c079] | 44 | BSP_START_TEXT_SECTION static inline uint32_t |
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| 45 | arm_cp15_get_multiprocessor_affinity(void); |
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| 46 | |
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| 47 | BSP_START_TEXT_SECTION static inline uint32_t |
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| 48 | arm_cortex_a9_get_multiprocessor_cpu_id(void); |
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| 49 | |
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[ecf7dd9] | 50 | typedef struct { |
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| 51 | uint32_t begin; |
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| 52 | uint32_t end; |
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| 53 | uint32_t flags; |
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| 54 | } arm_cp15_start_section_config; |
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| 55 | |
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| 56 | BSP_START_TEXT_SECTION static inline void |
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| 57 | arm_cp15_start_set_translation_table_entries( |
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| 58 | uint32_t *ttb, |
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| 59 | const arm_cp15_start_section_config *config |
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| 60 | ) |
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| 61 | { |
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| 62 | uint32_t i = ARM_MMU_SECT_GET_INDEX(config->begin); |
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| 63 | uint32_t iend = |
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| 64 | ARM_MMU_SECT_GET_INDEX(ARM_MMU_SECT_MVA_ALIGN_UP(config->end)); |
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| 65 | |
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| 66 | if (config->begin != config->end) { |
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| 67 | while (i < iend) { |
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| 68 | ttb [i] = (i << ARM_MMU_SECT_BASE_SHIFT) | config->flags; |
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| 69 | ++i; |
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| 70 | } |
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| 71 | } |
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| 72 | } |
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| 73 | |
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| 74 | BSP_START_TEXT_SECTION static void |
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| 75 | arm_cp15_start_setup_translation_table_and_enable_mmu( |
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| 76 | uint32_t ctrl, |
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| 77 | uint32_t *ttb, |
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| 78 | uint32_t client_domain, |
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| 79 | const arm_cp15_start_section_config *config_table, |
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| 80 | size_t config_count |
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| 81 | ) |
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| 82 | { |
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| 83 | uint32_t dac = ARM_CP15_DAC_DOMAIN(client_domain, ARM_CP15_DAC_CLIENT); |
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| 84 | size_t i; |
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| 85 | |
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| 86 | arm_cp15_set_domain_access_control(dac); |
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| 87 | arm_cp15_set_translation_table_base(ttb); |
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| 88 | |
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| 89 | /* Initialize translation table with invalid entries */ |
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| 90 | for (i = 0; i < ARM_MMU_TRANSLATION_TABLE_ENTRY_COUNT; ++i) { |
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| 91 | ttb [i] = 0; |
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| 92 | } |
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| 93 | |
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| 94 | for (i = 0; i < config_count; ++i) { |
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| 95 | arm_cp15_start_set_translation_table_entries(ttb, &config_table [i]); |
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| 96 | } |
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| 97 | |
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| 98 | /* Enable MMU and cache */ |
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| 99 | ctrl |= ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M; |
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| 100 | arm_cp15_set_control(ctrl); |
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| 101 | } |
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| 102 | |
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| 103 | BSP_START_TEXT_SECTION static inline uint32_t |
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| 104 | arm_cp15_start_setup_mmu_and_cache(uint32_t ctrl_clear, uint32_t ctrl_set) |
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| 105 | { |
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| 106 | uint32_t ctrl = arm_cp15_get_control(); |
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| 107 | |
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| 108 | ctrl &= ~ctrl_clear; |
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| 109 | ctrl |= ctrl_set; |
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| 110 | |
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| 111 | arm_cp15_set_control(ctrl); |
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| 112 | |
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| 113 | arm_cp15_tlb_invalidate(); |
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| 114 | |
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| 115 | return ctrl; |
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| 116 | } |
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| 117 | |
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| 118 | #ifdef __cplusplus |
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| 119 | } |
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| 120 | #endif /* __cplusplus */ |
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| 121 | |
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| 122 | #endif /* LIBBSP_ARM_SHARED_ARM_CP15_START_H */ |
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