1 | /** |
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2 | * @file arm-cache-l1.h |
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3 | * |
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4 | * @ingroup arm_shared |
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5 | * |
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6 | * @brief Level 1 Cache definitions and functions. |
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7 | * |
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8 | * This file implements handling for the ARM Level 1 cache controller |
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9 | */ |
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10 | |
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11 | /* |
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12 | * Copyright (c) 2014 embedded brains GmbH. All rights reserved. |
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13 | * |
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14 | * embedded brains GmbH |
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15 | * Dornierstr. 4 |
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16 | * 82178 Puchheim |
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17 | * Germany |
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18 | * <rtems@embedded-brains.de> |
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19 | * |
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20 | * The license and distribution terms for this file may be |
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21 | * found in the file LICENSE in this distribution or at |
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22 | * http://www.rtems.org/license/LICENSE. |
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23 | */ |
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24 | |
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25 | #ifndef LIBBSP_ARM_SHARED_CACHE_L1_H |
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26 | #define LIBBSP_ARM_SHARED_CACHE_L1_H |
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27 | |
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28 | #include <bsp.h> |
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29 | #include <libcpu/arm-cp15.h> |
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30 | |
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31 | #ifdef __cplusplus |
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32 | extern "C" { |
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33 | #endif /* __cplusplus */ |
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34 | |
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35 | /* These two defines also ensure that the rtems_cache_* functions have bodies */ |
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36 | #define ARM_CACHE_L1_CPU_DATA_ALIGNMENT 32 |
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37 | #define ARM_CACHE_L1_CPU_INSTRUCTION_ALIGNMENT 32 |
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38 | #define ARM_CACHE_L1_CPU_SUPPORT_PROVIDES_RANGE_FUNCTIONS |
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39 | |
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40 | #define ARM_CACHE_L1_CSS_ID_DATA \ |
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41 | (ARM_CP15_CACHE_CSS_ID_DATA | ARM_CP15_CACHE_CSS_LEVEL(0)) |
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42 | #define ARM_CACHE_L1_CSS_ID_INSTRUCTION \ |
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43 | (ARM_CP15_CACHE_CSS_ID_INSTRUCTION | ARM_CP15_CACHE_CSS_LEVEL(0)) |
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44 | #define ARM_CACHE_L1_DATA_LINE_MASK ( ARM_CACHE_L1_CPU_DATA_ALIGNMENT - 1 ) |
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45 | #define ARM_CACHE_L1_INSTRUCTION_LINE_MASK \ |
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46 | ( ARM_CACHE_L1_CPU_INSTRUCTION_ALIGNMENT \ |
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47 | - 1 ) |
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48 | |
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49 | /* Errata Handlers */ |
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50 | static void arm_cache_l1_errata_764369_handler( void ) |
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51 | { |
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52 | #ifdef RTEMS_SMP |
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53 | _ARM_Data_synchronization_barrier(); |
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54 | #endif |
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55 | } |
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56 | |
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57 | /* |
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58 | * @param l1LineSize Number of bytes in cache line expressed as power of |
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59 | * 2 value |
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60 | * @param l1Associativity Associativity of cache. The associativity does not |
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61 | * have to be a power of 2. |
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62 | * qparam liNumSets Number of sets in cache |
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63 | * */ |
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64 | |
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65 | static inline void arm_cache_l1_properties_for_level( |
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66 | uint32_t *l1LineSize, |
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67 | uint32_t *l1Associativity, |
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68 | uint32_t *l1NumSets, |
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69 | uint32_t level_and_inst_dat |
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70 | ) |
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71 | { |
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72 | uint32_t ccsidr; |
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73 | |
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74 | ccsidr = arm_cp15_get_cache_size_id_for_level(level_and_inst_dat); |
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75 | |
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76 | /* Cache line size in words + 2 -> bytes) */ |
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77 | *l1LineSize = arm_ccsidr_get_line_power(ccsidr); |
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78 | /* Number of Ways */ |
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79 | *l1Associativity = arm_ccsidr_get_associativity(ccsidr); |
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80 | /* Number of Sets */ |
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81 | *l1NumSets = arm_ccsidr_get_num_sets(ccsidr); |
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82 | } |
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83 | |
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84 | /* |
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85 | * @param log_2_line_bytes The number of bytes per cache line expressed in log2 |
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86 | * @param associativity The associativity of the cache beeing operated |
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87 | * @param cache_level_idx The level of the cache beeing operated minus 1 e.g 0 |
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88 | * for cache level 1 |
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89 | * @param set Number of the set to operate on |
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90 | * @param way Number of the way to operate on |
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91 | * */ |
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92 | |
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93 | static inline uint32_t arm_cache_l1_get_set_way_param( |
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94 | const uint32_t log_2_line_bytes, |
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95 | const uint32_t associativity, |
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96 | const uint32_t cache_level_idx, |
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97 | const uint32_t set, |
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98 | const uint32_t way ) |
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99 | { |
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100 | uint32_t way_shift = __builtin_clz( associativity - 1 ); |
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101 | |
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102 | |
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103 | return ( 0 |
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104 | | ( way |
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105 | << way_shift ) | ( set << log_2_line_bytes ) | ( cache_level_idx << 1 ) ); |
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106 | } |
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107 | |
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108 | static inline void arm_cache_l1_flush_1_data_line( const void *d_addr ) |
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109 | { |
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110 | /* Flush the Data cache */ |
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111 | arm_cp15_data_cache_clean_and_invalidate_line( d_addr ); |
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112 | |
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113 | /* Wait for L1 flush to complete */ |
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114 | _ARM_Data_synchronization_barrier(); |
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115 | } |
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116 | |
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117 | static inline void arm_cache_l1_flush_entire_data( void ) |
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118 | { |
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119 | uint32_t l1LineSize, l1Associativity, l1NumSets; |
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120 | uint32_t s, w; |
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121 | uint32_t set_way_param; |
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122 | |
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123 | /* ensure ordering with previous memory accesses */ |
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124 | _ARM_Data_memory_barrier(); |
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125 | |
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126 | /* Get the L1 cache properties */ |
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127 | arm_cache_l1_properties_for_level( &l1LineSize, |
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128 | &l1Associativity, &l1NumSets, |
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129 | ARM_CACHE_L1_CSS_ID_DATA); |
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130 | |
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131 | for ( w = 0; w < l1Associativity; ++w ) { |
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132 | for ( s = 0; s < l1NumSets; ++s ) { |
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133 | set_way_param = arm_cache_l1_get_set_way_param( |
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134 | l1LineSize, |
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135 | l1Associativity, |
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136 | 0, |
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137 | s, |
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138 | w |
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139 | ); |
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140 | arm_cp15_data_cache_clean_line_by_set_and_way( set_way_param ); |
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141 | } |
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142 | } |
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143 | |
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144 | /* Wait for L1 flush to complete */ |
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145 | _ARM_Data_synchronization_barrier(); |
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146 | } |
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147 | |
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148 | static inline void arm_cache_l1_invalidate_entire_data( void ) |
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149 | { |
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150 | uint32_t l1LineSize, l1Associativity, l1NumSets; |
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151 | uint32_t s, w; |
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152 | uint32_t set_way_param; |
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153 | |
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154 | /* ensure ordering with previous memory accesses */ |
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155 | _ARM_Data_memory_barrier(); |
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156 | |
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157 | /* Get the L1 cache properties */ |
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158 | arm_cache_l1_properties_for_level( &l1LineSize, |
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159 | &l1Associativity, &l1NumSets, |
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160 | ARM_CACHE_L1_CSS_ID_DATA); |
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161 | |
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162 | for ( w = 0; w < l1Associativity; ++w ) { |
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163 | for ( s = 0; s < l1NumSets; ++s ) { |
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164 | set_way_param = arm_cache_l1_get_set_way_param( |
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165 | l1LineSize, |
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166 | l1Associativity, |
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167 | 0, |
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168 | s, |
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169 | w |
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170 | ); |
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171 | arm_cp15_data_cache_invalidate_line_by_set_and_way( set_way_param ); |
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172 | } |
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173 | } |
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174 | |
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175 | /* Wait for L1 invalidate to complete */ |
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176 | _ARM_Data_synchronization_barrier(); |
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177 | } |
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178 | |
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179 | static inline void arm_cache_l1_clean_and_invalidate_entire_data( void ) |
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180 | { |
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181 | uint32_t l1LineSize, l1Associativity, l1NumSets; |
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182 | uint32_t s, w; |
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183 | uint32_t set_way_param; |
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184 | |
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185 | /* ensure ordering with previous memory accesses */ |
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186 | _ARM_Data_memory_barrier(); |
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187 | |
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188 | |
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189 | /* Get the L1 cache properties */ |
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190 | arm_cache_l1_properties_for_level( &l1LineSize, |
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191 | &l1Associativity, &l1NumSets, |
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192 | ARM_CACHE_L1_CSS_ID_DATA); |
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193 | |
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194 | for ( w = 0; w < l1Associativity; ++w ) { |
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195 | for ( s = 0; s < l1NumSets; ++s ) { |
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196 | set_way_param = arm_cache_l1_get_set_way_param( |
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197 | l1LineSize, |
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198 | l1Associativity, |
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199 | 0, |
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200 | s, |
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201 | w |
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202 | ); |
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203 | arm_cp15_data_cache_clean_and_invalidate_line_by_set_and_way( |
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204 | set_way_param ); |
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205 | } |
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206 | } |
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207 | |
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208 | /* Wait for L1 invalidate to complete */ |
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209 | _ARM_Data_synchronization_barrier(); |
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210 | } |
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211 | |
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212 | static inline void arm_cache_l1_flush_data_range( |
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213 | const void *d_addr, |
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214 | size_t n_bytes |
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215 | ) |
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216 | { |
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217 | if ( n_bytes != 0 ) { |
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218 | uint32_t adx = (uint32_t) d_addr |
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219 | & ~ARM_CACHE_L1_DATA_LINE_MASK; |
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220 | const uint32_t ADDR_LAST = |
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221 | (uint32_t)( (size_t) d_addr + n_bytes - 1 ); |
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222 | |
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223 | arm_cache_l1_errata_764369_handler(); |
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224 | |
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225 | for (; adx <= ADDR_LAST; adx += ARM_CACHE_L1_CPU_DATA_ALIGNMENT ) { |
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226 | /* Store and invalidate the Data cache line */ |
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227 | arm_cp15_data_cache_clean_and_invalidate_line( (void*)adx ); |
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228 | } |
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229 | /* Wait for L1 store to complete */ |
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230 | _ARM_Data_synchronization_barrier(); |
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231 | } |
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232 | } |
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233 | |
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234 | |
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235 | static inline void arm_cache_l1_invalidate_1_data_line( |
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236 | const void *d_addr ) |
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237 | { |
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238 | /* Invalidate the data cache line */ |
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239 | arm_cp15_data_cache_invalidate_line( d_addr ); |
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240 | |
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241 | /* Wait for L1 invalidate to complete */ |
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242 | _ARM_Data_synchronization_barrier(); |
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243 | } |
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244 | |
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245 | static inline void arm_cache_l1_freeze_data( void ) |
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246 | { |
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247 | /* To be implemented as needed, if supported by hardware at all */ |
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248 | } |
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249 | |
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250 | static inline void arm_cache_l1_unfreeze_data( void ) |
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251 | { |
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252 | /* To be implemented as needed, if supported by hardware at all */ |
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253 | } |
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254 | |
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255 | static inline void arm_cache_l1_invalidate_1_instruction_line( |
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256 | const void *i_addr ) |
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257 | { |
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258 | /* Invalidate the Instruction cache line */ |
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259 | arm_cp15_instruction_cache_invalidate_line( i_addr ); |
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260 | |
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261 | /* Wait for L1 invalidate to complete */ |
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262 | _ARM_Data_synchronization_barrier(); |
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263 | } |
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264 | |
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265 | static inline void arm_cache_l1_invalidate_data_range( |
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266 | const void *d_addr, |
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267 | size_t n_bytes |
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268 | ) |
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269 | { |
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270 | if ( n_bytes != 0 ) { |
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271 | uint32_t adx = (uint32_t) d_addr |
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272 | & ~ARM_CACHE_L1_DATA_LINE_MASK; |
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273 | const uint32_t end = |
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274 | (uint32_t)( (size_t)d_addr + n_bytes -1); |
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275 | |
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276 | arm_cache_l1_errata_764369_handler(); |
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277 | |
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278 | /* Back starting address up to start of a line and invalidate until end */ |
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279 | for (; |
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280 | adx <= end; |
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281 | adx += ARM_CACHE_L1_CPU_DATA_ALIGNMENT ) { |
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282 | /* Invalidate the Instruction cache line */ |
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283 | arm_cp15_data_cache_invalidate_line( (void*)adx ); |
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284 | } |
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285 | /* Wait for L1 invalidate to complete */ |
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286 | _ARM_Data_synchronization_barrier(); |
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287 | } |
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288 | } |
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289 | |
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290 | static inline void arm_cache_l1_invalidate_instruction_range( |
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291 | const void *i_addr, |
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292 | size_t n_bytes |
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293 | ) |
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294 | { |
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295 | if ( n_bytes != 0 ) { |
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296 | uint32_t adx = (uint32_t) i_addr |
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297 | & ~ARM_CACHE_L1_INSTRUCTION_LINE_MASK; |
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298 | const uint32_t end = |
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299 | (uint32_t)( (size_t)i_addr + n_bytes -1); |
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300 | |
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301 | arm_cache_l1_errata_764369_handler(); |
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302 | |
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303 | /* Back starting address up to start of a line and invalidate until end */ |
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304 | for (; |
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305 | adx <= end; |
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306 | adx += ARM_CACHE_L1_CPU_INSTRUCTION_ALIGNMENT ) { |
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307 | /* Invalidate the Instruction cache line */ |
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308 | arm_cp15_instruction_cache_invalidate_line( (void*)adx ); |
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309 | } |
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310 | /* Wait for L1 invalidate to complete */ |
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311 | _ARM_Data_synchronization_barrier(); |
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312 | } |
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313 | } |
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314 | |
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315 | static inline void arm_cache_l1_invalidate_entire_instruction( void ) |
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316 | { |
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317 | uint32_t ctrl = arm_cp15_get_control(); |
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318 | |
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319 | |
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320 | #ifdef RTEMS_SMP |
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321 | |
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322 | /* invalidate I-cache inner shareable */ |
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323 | arm_cp15_instruction_cache_inner_shareable_invalidate_all(); |
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324 | |
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325 | /* I+BTB cache invalidate */ |
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326 | arm_cp15_instruction_cache_invalidate(); |
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327 | #else /* RTEMS_SMP */ |
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328 | /* I+BTB cache invalidate */ |
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329 | arm_cp15_instruction_cache_invalidate(); |
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330 | #endif /* RTEMS_SMP */ |
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331 | |
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332 | if ( ( ctrl & ARM_CP15_CTRL_Z ) == 0 ) { |
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333 | arm_cp15_branch_predictor_inner_shareable_invalidate_all(); |
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334 | arm_cp15_branch_predictor_invalidate_all(); |
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335 | } |
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336 | } |
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337 | |
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338 | static inline void arm_cache_l1_freeze_instruction( void ) |
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339 | { |
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340 | /* To be implemented as needed, if supported by hardware at all */ |
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341 | } |
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342 | |
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343 | static inline void arm_cache_l1_unfreeze_instruction( void ) |
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344 | { |
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345 | /* To be implemented as needed, if supported by hardware at all */ |
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346 | } |
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347 | |
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348 | static inline void arm_cache_l1_disable_data( void ) |
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349 | { |
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350 | /* Clean and invalidate the Data cache */ |
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351 | arm_cache_l1_flush_entire_data(); |
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352 | |
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353 | /* Disable the Data cache */ |
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354 | arm_cp15_set_control( arm_cp15_get_control() & ~ARM_CP15_CTRL_C ); |
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355 | } |
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356 | |
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357 | static inline void arm_cache_l1_disable_instruction( void ) |
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358 | { |
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359 | /* Synchronize the processor */ |
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360 | _ARM_Data_synchronization_barrier(); |
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361 | |
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362 | /* Invalidate the Instruction cache */ |
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363 | arm_cache_l1_invalidate_entire_instruction(); |
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364 | |
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365 | /* Disable the Instruction cache */ |
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366 | arm_cp15_set_control( arm_cp15_get_control() & ~ARM_CP15_CTRL_I ); |
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367 | } |
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368 | |
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369 | static inline size_t arm_cache_l1_get_data_cache_size( void ) |
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370 | { |
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371 | size_t size; |
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372 | uint32_t line_size = 0; |
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373 | uint32_t associativity = 0; |
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374 | uint32_t num_sets = 0; |
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375 | |
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376 | arm_cache_l1_properties_for_level( &line_size, |
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377 | &associativity, &num_sets, |
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378 | ARM_CACHE_L1_CSS_ID_DATA); |
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379 | |
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380 | size = (1 << line_size) * associativity * num_sets; |
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381 | |
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382 | return size; |
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383 | } |
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384 | |
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385 | static inline size_t arm_cache_l1_get_instruction_cache_size( void ) |
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386 | { |
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387 | size_t size; |
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388 | uint32_t line_size = 0; |
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389 | uint32_t associativity = 0; |
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390 | uint32_t num_sets = 0; |
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391 | |
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392 | arm_cache_l1_properties_for_level( &line_size, |
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393 | &associativity, &num_sets, |
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394 | ARM_CACHE_L1_CSS_ID_INSTRUCTION); |
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395 | |
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396 | size = (1 << line_size) * associativity * num_sets; |
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397 | |
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398 | return size; |
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399 | } |
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400 | |
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401 | #ifdef __cplusplus |
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402 | } |
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403 | #endif /* __cplusplus */ |
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404 | |
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405 | #endif /* LIBBSP_ARM_SHARED_CACHE_L1_H */ |
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