1 | /** |
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2 | * @file arm-cache-l1.h |
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3 | * |
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4 | * @ingroup arm_shared |
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5 | * |
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6 | * @brief Level 1 Cache definitions and functions. |
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7 | * |
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8 | * This file implements handling for the ARM Level 1 cache controller |
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9 | */ |
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10 | |
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11 | /* |
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12 | * Copyright (c) 2014 embedded brains GmbH. All rights reserved. |
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13 | * |
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14 | * embedded brains GmbH |
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15 | * Dornierstr. 4 |
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16 | * 82178 Puchheim |
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17 | * Germany |
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18 | * <rtems@embedded-brains.de> |
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19 | * |
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20 | * The license and distribution terms for this file may be |
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21 | * found in the file LICENSE in this distribution or at |
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22 | * http://www.rtems.org/license/LICENSE. |
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23 | */ |
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24 | |
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25 | #ifndef LIBBSP_ARM_SHARED_CACHE_L1_H |
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26 | #define LIBBSP_ARM_SHARED_CACHE_L1_H |
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27 | |
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28 | #include <assert.h> |
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29 | #include <bsp.h> |
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30 | #include <libcpu/arm-cp15.h> |
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31 | |
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32 | #ifdef __cplusplus |
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33 | extern "C" { |
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34 | #endif /* __cplusplus */ |
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35 | |
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36 | /* These two defines also ensure that the rtems_cache_* functions have bodies */ |
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37 | #define ARM_CACHE_L1_CPU_DATA_ALIGNMENT 32 |
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38 | #define ARM_CACHE_L1_CPU_INSTRUCTION_ALIGNMENT 32 |
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39 | #define ARM_CACHE_L1_CPU_SUPPORT_PROVIDES_RANGE_FUNCTIONS |
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40 | |
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41 | #define ARM_CACHE_L1_CSS_ID_DATA 0 |
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42 | #define ARM_CACHE_L1_CSS_ID_INSTRUCTION 1 |
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43 | #define ARM_CACHE_L1_DATA_LINE_MASK ( ARM_CACHE_L1_CPU_DATA_ALIGNMENT - 1 ) |
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44 | #define ARM_CACHE_L1_INSTRUCTION_LINE_MASK \ |
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45 | ( ARM_CACHE_L1_CPU_INSTRUCTION_ALIGNMENT \ |
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46 | - 1 ) |
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47 | |
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48 | /* Errata Handlers */ |
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49 | #if ( defined( RTEMS_SMP ) ) |
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50 | #define ARM_CACHE_L1_ERRATA_764369_HANDLER() \ |
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51 | if( arm_errata_is_applicable_processor_errata_764369() ) { \ |
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52 | _ARM_Data_synchronization_barrier(); \ |
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53 | } |
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54 | #else /* #if ( defined( RTEMS_SMP ) ) */ |
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55 | #define ARM_CACHE_L1_ERRATA_764369_HANDLER() |
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56 | #endif /* #if ( defined( RTEMS_SMP ) ) */ |
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57 | |
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58 | |
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59 | static void arm_cache_l1_select( const uint32_t selection ) |
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60 | { |
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61 | /* select current cache level in cssr */ |
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62 | arm_cp15_set_cache_size_selection( selection ); |
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63 | |
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64 | /* isb to sych the new cssr&csidr */ |
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65 | _ARM_Instruction_synchronization_barrier(); |
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66 | } |
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67 | |
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68 | /* |
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69 | * @param l1LineSize Number of bytes in cache line expressed as power of |
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70 | * 2 value |
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71 | * @param l1Associativity Associativity of cache. The associativity does not |
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72 | * have to be a power of 2. |
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73 | * qparam liNumSets Number of sets in cache |
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74 | * */ |
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75 | |
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76 | static inline void arm_cache_l1_properties( |
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77 | uint32_t *l1LineSize, |
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78 | uint32_t *l1Associativity, |
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79 | uint32_t *l1NumSets ) |
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80 | { |
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81 | uint32_t id; |
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82 | |
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83 | _ARM_Instruction_synchronization_barrier(); |
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84 | id = arm_cp15_get_cache_size_id(); |
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85 | |
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86 | /* Cache line size in words + 2 -> bytes) */ |
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87 | *l1LineSize = ( id & 0x0007U ) + 2 + 2; |
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88 | /* Number of Ways */ |
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89 | *l1Associativity = ( ( id >> 3 ) & 0x03ffU ) + 1; |
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90 | /* Number of Sets */ |
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91 | *l1NumSets = ( ( id >> 13 ) & 0x7fffU ) + 1; |
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92 | } |
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93 | |
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94 | /* |
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95 | * @param log_2_line_bytes The number of bytes per cache line expressed in log2 |
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96 | * @param associativity The associativity of the cache beeing operated |
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97 | * @param cache_level_idx The level of the cache beeing operated minus 1 e.g 0 |
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98 | * for cache level 1 |
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99 | * @param set Number of the set to operate on |
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100 | * @param way Number of the way to operate on |
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101 | * */ |
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102 | |
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103 | static inline uint32_t arm_cache_l1_get_set_way_param( |
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104 | const uint32_t log_2_line_bytes, |
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105 | const uint32_t associativity, |
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106 | const uint32_t cache_level_idx, |
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107 | const uint32_t set, |
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108 | const uint32_t way ) |
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109 | { |
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110 | uint32_t way_shift = __builtin_clz( associativity - 1 ); |
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111 | |
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112 | |
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113 | return ( 0 |
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114 | | ( way |
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115 | << way_shift ) | ( set << log_2_line_bytes ) | ( cache_level_idx << 1 ) ); |
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116 | } |
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117 | |
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118 | static inline void arm_cache_l1_flush_1_data_line( const void *d_addr ) |
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119 | { |
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120 | /* Flush the Data cache */ |
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121 | arm_cp15_data_cache_clean_and_invalidate_line( d_addr ); |
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122 | |
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123 | /* Wait for L1 flush to complete */ |
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124 | _ARM_Data_synchronization_barrier(); |
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125 | } |
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126 | |
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127 | static inline void arm_cache_l1_flush_entire_data( void ) |
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128 | { |
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129 | uint32_t l1LineSize, l1Associativity, l1NumSets; |
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130 | uint32_t s, w; |
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131 | uint32_t set_way_param; |
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132 | rtems_interrupt_level level; |
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133 | |
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134 | |
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135 | /* ensure ordering with previous memory accesses */ |
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136 | _ARM_Data_memory_barrier(); |
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137 | |
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138 | /* make cssr&csidr read atomic */ |
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139 | rtems_interrupt_disable( level ); |
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140 | |
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141 | /* Get the L1 cache properties */ |
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142 | arm_cache_l1_properties( &l1LineSize, &l1Associativity, |
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143 | &l1NumSets ); |
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144 | rtems_interrupt_enable( level ); |
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145 | |
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146 | for ( w = 0; w < l1Associativity; ++w ) { |
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147 | for ( s = 0; s < l1NumSets; ++s ) { |
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148 | set_way_param = arm_cache_l1_get_set_way_param( |
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149 | l1LineSize, |
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150 | l1Associativity, |
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151 | 0, |
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152 | s, |
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153 | w |
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154 | ); |
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155 | arm_cp15_data_cache_clean_line_by_set_and_way( set_way_param ); |
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156 | } |
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157 | } |
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158 | |
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159 | /* Wait for L1 flush to complete */ |
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160 | _ARM_Data_synchronization_barrier(); |
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161 | } |
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162 | |
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163 | static inline void arm_cache_l1_invalidate_entire_data( void ) |
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164 | { |
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165 | uint32_t l1LineSize, l1Associativity, l1NumSets; |
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166 | uint32_t s, w; |
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167 | uint32_t set_way_param; |
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168 | rtems_interrupt_level level; |
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169 | |
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170 | |
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171 | /* ensure ordering with previous memory accesses */ |
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172 | _ARM_Data_memory_barrier(); |
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173 | |
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174 | /* make cssr&csidr read atomic */ |
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175 | rtems_interrupt_disable( level ); |
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176 | |
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177 | /* Get the L1 cache properties */ |
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178 | arm_cache_l1_properties( &l1LineSize, &l1Associativity, |
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179 | &l1NumSets ); |
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180 | rtems_interrupt_enable( level ); |
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181 | |
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182 | for ( w = 0; w < l1Associativity; ++w ) { |
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183 | for ( s = 0; s < l1NumSets; ++s ) { |
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184 | set_way_param = arm_cache_l1_get_set_way_param( |
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185 | l1LineSize, |
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186 | l1Associativity, |
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187 | 0, |
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188 | s, |
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189 | w |
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190 | ); |
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191 | arm_cp15_data_cache_invalidate_line_by_set_and_way( set_way_param ); |
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192 | } |
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193 | } |
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194 | |
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195 | /* Wait for L1 invalidate to complete */ |
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196 | _ARM_Data_synchronization_barrier(); |
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197 | } |
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198 | |
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199 | static inline void arm_cache_l1_clean_and_invalidate_entire_data( void ) |
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200 | { |
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201 | uint32_t l1LineSize, l1Associativity, l1NumSets; |
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202 | uint32_t s, w; |
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203 | uint32_t set_way_param; |
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204 | rtems_interrupt_level level; |
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205 | |
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206 | |
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207 | /* ensure ordering with previous memory accesses */ |
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208 | _ARM_Data_memory_barrier(); |
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209 | |
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210 | /* make cssr&csidr read atomic */ |
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211 | rtems_interrupt_disable( level ); |
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212 | |
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213 | /* Get the L1 cache properties */ |
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214 | arm_cache_l1_properties( &l1LineSize, &l1Associativity, |
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215 | &l1NumSets ); |
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216 | rtems_interrupt_enable( level ); |
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217 | |
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218 | for ( w = 0; w < l1Associativity; ++w ) { |
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219 | for ( s = 0; s < l1NumSets; ++s ) { |
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220 | set_way_param = arm_cache_l1_get_set_way_param( |
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221 | l1LineSize, |
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222 | l1Associativity, |
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223 | 0, |
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224 | s, |
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225 | w |
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226 | ); |
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227 | arm_cp15_data_cache_clean_and_invalidate_line_by_set_and_way( |
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228 | set_way_param ); |
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229 | } |
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230 | } |
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231 | |
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232 | /* Wait for L1 invalidate to complete */ |
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233 | _ARM_Data_synchronization_barrier(); |
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234 | } |
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235 | |
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236 | static inline void arm_cache_l1_store_data( const void *d_addr ) |
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237 | { |
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238 | /* Store the Data cache line */ |
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239 | arm_cp15_data_cache_clean_line( d_addr ); |
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240 | |
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241 | /* Wait for L1 store to complete */ |
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242 | _ARM_Data_synchronization_barrier(); |
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243 | } |
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244 | |
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245 | static inline void arm_cache_l1_flush_data_range( |
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246 | const void *d_addr, |
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247 | size_t n_bytes |
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248 | ) |
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249 | { |
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250 | if ( n_bytes != 0 ) { |
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251 | uint32_t adx = (uint32_t) d_addr |
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252 | & ~ARM_CACHE_L1_DATA_LINE_MASK; |
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253 | const uint32_t ADDR_LAST = |
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254 | ( (uint32_t) d_addr + n_bytes - 1 ) & ~ARM_CACHE_L1_DATA_LINE_MASK; |
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255 | |
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256 | ARM_CACHE_L1_ERRATA_764369_HANDLER(); |
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257 | |
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258 | for (; adx <= ADDR_LAST; adx += ARM_CACHE_L1_CPU_DATA_ALIGNMENT ) { |
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259 | /* Store the Data cache line */ |
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260 | arm_cp15_data_cache_clean_line( (void*)adx ); |
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261 | } |
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262 | /* Wait for L1 store to complete */ |
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263 | _ARM_Data_synchronization_barrier(); |
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264 | } |
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265 | } |
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266 | |
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267 | |
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268 | static inline void arm_cache_l1_invalidate_1_data_line( |
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269 | const void *d_addr ) |
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270 | { |
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271 | /* Invalidate the data cache line */ |
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272 | arm_cp15_data_cache_invalidate_line( d_addr ); |
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273 | |
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274 | /* Wait for L1 invalidate to complete */ |
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275 | _ARM_Data_synchronization_barrier(); |
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276 | } |
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277 | |
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278 | static inline void arm_cache_l1_freeze_data( void ) |
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279 | { |
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280 | /* To be implemented as needed, if supported by hardware at all */ |
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281 | } |
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282 | |
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283 | static inline void arm_cache_l1_unfreeze_data( void ) |
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284 | { |
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285 | /* To be implemented as needed, if supported by hardware at all */ |
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286 | } |
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287 | |
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288 | static inline void arm_cache_l1_invalidate_1_instruction_line( |
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289 | const void *i_addr ) |
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290 | { |
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291 | /* Invalidate the Instruction cache line */ |
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292 | arm_cp15_instruction_cache_invalidate_line( i_addr ); |
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293 | |
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294 | /* Wait for L1 invalidate to complete */ |
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295 | _ARM_Data_synchronization_barrier(); |
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296 | } |
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297 | |
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298 | static inline void arm_cache_l1_invalidate_data_range( |
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299 | const void *d_addr, |
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300 | size_t n_bytes |
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301 | ) |
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302 | { |
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303 | if ( n_bytes != 0 ) { |
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304 | uint32_t adx = (uint32_t) d_addr |
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305 | & ~ARM_CACHE_L1_DATA_LINE_MASK; |
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306 | const uint32_t end = |
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307 | ( adx + n_bytes ) & ~ARM_CACHE_L1_DATA_LINE_MASK; |
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308 | |
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309 | ARM_CACHE_L1_ERRATA_764369_HANDLER(); |
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310 | |
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311 | /* Back starting address up to start of a line and invalidate until end */ |
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312 | for (; |
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313 | adx < end; |
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314 | adx += ARM_CACHE_L1_CPU_DATA_ALIGNMENT ) { |
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315 | /* Invalidate the Instruction cache line */ |
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316 | arm_cp15_data_cache_invalidate_line( (void*)adx ); |
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317 | } |
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318 | /* Wait for L1 invalidate to complete */ |
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319 | _ARM_Data_synchronization_barrier(); |
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320 | } |
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321 | } |
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322 | |
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323 | static inline void arm_cache_l1_invalidate_instruction_range( |
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324 | const void *i_addr, |
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325 | size_t n_bytes |
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326 | ) |
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327 | { |
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328 | if ( n_bytes != 0 ) { |
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329 | uint32_t adx = (uint32_t) i_addr |
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330 | & ~ARM_CACHE_L1_INSTRUCTION_LINE_MASK; |
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331 | const uint32_t end = |
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332 | ( adx + n_bytes ) & ~ARM_CACHE_L1_INSTRUCTION_LINE_MASK; |
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333 | |
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334 | arm_cache_l1_select( ARM_CACHE_L1_CSS_ID_INSTRUCTION ); |
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335 | |
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336 | ARM_CACHE_L1_ERRATA_764369_HANDLER(); |
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337 | |
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338 | /* Back starting address up to start of a line and invalidate until end */ |
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339 | for (; |
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340 | adx < end; |
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341 | adx += ARM_CACHE_L1_CPU_INSTRUCTION_ALIGNMENT ) { |
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342 | /* Invalidate the Instruction cache line */ |
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343 | arm_cp15_instruction_cache_invalidate_line( (void*)adx ); |
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344 | } |
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345 | /* Wait for L1 invalidate to complete */ |
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346 | _ARM_Data_synchronization_barrier(); |
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347 | |
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348 | arm_cache_l1_select( ARM_CACHE_L1_CSS_ID_DATA ); |
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349 | } |
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350 | } |
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351 | |
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352 | static inline void arm_cache_l1_invalidate_entire_instruction( void ) |
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353 | { |
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354 | uint32_t ctrl = arm_cp15_get_control(); |
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355 | |
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356 | |
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357 | #ifdef RTEMS_SMP |
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358 | |
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359 | /* invalidate I-cache inner shareable */ |
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360 | arm_cp15_instruction_cache_inner_shareable_invalidate_all(); |
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361 | |
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362 | /* I+BTB cache invalidate */ |
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363 | arm_cp15_instruction_cache_invalidate(); |
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364 | #else /* RTEMS_SMP */ |
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365 | /* I+BTB cache invalidate */ |
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366 | arm_cp15_instruction_cache_invalidate(); |
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367 | #endif /* RTEMS_SMP */ |
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368 | |
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369 | if ( ( ctrl & ARM_CP15_CTRL_Z ) == 0 ) { |
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370 | arm_cp15_branch_predictor_inner_shareable_invalidate_all(); |
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371 | arm_cp15_branch_predictor_invalidate_all(); |
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372 | } |
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373 | } |
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374 | |
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375 | static inline void arm_cache_l1_freeze_instruction( void ) |
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376 | { |
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377 | /* To be implemented as needed, if supported by hardware at all */ |
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378 | } |
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379 | |
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380 | static inline void arm_cache_l1_unfreeze_instruction( void ) |
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381 | { |
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382 | /* To be implemented as needed, if supported by hardware at all */ |
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383 | } |
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384 | |
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385 | static inline void arm_cache_l1_enable_data( void ) |
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386 | { |
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387 | rtems_interrupt_level level; |
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388 | uint32_t ctrl; |
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389 | |
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390 | |
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391 | arm_cache_l1_select( ARM_CACHE_L1_CSS_ID_DATA ); |
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392 | |
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393 | assert( ARM_CACHE_L1_CPU_DATA_ALIGNMENT == arm_cp15_get_data_cache_line_size() ); |
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394 | |
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395 | rtems_interrupt_disable( level ); |
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396 | ctrl = arm_cp15_get_control(); |
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397 | rtems_interrupt_enable( level ); |
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398 | |
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399 | /* Only enable the cache if it is disabled */ |
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400 | if ( !( ctrl & ARM_CP15_CTRL_C ) ) { |
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401 | /* Clean and invalidate the Data cache */ |
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402 | arm_cache_l1_invalidate_entire_data(); |
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403 | |
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404 | /* Enable the Data cache */ |
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405 | ctrl |= ARM_CP15_CTRL_C; |
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406 | |
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407 | rtems_interrupt_disable( level ); |
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408 | arm_cp15_set_control( ctrl ); |
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409 | rtems_interrupt_enable( level ); |
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410 | } |
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411 | } |
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412 | |
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413 | static inline void arm_cache_l1_disable_data( void ) |
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414 | { |
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415 | rtems_interrupt_level level; |
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416 | |
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417 | |
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418 | /* Clean and invalidate the Data cache */ |
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419 | arm_cache_l1_flush_entire_data(); |
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420 | |
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421 | rtems_interrupt_disable( level ); |
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422 | |
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423 | /* Disable the Data cache */ |
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424 | arm_cp15_set_control( arm_cp15_get_control() & ~ARM_CP15_CTRL_C ); |
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425 | |
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426 | rtems_interrupt_enable( level ); |
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427 | } |
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428 | |
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429 | static inline void arm_cache_l1_disable_instruction( void ) |
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430 | { |
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431 | rtems_interrupt_level level; |
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432 | |
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433 | |
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434 | rtems_interrupt_disable( level ); |
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435 | |
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436 | /* Synchronize the processor */ |
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437 | _ARM_Data_synchronization_barrier(); |
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438 | |
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439 | /* Invalidate the Instruction cache */ |
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440 | arm_cache_l1_invalidate_entire_instruction(); |
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441 | |
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442 | /* Disable the Instruction cache */ |
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443 | arm_cp15_set_control( arm_cp15_get_control() & ~ARM_CP15_CTRL_I ); |
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444 | |
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445 | rtems_interrupt_enable( level ); |
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446 | } |
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447 | |
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448 | static inline void arm_cache_l1_enable_instruction( void ) |
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449 | { |
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450 | rtems_interrupt_level level; |
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451 | uint32_t ctrl; |
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452 | |
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453 | |
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454 | arm_cache_l1_select( ARM_CACHE_L1_CSS_ID_INSTRUCTION ); |
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455 | |
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456 | assert( ARM_CACHE_L1_CPU_INSTRUCTION_ALIGNMENT |
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457 | == arm_cp15_get_data_cache_line_size() ); |
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458 | |
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459 | rtems_interrupt_disable( level ); |
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460 | |
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461 | /* Enable Instruction cache only if it is disabled */ |
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462 | ctrl = arm_cp15_get_control(); |
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463 | |
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464 | if ( !( ctrl & ARM_CP15_CTRL_I ) ) { |
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465 | /* Invalidate the Instruction cache */ |
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466 | arm_cache_l1_invalidate_entire_instruction(); |
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467 | |
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468 | /* Enable the Instruction cache */ |
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469 | ctrl |= ARM_CP15_CTRL_I; |
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470 | |
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471 | arm_cp15_set_control( ctrl ); |
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472 | } |
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473 | |
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474 | rtems_interrupt_enable( level ); |
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475 | |
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476 | arm_cache_l1_select( ARM_CACHE_L1_CSS_ID_DATA ); |
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477 | } |
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478 | |
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479 | #ifdef __cplusplus |
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480 | } |
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481 | #endif /* __cplusplus */ |
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482 | |
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483 | #endif /* LIBBSP_ARM_SHARED_CACHE_L1_H */ |
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