1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup arm_shared |
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5 | * |
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6 | * @brief A9MPCORE_START Support |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved. |
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11 | * |
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12 | * embedded brains GmbH |
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13 | * Dornierstr. 4 |
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14 | * 82178 Puchheim |
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15 | * Germany |
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16 | * <info@embedded-brains.de> |
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17 | * |
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18 | * The license and distribution terms for this file may be |
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19 | * found in the file LICENSE in this distribution or at |
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20 | * http://www.rtems.org/license/LICENSE. |
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21 | */ |
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22 | |
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23 | #ifndef LIBBSP_ARM_SHARED_ARM_A9MPCORE_START_H |
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24 | #define LIBBSP_ARM_SHARED_ARM_A9MPCORE_START_H |
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25 | |
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26 | #include <rtems/score/smpimpl.h> |
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27 | |
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28 | #include <libcpu/arm-cp15.h> |
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29 | |
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30 | #include <bsp.h> |
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31 | #include <bsp/start.h> |
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32 | #include <bsp/arm-a9mpcore-regs.h> |
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33 | #include <bsp/arm-errata.h> |
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34 | |
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35 | #ifdef __cplusplus |
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36 | extern "C" { |
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37 | #endif /* __cplusplus */ |
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38 | |
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39 | BSP_START_TEXT_SECTION static inline uint32_t |
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40 | arm_cp15_get_control(void); |
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41 | |
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42 | BSP_START_TEXT_SECTION static inline void |
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43 | arm_cp15_set_control(uint32_t val); |
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44 | |
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45 | BSP_START_TEXT_SECTION static inline uint32_t |
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46 | arm_cp15_get_auxiliary_control(void); |
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47 | |
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48 | BSP_START_TEXT_SECTION static inline void |
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49 | arm_cp15_set_auxiliary_control(uint32_t val); |
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50 | |
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51 | BSP_START_TEXT_SECTION static inline void |
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52 | arm_cp15_set_vector_base_address(void *base); |
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53 | |
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54 | BSP_START_TEXT_SECTION static inline arm_a9mpcore_start_set_vector_base(void) |
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55 | { |
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56 | /* |
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57 | * Do not use bsp_vector_table_begin == 0, since this will get optimized away. |
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58 | */ |
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59 | if (bsp_vector_table_end != bsp_vector_table_size) { |
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60 | uint32_t ctrl; |
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61 | |
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62 | /* |
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63 | * For now we assume that every Cortex-A9 MPCore has the Security Extensions. |
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64 | * Later it might be necessary to evaluate the ID_PFR1 register. |
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65 | */ |
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66 | arm_cp15_set_vector_base_address(bsp_vector_table_begin); |
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67 | |
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68 | ctrl = arm_cp15_get_control(); |
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69 | ctrl &= ~ARM_CP15_CTRL_V; |
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70 | arm_cp15_set_control(ctrl); |
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71 | } |
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72 | } |
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73 | |
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74 | BSP_START_TEXT_SECTION static inline arm_a9mpcore_start_scu_invalidate( |
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75 | volatile a9mpcore_scu *scu, |
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76 | uint32_t cpu_id, |
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77 | uint32_t ways |
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78 | ) |
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79 | { |
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80 | scu->invss = (ways & 0xf) << ((cpu_id & 0x3) * 4); |
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81 | } |
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82 | |
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83 | BSP_START_TEXT_SECTION static void inline |
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84 | arm_a9mpcore_start_errata_764369_handler(volatile a9mpcore_scu *scu) |
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85 | { |
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86 | if (arm_errata_is_applicable_processor_errata_764369()) { |
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87 | scu->diagn_ctrl |= A9MPCORE_SCU_DIAGN_CTRL_MIGRATORY_BIT_DISABLE; |
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88 | } |
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89 | } |
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90 | |
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91 | BSP_START_TEXT_SECTION static inline |
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92 | arm_a9mpcore_start_scu_enable(volatile a9mpcore_scu *scu) |
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93 | { |
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94 | scu->ctrl |= A9MPCORE_SCU_CTRL_SCU_EN; |
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95 | arm_a9mpcore_start_errata_764369_handler(scu); |
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96 | } |
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97 | |
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98 | BSP_START_TEXT_SECTION static inline arm_a9mpcore_start_hook_0(void) |
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99 | { |
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100 | volatile a9mpcore_scu *scu = |
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101 | (volatile a9mpcore_scu *) BSP_ARM_A9MPCORE_SCU_BASE; |
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102 | uint32_t cpu_id; |
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103 | |
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104 | arm_a9mpcore_start_scu_enable(scu); |
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105 | |
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106 | #ifdef RTEMS_SMP |
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107 | /* Enable cache coherency support for this processor */ |
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108 | { |
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109 | uint32_t actlr = arm_cp15_get_auxiliary_control(); |
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110 | actlr |= ARM_CORTEX_A9_ACTL_SMP; |
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111 | arm_cp15_set_auxiliary_control(actlr); |
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112 | } |
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113 | #endif |
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114 | |
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115 | cpu_id = arm_cortex_a9_get_multiprocessor_cpu_id(); |
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116 | |
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117 | arm_a9mpcore_start_scu_invalidate(scu, cpu_id, 0xf); |
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118 | |
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119 | #ifdef RTEMS_SMP |
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120 | if (cpu_id != 0) { |
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121 | arm_a9mpcore_start_set_vector_base(); |
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122 | |
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123 | if (cpu_id < rtems_configuration_get_maximum_processors()) { |
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124 | uint32_t ctrl; |
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125 | |
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126 | arm_gic_irq_initialize_secondary_cpu(); |
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127 | |
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128 | ctrl = arm_cp15_start_setup_mmu_and_cache( |
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129 | 0, |
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130 | ARM_CP15_CTRL_AFE | ARM_CP15_CTRL_Z |
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131 | ); |
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132 | |
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133 | arm_cp15_set_domain_access_control( |
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134 | ARM_CP15_DAC_DOMAIN(ARM_MMU_DEFAULT_CLIENT_DOMAIN, ARM_CP15_DAC_CLIENT) |
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135 | ); |
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136 | |
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137 | /* FIXME: Sharing the translation table between processors is brittle */ |
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138 | arm_cp15_set_translation_table_base( |
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139 | (uint32_t *) bsp_translation_table_base |
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140 | ); |
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141 | |
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142 | ctrl |= ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M; |
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143 | arm_cp15_set_control(ctrl); |
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144 | |
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145 | _SMP_Start_multitasking_on_secondary_processor(); |
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146 | } else { |
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147 | /* FIXME: Shutdown processor */ |
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148 | while (1) { |
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149 | __asm__ volatile ("wfi"); |
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150 | } |
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151 | } |
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152 | } |
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153 | #endif |
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154 | } |
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155 | |
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156 | BSP_START_TEXT_SECTION static inline arm_a9mpcore_start_global_timer(void) |
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157 | { |
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158 | volatile a9mpcore_gt *gt = (volatile a9mpcore_gt *) BSP_ARM_A9MPCORE_GT_BASE; |
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159 | |
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160 | gt->ctrl = 0; |
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161 | gt->cntrlower = 0; |
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162 | gt->cntrupper = 0; |
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163 | gt->ctrl = A9MPCORE_GT_CTRL_TMR_EN; |
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164 | } |
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165 | |
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166 | BSP_START_TEXT_SECTION static inline arm_a9mpcore_start_hook_1(void) |
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167 | { |
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168 | arm_a9mpcore_start_global_timer(); |
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169 | arm_a9mpcore_start_set_vector_base(); |
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170 | } |
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171 | |
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172 | #ifdef __cplusplus |
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173 | } |
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174 | #endif /* __cplusplus */ |
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175 | |
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176 | #endif /* LIBBSP_ARM_SHARED_ARM_A9MPCORE_START_H */ |
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