source: rtems/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-start.h @ 0034629

4.115
Last change on this file since 0034629 was 0034629, checked in by Sebastian Huber <sebastian.huber@…>, on 05/07/14 at 07:23:23

bsps/arm: Declare return types

  • Property mode set to 100644
File size: 4.3 KB
Line 
1/**
2 *  @file
3 *
4 *  @ingroup arm_shared
5 *
6 *  @brief A9MPCORE_START Support
7 */
8
9/*
10 * Copyright (c) 2013-2014 embedded brains GmbH.  All rights reserved.
11 *
12 *  embedded brains GmbH
13 *  Dornierstr. 4
14 *  82178 Puchheim
15 *  Germany
16 *  <info@embedded-brains.de>
17 *
18 * The license and distribution terms for this file may be
19 * found in the file LICENSE in this distribution or at
20 * http://www.rtems.org/license/LICENSE.
21 */
22
23#ifndef LIBBSP_ARM_SHARED_ARM_A9MPCORE_START_H
24#define LIBBSP_ARM_SHARED_ARM_A9MPCORE_START_H
25
26#include <rtems/score/smpimpl.h>
27
28#include <libcpu/arm-cp15.h>
29
30#include <bsp.h>
31#include <bsp/start.h>
32#include <bsp/arm-a9mpcore-regs.h>
33#include <bsp/arm-errata.h>
34
35#ifdef __cplusplus
36extern "C" {
37#endif /* __cplusplus */
38
39BSP_START_TEXT_SECTION static inline uint32_t
40arm_cp15_get_control(void);
41
42BSP_START_TEXT_SECTION static inline void
43arm_cp15_set_control(uint32_t val);
44
45BSP_START_TEXT_SECTION static inline uint32_t
46arm_cp15_get_auxiliary_control(void);
47
48BSP_START_TEXT_SECTION static inline void
49arm_cp15_set_auxiliary_control(uint32_t val);
50
51BSP_START_TEXT_SECTION static inline void
52arm_cp15_set_vector_base_address(void *base);
53
54BSP_START_TEXT_SECTION static inline void
55arm_a9mpcore_start_set_vector_base(void)
56{
57  /*
58   * Do not use bsp_vector_table_begin == 0, since this will get optimized away.
59  */
60  if (bsp_vector_table_end != bsp_vector_table_size) {
61    uint32_t ctrl;
62
63    /*
64     * For now we assume that every Cortex-A9 MPCore has the Security Extensions.
65     * Later it might be necessary to evaluate the ID_PFR1 register.
66     */
67    arm_cp15_set_vector_base_address(bsp_vector_table_begin);
68
69    ctrl = arm_cp15_get_control();
70    ctrl &= ~ARM_CP15_CTRL_V;
71    arm_cp15_set_control(ctrl);
72  }
73}
74
75BSP_START_TEXT_SECTION static inline void arm_a9mpcore_start_scu_invalidate(
76  volatile a9mpcore_scu *scu,
77  uint32_t cpu_id,
78  uint32_t ways
79)
80{
81  scu->invss = (ways & 0xf) << ((cpu_id & 0x3) * 4);
82}
83
84BSP_START_TEXT_SECTION static inline void
85arm_a9mpcore_start_errata_764369_handler(volatile a9mpcore_scu *scu)
86{
87  if (arm_errata_is_applicable_processor_errata_764369()) {
88    scu->diagn_ctrl |= A9MPCORE_SCU_DIAGN_CTRL_MIGRATORY_BIT_DISABLE;
89  }
90}
91
92BSP_START_TEXT_SECTION static inline void
93arm_a9mpcore_start_scu_enable(volatile a9mpcore_scu *scu)
94{
95  scu->ctrl |= A9MPCORE_SCU_CTRL_SCU_EN;
96  arm_a9mpcore_start_errata_764369_handler(scu);
97}
98
99BSP_START_TEXT_SECTION static inline void arm_a9mpcore_start_hook_0(void)
100{
101  volatile a9mpcore_scu *scu =
102    (volatile a9mpcore_scu *) BSP_ARM_A9MPCORE_SCU_BASE;
103  uint32_t cpu_id;
104
105  arm_a9mpcore_start_scu_enable(scu);
106
107#ifdef RTEMS_SMP
108  /* Enable cache coherency support for this processor */
109  {
110    uint32_t actlr = arm_cp15_get_auxiliary_control();
111    actlr |= ARM_CORTEX_A9_ACTL_SMP;
112    arm_cp15_set_auxiliary_control(actlr);
113  }
114#endif
115
116  cpu_id = arm_cortex_a9_get_multiprocessor_cpu_id();
117
118  arm_a9mpcore_start_scu_invalidate(scu, cpu_id, 0xf);
119
120#ifdef RTEMS_SMP
121  if (cpu_id != 0) {
122    arm_a9mpcore_start_set_vector_base();
123
124    if (cpu_id < rtems_configuration_get_maximum_processors()) {
125      uint32_t ctrl;
126
127      arm_gic_irq_initialize_secondary_cpu();
128
129      ctrl = arm_cp15_start_setup_mmu_and_cache(
130        0,
131        ARM_CP15_CTRL_AFE | ARM_CP15_CTRL_Z
132      );
133
134      arm_cp15_set_domain_access_control(
135        ARM_CP15_DAC_DOMAIN(ARM_MMU_DEFAULT_CLIENT_DOMAIN, ARM_CP15_DAC_CLIENT)
136      );
137
138      /* FIXME: Sharing the translation table between processors is brittle */
139      arm_cp15_set_translation_table_base(
140        (uint32_t *) bsp_translation_table_base
141      );
142
143      ctrl |= ARM_CP15_CTRL_I | ARM_CP15_CTRL_C | ARM_CP15_CTRL_M;
144      arm_cp15_set_control(ctrl);
145
146      _SMP_Start_multitasking_on_secondary_processor();
147    } else {
148      /* FIXME: Shutdown processor */
149      while (1) {
150        __asm__ volatile ("wfi");
151      }
152    }
153  }
154#endif
155}
156
157BSP_START_TEXT_SECTION static inline void arm_a9mpcore_start_global_timer(void)
158{
159  volatile a9mpcore_gt *gt = (volatile a9mpcore_gt *) BSP_ARM_A9MPCORE_GT_BASE;
160
161  gt->ctrl = 0;
162  gt->cntrlower = 0;
163  gt->cntrupper = 0;
164  gt->ctrl = A9MPCORE_GT_CTRL_TMR_EN;
165}
166
167BSP_START_TEXT_SECTION static inline void arm_a9mpcore_start_hook_1(void)
168{
169  arm_a9mpcore_start_global_timer();
170  arm_a9mpcore_start_set_vector_base();
171}
172
173#ifdef __cplusplus
174}
175#endif /* __cplusplus */
176
177#endif /* LIBBSP_ARM_SHARED_ARM_A9MPCORE_START_H */
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