source: rtems/c/src/lib/libbsp/arm/shared/include/arm-a9mpcore-regs.h @ db42c079

4.11
Last change on this file since db42c079 was db42c079, checked in by Sebastian Huber <sebastian.huber@…>, on May 31, 2013 at 11:59:47 AM

bsps/arm: Add SMP support

  • Property mode set to 100644
File size: 2.8 KB
Line 
1/*
2 * Copyright (c) 2013 embedded brains GmbH.  All rights reserved.
3 *
4 *  embedded brains GmbH
5 *  Dornierstr. 4
6 *  82178 Puchheim
7 *  Germany
8 *  <info@embedded-brains.de>
9 *
10 * The license and distribution terms for this file may be
11 * found in the file LICENSE in this distribution or at
12 * http://www.rtems.com/license/LICENSE.
13 */
14
15#ifndef LIBBSP_ARM_SHARED_ARM_A9MPCORE_REGS_H
16#define LIBBSP_ARM_SHARED_ARM_A9MPCORE_REGS_H
17
18#include <bsp/utility.h>
19
20typedef struct {
21  uint32_t ctrl;
22#define A9MPCORE_SCU_CTRL_SCU_EN BSP_BIT32(0)
23#define A9MPCORE_SCU_CTRL_ADDR_FLT_EN BSP_BIT32(1)
24#define A9MPCORE_SCU_CTRL_RAM_PAR_EN BSP_BIT32(2)
25#define A9MPCORE_SCU_CTRL_SCU_SPEC_LINE_FILL_EN BSP_BIT32(3)
26#define A9MPCORE_SCU_CTRL_FORCE_PORT_0_EN BSP_BIT32(4)
27#define A9MPCORE_SCU_CTRL_SCU_STANDBY_EN BSP_BIT32(5)
28#define A9MPCORE_SCU_CTRL_IC_STANDBY_EN BSP_BIT32(6)
29  uint32_t cfg;
30#define A9MPCORE_SCU_CFG_CPU_COUNT(val) BSP_FLD32(val, 0, 1)
31#define A9MPCORE_SCU_CFG_CPU_COUNT_GET(reg) BSP_FLD32GET(reg, 0, 1)
32#define A9MPCORE_SCU_CFG_CPU_COUNT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 1)
33#define A9MPCORE_SCU_CFG_SMP_MODE(val) BSP_FLD32(val, 4, 7)
34#define A9MPCORE_SCU_CFG_SMP_MODE_GET(reg) BSP_FLD32GET(reg, 4, 7)
35#define A9MPCORE_SCU_CFG_SMP_MODE_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7)
36#define A9MPCORE_SCU_CFG_TAG_RAM_SIZE(val) BSP_FLD32(val, 8, 15)
37#define A9MPCORE_SCU_CFG_TAG_RAM_SIZE_GET(reg) BSP_FLD32GET(reg, 8, 15)
38#define A9MPCORE_SCU_CFG_TAG_RAM_SIZE_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
39  uint32_t pwrst;
40  uint32_t invss;
41  uint32_t reserved_10[12];
42  uint32_t fltstart;
43  uint32_t fltend;
44  uint32_t reserved_48[2];
45  uint32_t sac;
46  uint32_t snsac;
47} a9mpcore_scu;
48
49typedef struct {
50} a9mpcore_gic;
51
52typedef struct {
53  uint32_t cntr;
54  uint32_t reserved_04;
55  uint32_t ctrl;
56  uint32_t irqst;
57  uint32_t cmpval;
58  uint32_t reserved_14;
59  uint32_t autoinc;
60} a9mpcore_gt;
61
62typedef struct {
63  uint32_t load;
64  uint32_t cntr;
65  uint32_t ctrl;
66#define A9MPCORE_PT_CTRL_PRESCALER(val) BSP_FLD32(val, 8, 15)
67#define A9MPCORE_PT_CTRL_PRESCALER_GET(reg) BSP_FLD32GET(reg, 8, 15)
68#define A9MPCORE_PT_CTRL_PRESCALER_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15)
69#define A9MPCORE_PT_CTRL_IRQ_EN BSP_BIT32(2)
70#define A9MPCORE_PT_CTRL_AUTO_RLD BSP_BIT32(1)
71#define A9MPCORE_PT_CTRL_TMR_EN BSP_BIT32(0)
72  uint32_t irqst;
73#define A9MPCORE_PT_IRQST_EFLG BSP_BIT32(0)
74} a9mpcore_pt;
75
76typedef struct {
77  uint32_t load;
78  uint32_t cntr;
79  uint32_t ctrl;
80  uint32_t irqst;
81  uint32_t rstst;
82  uint32_t dis;
83} a9mpcore_pw;
84
85typedef struct {
86} a9mpcore_idist;
87
88typedef struct {
89  a9mpcore_scu scu;
90  uint32_t reserved_58[42];
91  a9mpcore_gic gic;
92  uint32_t reserved_100[64];
93  a9mpcore_gt gt;
94  uint32_t reserved_21c[249];
95  a9mpcore_pt pt;
96  uint32_t reserved_610[4];
97  a9mpcore_pw pw;
98  uint32_t reserved_638[626];
99  a9mpcore_idist idist;
100} a9mpcore;
101
102#endif /* LIBBSP_ARM_SHARED_ARM_A9MPCORE_REGS_H */
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