1 | /** |
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2 | * @file |
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3 | * |
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4 | * @ingroup arm_shared |
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5 | * |
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6 | * @brief ARM_A9MPCORE_REGS Support |
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7 | */ |
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8 | |
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9 | /* |
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10 | * Copyright (c) 2013 embedded brains GmbH. All rights reserved. |
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11 | * |
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12 | * embedded brains GmbH |
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13 | * Dornierstr. 4 |
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14 | * 82178 Puchheim |
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15 | * Germany |
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16 | * <info@embedded-brains.de> |
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17 | * |
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18 | * The license and distribution terms for this file may be |
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19 | * found in the file LICENSE in this distribution or at |
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20 | * http://www.rtems.org/license/LICENSE. |
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21 | */ |
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22 | |
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23 | #ifndef LIBBSP_ARM_SHARED_ARM_A9MPCORE_REGS_H |
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24 | #define LIBBSP_ARM_SHARED_ARM_A9MPCORE_REGS_H |
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25 | |
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26 | #include <bsp/utility.h> |
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27 | |
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28 | typedef struct { |
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29 | uint32_t ctrl; |
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30 | #define A9MPCORE_SCU_CTRL_SCU_EN BSP_BIT32(0) |
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31 | #define A9MPCORE_SCU_CTRL_ADDR_FLT_EN BSP_BIT32(1) |
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32 | #define A9MPCORE_SCU_CTRL_RAM_PAR_EN BSP_BIT32(2) |
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33 | #define A9MPCORE_SCU_CTRL_SCU_SPEC_LINE_FILL_EN BSP_BIT32(3) |
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34 | #define A9MPCORE_SCU_CTRL_FORCE_PORT_0_EN BSP_BIT32(4) |
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35 | #define A9MPCORE_SCU_CTRL_SCU_STANDBY_EN BSP_BIT32(5) |
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36 | #define A9MPCORE_SCU_CTRL_IC_STANDBY_EN BSP_BIT32(6) |
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37 | uint32_t cfg; |
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38 | #define A9MPCORE_SCU_CFG_CPU_COUNT(val) BSP_FLD32(val, 0, 1) |
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39 | #define A9MPCORE_SCU_CFG_CPU_COUNT_GET(reg) BSP_FLD32GET(reg, 0, 1) |
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40 | #define A9MPCORE_SCU_CFG_CPU_COUNT_SET(reg, val) BSP_FLD32SET(reg, val, 0, 1) |
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41 | #define A9MPCORE_SCU_CFG_SMP_MODE(val) BSP_FLD32(val, 4, 7) |
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42 | #define A9MPCORE_SCU_CFG_SMP_MODE_GET(reg) BSP_FLD32GET(reg, 4, 7) |
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43 | #define A9MPCORE_SCU_CFG_SMP_MODE_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7) |
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44 | #define A9MPCORE_SCU_CFG_TAG_RAM_SIZE(val) BSP_FLD32(val, 8, 15) |
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45 | #define A9MPCORE_SCU_CFG_TAG_RAM_SIZE_GET(reg) BSP_FLD32GET(reg, 8, 15) |
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46 | #define A9MPCORE_SCU_CFG_TAG_RAM_SIZE_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15) |
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47 | uint32_t pwrst; |
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48 | uint32_t invss; |
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49 | #define A9MPCORE_SCU_INVSS_CPU0(ways) BSP_FLD32(val, 0, 3) |
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50 | #define A9MPCORE_SCU_INVSS_CPU0_GET(reg) /* Write only register */ |
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51 | #define A9MPCORE_SCU_INVSS_CPU0_SET(reg, val) BSP_FLD32SET(reg, val, 0, 3) |
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52 | #define A9MPCORE_SCU_INVSS_CPU1(ways) BSP_FLD32(val, 4, 7) |
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53 | #define A9MPCORE_SCU_INVSS_CPU1_GET(reg) /* Write only register */ |
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54 | #define A9MPCORE_SCU_INVSS_CPU1_SET(reg, val) BSP_FLD32SET(reg, val, 4, 7) |
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55 | #define A9MPCORE_SCU_INVSS_CPU2(ways) BSP_FLD32(val, 8, 11) |
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56 | #define A9MPCORE_SCU_INVSS_CPU2_GET(reg) /* Write only register */ |
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57 | #define A9MPCORE_SCU_INVSS_CPU2_SET(reg, val) BSP_FLD32SET(reg, val, 8, 11) |
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58 | #define A9MPCORE_SCU_INVSS_CPU3(ways) BSP_FLD32(val, 12, 15) |
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59 | #define A9MPCORE_SCU_INVSS_CPU3_GET(reg) /* Write only register */ |
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60 | #define A9MPCORE_SCU_INVSS_CPU3_SET(reg, val) BSP_FLD32SET(reg, val, 12, 15) |
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61 | uint32_t reserved_09[8]; |
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62 | uint32_t diagn_ctrl; |
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63 | #define A9MPCORE_SCU_DIAGN_CTRL_MIGRATORY_BIT_DISABLE BSP_BIT32(0) |
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64 | uint32_t reserved_10[3]; |
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65 | uint32_t fltstart; |
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66 | uint32_t fltend; |
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67 | uint32_t reserved_48[2]; |
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68 | uint32_t sac; |
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69 | uint32_t snsac; |
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70 | } a9mpcore_scu; |
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71 | |
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72 | typedef struct { |
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73 | } a9mpcore_gic; |
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74 | |
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75 | typedef struct { |
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76 | uint32_t cntrlower; |
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77 | uint32_t cntrupper; |
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78 | #define A9MPCORE_GT_CTRL_PRESCALER(val) BSP_FLD32(val, 8, 15) |
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79 | #define A9MPCORE_GT_CTRL_PRESCALER_GET(reg) BSP_FLD32GET(reg, 8, 15) |
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80 | #define A9MPCORE_GT_CTRL_PRESCALER_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15) |
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81 | #define A9MPCORE_GT_CTRL_AUTOINC_EN BSP_BIT32(3) |
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82 | #define A9MPCORE_GT_CTRL_IRQ_EN BSP_BIT32(2) |
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83 | #define A9MPCORE_GT_CTRL_COMP_EN BSP_BIT32(1) |
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84 | #define A9MPCORE_GT_CTRL_TMR_EN BSP_BIT32(0) |
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85 | uint32_t ctrl; |
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86 | #define A9MPCORE_GT_IRQST_EFLG BSP_BIT32(0) |
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87 | uint32_t irqst; |
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88 | uint32_t cmpvallower; |
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89 | uint32_t cmpvalupper; |
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90 | uint32_t autoinc; |
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91 | } a9mpcore_gt; |
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92 | |
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93 | typedef struct { |
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94 | uint32_t load; |
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95 | uint32_t cntr; |
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96 | uint32_t ctrl; |
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97 | #define A9MPCORE_PT_CTRL_PRESCALER(val) BSP_FLD32(val, 8, 15) |
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98 | #define A9MPCORE_PT_CTRL_PRESCALER_GET(reg) BSP_FLD32GET(reg, 8, 15) |
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99 | #define A9MPCORE_PT_CTRL_PRESCALER_SET(reg, val) BSP_FLD32SET(reg, val, 8, 15) |
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100 | #define A9MPCORE_PT_CTRL_IRQ_EN BSP_BIT32(2) |
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101 | #define A9MPCORE_PT_CTRL_AUTO_RLD BSP_BIT32(1) |
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102 | #define A9MPCORE_PT_CTRL_TMR_EN BSP_BIT32(0) |
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103 | uint32_t irqst; |
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104 | #define A9MPCORE_PT_IRQST_EFLG BSP_BIT32(0) |
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105 | } a9mpcore_pt; |
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106 | |
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107 | typedef struct { |
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108 | uint32_t load; |
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109 | uint32_t cntr; |
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110 | uint32_t ctrl; |
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111 | uint32_t irqst; |
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112 | uint32_t rstst; |
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113 | uint32_t dis; |
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114 | } a9mpcore_pw; |
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115 | |
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116 | typedef struct { |
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117 | } a9mpcore_idist; |
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118 | |
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119 | typedef struct { |
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120 | a9mpcore_scu scu; |
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121 | uint32_t reserved_58[42]; |
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122 | a9mpcore_gic gic; |
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123 | uint32_t reserved_100[64]; |
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124 | a9mpcore_gt gt; |
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125 | uint32_t reserved_21c[249]; |
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126 | a9mpcore_pt pt; |
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127 | uint32_t reserved_610[4]; |
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128 | a9mpcore_pw pw; |
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129 | uint32_t reserved_638[626]; |
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130 | a9mpcore_idist idist; |
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131 | } a9mpcore; |
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132 | |
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133 | #endif /* LIBBSP_ARM_SHARED_ARM_A9MPCORE_REGS_H */ |
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