source: rtems/c/src/lib/libbsp/arm/shared/comm/uart.h @ 936c8d6

4.115
Last change on this file since 936c8d6 was 9b4422a2, checked in by Joel Sherrill <joel.sherrill@…>, on May 3, 2012 at 3:09:24 PM

Remove All CVS Id Strings Possible Using a Script

Script does what is expected and tries to do it as
smartly as possible.

+ remove occurrences of two blank comment lines

next to each other after Id string line removed.

+ remove entire comment blocks which only exited to

contain CVS Ids

+ If the processing left a blank line at the top of

a file, it was removed.

  • Property mode set to 100644
File size: 4.8 KB
Line 
1
2/*
3 * This software is Copyright (C) 1998 by T.sqware - all rights limited
4 * It is provided in to the public domain "as is", can be freely modified
5 * as far as this copyight notice is kept unchanged, but does not imply
6 * an endorsement by T.sqware of the product in which it is included.
7 *
8 * Copyright (c) Canon Research France SA.]
9 * Emmanuel Raguet, mailto:raguet@crf.canon.fr
10 *
11 *  The license and distribution terms for this file may be
12 *  found in the file LICENSE in this distribution or at
13 *  http://www.rtems.com/license/LICENSE.
14 */
15
16#ifndef _BSPUART_H
17#define _BSPUART_H
18
19void BSP_uart_init(int uart, int baud, int hwFlow);
20void BSP_uart_set_baud(int aurt, int baud);
21void BSP_uart_intr_ctrl(int uart, int cmd);
22void BSP_uart_throttle(int uart);
23void BSP_uart_unthrottle(int uart);
24int  BSP_uart_polled_status(int uart);
25void BSP_uart_polled_write(int uart, int val);
26int  BSP_uart_polled_read(int uart);
27void BSP_uart_termios_set(int uart, void *ttyp);
28int  BSP_uart_termios_write_com1(int minor, const char *buf, int len);
29int  BSP_uart_termios_write_com2(int minor, const char *buf, int len);
30void BSP_uart_termios_isr_com1();
31void BSP_uart_termios_isr_com2();
32void BSP_uart_dbgisr_com1(void);
33void BSP_uart_dbgisr_com2(void);
34extern unsigned BSP_poll_char_via_serial(void);
35extern void BSP_output_char_via_serial(int val);
36extern int BSPConsolePort;
37extern int BSPBaseBaud;
38/*
39 * Command values for BSP_uart_intr_ctrl(),
40 * values are strange in order to catch errors
41 * with assert
42 */
43#define BSP_UART_INTR_CTRL_DISABLE  (0)
44#define BSP_UART_INTR_CTRL_GDB      (0xaa) /* RX only */
45#define BSP_UART_INTR_CTRL_ENABLE   (0xbb) /* Normal operations */
46#define BSP_UART_INTR_CTRL_TERMIOS  (0xcc) /* RX & line status */
47
48/* Return values for uart_polled_status() */
49#define BSP_UART_STATUS_ERROR    (-1) /* No character */
50#define BSP_UART_STATUS_NOCHAR   (0)  /* No character */
51#define BSP_UART_STATUS_CHAR     (1)  /* Character present */
52#define BSP_UART_STATUS_BREAK    (2)  /* Break point is detected */
53
54/* PC UART definitions */
55#define BSP_UART_COM1            (0)
56#define BSP_UART_COM2            (1)
57
58/*
59 * Base IO for UART
60 */
61
62#define COM1_BASE_IO    0x3F8
63#define COM2_BASE_IO    0x2F8
64
65/*
66 * Offsets from base
67 */
68
69/* DLAB 0 */
70#define RBR  RSRBR   /* Rx Buffer Register (read) */
71#define THR  RSTHR   /* Tx Buffer Register (write) */
72#define IER  RSIER   /* Interrupt Enable Register */
73
74/* DLAB X */
75#define IIR  RSIIR   /* Interrupt Ident Register (read) */
76#define FCR  RSFCR   /* FIFO Control Register (write) */
77#define LCR  RSLCR   /* Line Control Register */
78#define LSR  RSLSR   /* Line Status Register */
79
80/* DLAB 1 */
81#define DLL  RSDLL   /* Divisor Latch, LSB */
82#define DLM  RSDLH   /* Divisor Latch, MSB */
83
84/* Uart control */
85#define CNT  RSCNT   /* General Control register */
86
87/*
88 * define bit for CNT
89 */
90#define UART_ENABLE     1
91#define PAD_ENABLE      2
92
93/*
94 * Interrupt source definition via IIR
95 */
96#define NO_MORE_INTR                            1
97#define TRANSMITTER_HODING_REGISTER_EMPTY       2
98#define RECEIVER_DATA_AVAIL                     4
99#define RECEIVER_ERROR                          6
100#define CHARACTER_TIMEOUT_INDICATION            12
101
102/*
103 * Bits definition of IER
104 */
105#define RECEIVE_ENABLE          0x1
106#define TRANSMIT_ENABLE         0x2
107#define RECEIVER_LINE_ST_ENABLE 0x4
108#define INTERRUPT_DISABLE       0x0
109
110/*
111 * Bits definition of the Line Status Register (LSR)
112 */
113#define DR      0x01    /* Data Ready */
114#define OE      0x02    /* Overrun Error */
115#define PE      0x04    /* Parity Error */
116#define FE      0x08    /* Framing Error */
117#define BI      0x10    /* Break Interrupt */
118#define THRE    0x20    /* Transmitter Holding Register Empty */
119#define TEMT    0x40    /* Transmitter Empty */
120#define ERFIFO  0x80    /* Error receive Fifo */
121
122/*
123 * Bits definition of the Line Control Register (LCR)
124 */
125#define CHR_5_BITS 0
126#define CHR_6_BITS 1
127#define CHR_7_BITS 2
128#define CHR_8_BITS 3
129
130#define WL      0x03    /* Word length mask */
131#define STB     0x04    /* 1 Stop Bit, otherwise 2 Stop Bits */
132#define PEN     0x08    /* Parity Enabled */
133#define EPS     0x10    /* Even Parity Select, otherwise Odd */
134#define SP      0x20    /* Stick Parity */
135#define BCB     0x40    /* Break Control Bit */
136#define DLAB    0x80    /* Enable Divisor Latch Access */
137
138/*
139 * Bits definition of the FIFO Control Register : WD16C552 or NS16550
140 */
141
142#define FIFO_CTRL   0x01    /* Set to 1 permit access to other bits */
143#define FIFO_EN     0x01    /* Enable the FIFO */
144#define XMIT_RESET  0x04    /* Transmit FIFO Reset */
145#define RCV_RESET   0x02    /* Receive FIFO Reset */
146#define FCR3        0x08    /* do not understand manual! */
147
148#define RECEIVE_FIFO_TRIGGER1   0x0  /* trigger recieve interrupt after 1 byte  */
149#define RECEIVE_FIFO_TRIGGER4   0x40 /* trigger recieve interrupt after 4 byte  */
150#define RECEIVE_FIFO_TRIGGER8   0x80 /* trigger recieve interrupt after 8 byte  */
151#define RECEIVE_FIFO_TRIGGER12  0xc0 /* trigger recieve interrupt after 14 byte */
152#define TRIG_LEVEL              0xc0 /* Mask for the trigger level              */
153
154#endif /* _BSPUART_H */
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