source: rtems/c/src/lib/libbsp/arm/shared/comm/uart.h @ 08330bf

4.104.114.84.95
Last change on this file since 08330bf was 08330bf, checked in by Joel Sherrill <joel.sherrill@…>, on Jul 27, 2000 at 1:04:11 AM

Port of RTEMS to the ARM processor family by Eric Valette
<valette@…> and Emmanuel Raguet <raguet@…>
of Canon CRF - Communication Dept. This port includes a
basic BSP that is sufficient to link hello world.

  • Property mode set to 100644
File size: 4.8 KB
Line 
1
2
3/*
4 * This software is Copyright (C) 1998 by T.sqware - all rights limited
5 * It is provided in to the public domain "as is", can be freely modified
6 * as far as this copyight notice is kept unchanged, but does not imply
7 * an endorsement by T.sqware of the product in which it is included.
8 *
9 * Copyright (c) Canon Research France SA.]
10 * Emmanuel Raguet, mailto:raguet@crf.canon.fr
11 *
12 *  The license and distribution terms for this file may be
13 *  found in found in the file LICENSE in this distribution or at
14 *  http://www.OARcorp.com/rtems/license.html.
15 */
16
17#ifndef _BSPUART_H
18#define _BSPUART_H
19
20void BSP_uart_init(int uart, int baud, int hwFlow);
21void BSP_uart_set_baud(int aurt, int baud);
22void BSP_uart_intr_ctrl(int uart, int cmd);
23void BSP_uart_throttle(int uart);
24void BSP_uart_unthrottle(int uart);
25int  BSP_uart_polled_status(int uart);
26void BSP_uart_polled_write(int uart, int val);
27int  BSP_uart_polled_read(int uart);
28void BSP_uart_termios_set(int uart, void *ttyp);
29int  BSP_uart_termios_write_com1(int minor, const char *buf, int len);
30int  BSP_uart_termios_write_com2(int minor, const char *buf, int len);
31void BSP_uart_termios_isr_com1();
32void BSP_uart_termios_isr_com2();
33void BSP_uart_dbgisr_com1(void);
34void BSP_uart_dbgisr_com2(void);
35extern unsigned BSP_poll_char_via_serial(void);
36extern void BSP_output_char_via_serial(int val);
37extern int BSPConsolePort;
38extern int BSPBaseBaud;
39/*
40 * Command values for BSP_uart_intr_ctrl(),
41 * values are strange in order to catch errors
42 * with assert
43 */
44#define BSP_UART_INTR_CTRL_DISABLE  (0)
45#define BSP_UART_INTR_CTRL_GDB      (0xaa) /* RX only */
46#define BSP_UART_INTR_CTRL_ENABLE   (0xbb) /* Normal operations */
47#define BSP_UART_INTR_CTRL_TERMIOS  (0xcc) /* RX & line status */
48
49/* Return values for uart_polled_status() */
50#define BSP_UART_STATUS_ERROR    (-1) /* No character */
51#define BSP_UART_STATUS_NOCHAR   (0)  /* No character */
52#define BSP_UART_STATUS_CHAR     (1)  /* Character present */
53#define BSP_UART_STATUS_BREAK    (2)  /* Break point is detected */
54
55/* PC UART definitions */
56#define BSP_UART_COM1            (0)
57#define BSP_UART_COM2            (1)
58
59/*
60 * Base IO for UART
61 */
62
63#define COM1_BASE_IO    0x3F8
64#define COM2_BASE_IO    0x2F8
65
66/*
67 * Offsets from base
68 */
69
70/* DLAB 0 */
71#define RBR  RSRBR   /* Rx Buffer Register (read) */
72#define THR  RSTHR   /* Tx Buffer Register (write) */
73#define IER  RSIER   /* Interrupt Enable Register */
74 
75/* DLAB X */
76#define IIR  RSIIR   /* Interrupt Ident Register (read) */
77#define FCR  RSFCR   /* FIFO Control Register (write) */
78#define LCR  RSLCR   /* Line Control Register */
79#define LSR  RSLSR   /* Line Status Register */
80 
81/* DLAB 1 */
82#define DLL  RSDLL   /* Divisor Latch, LSB */
83#define DLM  RSDLH   /* Divisor Latch, MSB */
84 
85/* Uart control */
86#define CNT  RSCNT   /* General Control register */
87 
88/*
89 * define bit for CNT
90 */
91#define UART_ENABLE     1
92#define PAD_ENABLE      2
93
94/*
95 * Interrupt source definition via IIR
96 */
97#define NO_MORE_INTR                            1
98#define TRANSMITTER_HODING_REGISTER_EMPTY       2
99#define RECEIVER_DATA_AVAIL                     4
100#define RECEIVER_ERROR                          6
101#define CHARACTER_TIMEOUT_INDICATION            12
102
103/*
104 * Bits definition of IER
105 */
106#define RECEIVE_ENABLE          0x1
107#define TRANSMIT_ENABLE         0x2
108#define RECEIVER_LINE_ST_ENABLE 0x4
109#define INTERRUPT_DISABLE       0x0
110
111/*
112 * Bits definition of the Line Status Register (LSR)
113 */
114#define DR      0x01    /* Data Ready */
115#define OE      0x02    /* Overrun Error */
116#define PE      0x04    /* Parity Error */
117#define FE      0x08    /* Framing Error */
118#define BI      0x10    /* Break Interrupt */
119#define THRE    0x20    /* Transmitter Holding Register Empty */
120#define TEMT    0x40    /* Transmitter Empty */
121#define ERFIFO  0x80    /* Error receive Fifo */
122
123/*
124 * Bits definition of the Line Control Register (LCR)
125 */
126#define CHR_5_BITS 0
127#define CHR_6_BITS 1
128#define CHR_7_BITS 2
129#define CHR_8_BITS 3
130
131#define WL      0x03    /* Word length mask */
132#define STB     0x04    /* 1 Stop Bit, otherwise 2 Stop Bits */
133#define PEN     0x08    /* Parity Enabled */
134#define EPS     0x10    /* Even Parity Select, otherwise Odd */
135#define SP      0x20    /* Stick Parity */
136#define BCB     0x40    /* Break Control Bit */
137#define DLAB    0x80    /* Enable Divisor Latch Access */
138
139/*
140 * Bits definition of the FIFO Control Register : WD16C552 or NS16550
141 */
142
143#define FIFO_CTRL   0x01    /* Set to 1 permit access to other bits */
144#define FIFO_EN     0x01    /* Enable the FIFO */
145#define XMIT_RESET  0x04    /* Transmit FIFO Reset */
146#define RCV_RESET   0x02    /* Receive FIFO Reset */
147#define FCR3        0x08    /* do not understand manual! */
148
149#define RECEIVE_FIFO_TRIGGER1   0x0  /* trigger recieve interrupt after 1 byte  */
150#define RECEIVE_FIFO_TRIGGER4   0x40 /* trigger recieve interrupt after 4 byte  */
151#define RECEIVE_FIFO_TRIGGER8   0x80 /* trigger recieve interrupt after 8 byte  */
152#define RECEIVE_FIFO_TRIGGER12  0xc0 /* trigger recieve interrupt after 14 byte */
153#define TRIG_LEVEL              0xc0 /* Mask for the trigger level              */
154
155#endif /* _BSPUART_H */
156
157
158
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