1 | /* |
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2 | * This software is Copyright (C) 1998 by T.sqware - all rights limited |
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3 | * It is provided in to the public domain "as is", can be freely modified |
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4 | * as far as this copyight notice is kept unchanged, but does not imply |
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5 | * an endorsement by T.sqware of the product in which it is included. |
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6 | * |
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7 | * COPYRIGHT (c) 2000 Canon Research France SA. |
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8 | * Emmanuel Raguet, mailto:raguet@crf.canon.fr |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in found in the file LICENSE in this distribution or at |
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12 | * http://www.OARcorp.com/rtems/license.html. |
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13 | * |
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14 | * $Id$ |
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15 | */ |
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16 | |
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17 | #include <bsp.h> |
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18 | #include <irq.h> |
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19 | #include <registers.h> |
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20 | #include <uart.h> |
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21 | #include <rtems/libio.h> |
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22 | #include <assert.h> |
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23 | |
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24 | /* |
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25 | * Basic 16552 driver |
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26 | */ |
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27 | |
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28 | struct uart_data |
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29 | { |
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30 | int hwFlow; |
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31 | int baud; |
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32 | }; |
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33 | |
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34 | static struct uart_data uart_data[2]; |
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35 | |
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36 | /* |
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37 | * Macros to read/wirte register of uart, if configuration is |
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38 | * different just rewrite these macros |
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39 | */ |
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40 | |
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41 | static inline unsigned char |
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42 | uread(int uart, unsigned int reg) |
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43 | { |
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44 | register unsigned char val; |
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45 | |
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46 | val = Regs[reg]; |
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47 | |
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48 | return val; |
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49 | } |
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50 | |
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51 | static inline void |
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52 | uwrite(int uart, int reg, unsigned int val) |
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53 | { |
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54 | |
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55 | Regs[reg] = val; |
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56 | |
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57 | } |
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58 | |
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59 | #ifdef UARTDEBUG |
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60 | static void |
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61 | uartError(int uart) |
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62 | { |
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63 | unsigned char uartStatus, dummy; |
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64 | |
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65 | uartStatus = uread(uart, LSR); |
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66 | dummy = uread(uart, RBR); |
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67 | |
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68 | if (uartStatus & OE) |
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69 | printk("********* Over run Error **********\n"); |
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70 | if (uartStatus & PE) |
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71 | printk("********* Parity Error **********\n"); |
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72 | if (uartStatus & FE) |
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73 | printk("********* Framing Error **********\n"); |
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74 | if (uartStatus & BI) |
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75 | printk("********* Parity Error **********\n"); |
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76 | if (uartStatus & ERFIFO) |
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77 | printk("********* Error receive Fifo **********\n"); |
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78 | |
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79 | } |
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80 | #else |
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81 | inline void uartError(int uart) |
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82 | { |
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83 | unsigned char uartStatus; |
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84 | |
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85 | uartStatus = uread(uart, LSR); |
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86 | uartStatus = uread(uart, RBR); |
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87 | } |
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88 | #endif |
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89 | |
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90 | /* |
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91 | * Uart initialization, it is hardcoded to 8 bit, no parity, |
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92 | * one stop bit, FIFO, things to be changed |
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93 | * are baud rate and nad hw flow control, |
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94 | * and longest rx fifo setting |
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95 | */ |
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96 | void |
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97 | BSP_uart_init(int uart, int baud, int hwFlow) |
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98 | { |
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99 | unsigned char tmp; |
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100 | |
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101 | /* Sanity check */ |
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102 | assert(uart == BSP_UART_COM1 || uart == BSP_UART_COM2); |
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103 | |
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104 | switch(baud) |
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105 | { |
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106 | case 50: |
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107 | case 75: |
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108 | case 110: |
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109 | case 134: |
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110 | case 300: |
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111 | case 600: |
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112 | case 1200: |
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113 | case 2400: |
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114 | case 9600: |
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115 | case 19200: |
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116 | case 38400: |
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117 | case 57600: |
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118 | case 115200: |
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119 | break; |
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120 | default: |
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121 | assert(0); |
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122 | return; |
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123 | } |
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124 | |
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125 | /* Enable UART block */ |
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126 | uwrite(uart, CNT, UART_ENABLE | PAD_ENABLE); |
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127 | |
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128 | /* Set DLAB bit to 1 */ |
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129 | uwrite(uart, LCR, DLAB); |
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130 | |
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131 | /* Set baud rate */ |
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132 | uwrite(uart, DLL, (BSPBaseBaud/baud) & 0xff); |
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133 | uwrite(uart, DLM, ((BSPBaseBaud/baud) >> 8) & 0xff); |
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134 | |
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135 | /* 8-bit, no parity , 1 stop */ |
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136 | uwrite(uart, LCR, CHR_8_BITS); |
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137 | |
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138 | /* Enable FIFO */ |
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139 | uwrite(uart, FCR, FIFO_EN | XMIT_RESET | RCV_RESET | RECEIVE_FIFO_TRIGGER12); |
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140 | |
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141 | /* Disable Interrupts */ |
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142 | uwrite(uart, IER, 0); |
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143 | |
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144 | /* Read status to clear them */ |
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145 | tmp = uread(uart, LSR); |
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146 | tmp = uread(uart, RBR); |
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147 | |
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148 | /* Remember state */ |
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149 | uart_data[uart].hwFlow = hwFlow; |
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150 | uart_data[uart].baud = baud; |
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151 | return; |
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152 | } |
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153 | |
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154 | /* |
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155 | * Set baud |
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156 | */ |
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157 | void |
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158 | BSP_uart_set_baud(int uart, int baud) |
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159 | { |
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160 | unsigned char ier; |
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161 | |
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162 | /* Sanity check */ |
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163 | assert(uart == BSP_UART_COM1 || uart == BSP_UART_COM2); |
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164 | |
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165 | /* |
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166 | * This function may be called whenever TERMIOS parameters |
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167 | * are changed, so we have to make sure that baud change is |
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168 | * indeed required |
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169 | */ |
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170 | |
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171 | if(baud == uart_data[uart].baud) |
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172 | { |
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173 | return; |
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174 | } |
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175 | |
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176 | ier = uread(uart, IER); |
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177 | |
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178 | BSP_uart_init(uart, baud, uart_data[uart].hwFlow); |
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179 | |
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180 | uwrite(uart, IER, ier); |
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181 | |
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182 | return; |
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183 | } |
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184 | |
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185 | /* |
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186 | * Enable/disable interrupts |
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187 | */ |
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188 | void |
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189 | BSP_uart_intr_ctrl(int uart, int cmd) |
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190 | { |
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191 | |
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192 | assert(uart == BSP_UART_COM1 || uart == BSP_UART_COM2); |
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193 | |
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194 | switch(cmd) |
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195 | { |
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196 | case BSP_UART_INTR_CTRL_DISABLE: |
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197 | uwrite(uart, IER, INTERRUPT_DISABLE); |
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198 | break; |
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199 | case BSP_UART_INTR_CTRL_ENABLE: |
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200 | uwrite(uart, IER, |
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201 | (RECEIVE_ENABLE | |
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202 | TRANSMIT_ENABLE | |
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203 | RECEIVER_LINE_ST_ENABLE |
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204 | ) |
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205 | ); |
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206 | break; |
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207 | case BSP_UART_INTR_CTRL_TERMIOS: |
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208 | uwrite(uart, IER, |
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209 | (RECEIVE_ENABLE | |
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210 | RECEIVER_LINE_ST_ENABLE |
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211 | ) |
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212 | ); |
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213 | break; |
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214 | case BSP_UART_INTR_CTRL_GDB: |
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215 | uwrite(uart, IER, RECEIVE_ENABLE); |
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216 | break; |
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217 | default: |
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218 | assert(0); |
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219 | break; |
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220 | } |
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221 | |
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222 | return; |
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223 | } |
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224 | |
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225 | |
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226 | /* |
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227 | * Status function, -1 if error |
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228 | * detected, 0 if no received chars available, |
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229 | * 1 if received char available, 2 if break |
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230 | * is detected, it will eat break and error |
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231 | * chars. It ignores overruns - we cannot do |
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232 | * anything about - it execpt count statistics |
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233 | * and we are not counting it. |
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234 | */ |
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235 | int |
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236 | BSP_uart_polled_status(int uart) |
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237 | { |
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238 | unsigned char val; |
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239 | |
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240 | assert(uart == BSP_UART_COM1 || uart == BSP_UART_COM2); |
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241 | |
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242 | val = uread(uart, LSR); |
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243 | |
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244 | if(val & BI) |
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245 | { |
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246 | /* BREAK found, eat character */ |
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247 | uread(uart, RBR); |
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248 | return BSP_UART_STATUS_BREAK; |
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249 | } |
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250 | |
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251 | if((val & (DR | OE | FE)) == 1) |
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252 | { |
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253 | /* No error, character present */ |
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254 | return BSP_UART_STATUS_CHAR; |
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255 | } |
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256 | |
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257 | if((val & (DR | OE | FE)) == 0) |
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258 | { |
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259 | /* Nothing */ |
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260 | return BSP_UART_STATUS_NOCHAR; |
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261 | } |
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262 | |
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263 | /* |
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264 | * Framing or parity error |
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265 | * eat character |
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266 | */ |
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267 | uread(uart, RBR); |
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268 | |
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269 | return BSP_UART_STATUS_ERROR; |
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270 | } |
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271 | |
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272 | |
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273 | /* |
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274 | * Polled mode write function |
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275 | */ |
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276 | void |
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277 | BSP_uart_polled_write(int uart, int val) |
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278 | { |
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279 | unsigned char val1; |
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280 | |
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281 | /* Sanity check */ |
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282 | assert(uart == BSP_UART_COM1 || uart == BSP_UART_COM2); |
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283 | |
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284 | for(;;) |
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285 | { |
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286 | if((val1=uread(uart, LSR)) & THRE) |
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287 | { |
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288 | break; |
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289 | } |
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290 | } |
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291 | |
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292 | uwrite(uart, THR, val & 0xff); |
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293 | |
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294 | return; |
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295 | } |
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296 | |
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297 | void |
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298 | BSP_output_char_via_serial(int val) |
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299 | { |
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300 | BSP_uart_polled_write(BSPConsolePort, val); |
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301 | if (val == '\n') BSP_uart_polled_write(BSPConsolePort,'\r'); |
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302 | } |
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303 | |
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304 | /* |
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305 | * Polled mode read function |
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306 | */ |
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307 | int |
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308 | BSP_uart_polled_read(int uart) |
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309 | { |
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310 | unsigned char val; |
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311 | |
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312 | assert(uart == BSP_UART_COM1 || uart == BSP_UART_COM2); |
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313 | |
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314 | for(;;) |
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315 | { |
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316 | if(uread(uart, LSR) & DR) |
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317 | { |
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318 | break; |
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319 | } |
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320 | } |
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321 | |
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322 | val = uread(uart, RBR); |
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323 | |
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324 | return (int)(val & 0xff); |
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325 | } |
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326 | |
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327 | unsigned |
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328 | BSP_poll_char_via_serial() |
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329 | { |
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330 | return BSP_uart_polled_read(BSPConsolePort); |
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331 | } |
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332 | |
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333 | |
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334 | /* ================ Termios support =================*/ |
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335 | |
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336 | static volatile int termios_stopped_com1 = 0; |
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337 | static volatile int termios_tx_active_com1 = 0; |
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338 | static void* termios_ttyp_com1 = NULL; |
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339 | static char termios_tx_hold_com1 = 0; |
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340 | static volatile char termios_tx_hold_valid_com1 = 0; |
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341 | |
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342 | static volatile int termios_stopped_com2 = 0; |
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343 | static volatile int termios_tx_active_com2 = 0; |
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344 | static void* termios_ttyp_com2 = NULL; |
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345 | static char termios_tx_hold_com2 = 0; |
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346 | static volatile char termios_tx_hold_valid_com2 = 0; |
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347 | |
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348 | /* |
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349 | * Set channel parameters |
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350 | */ |
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351 | void |
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352 | BSP_uart_termios_set(int uart, void *ttyp) |
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353 | { |
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354 | assert(uart == BSP_UART_COM1 || uart == BSP_UART_COM2); |
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355 | |
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356 | if(uart == BSP_UART_COM1) |
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357 | { |
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358 | termios_stopped_com1 = 0; |
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359 | termios_tx_active_com1 = 0; |
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360 | termios_ttyp_com1 = ttyp; |
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361 | termios_tx_hold_com1 = 0; |
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362 | termios_tx_hold_valid_com1 = 0; |
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363 | } |
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364 | else |
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365 | { |
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366 | termios_stopped_com2 = 0; |
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367 | termios_tx_active_com2 = 0; |
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368 | termios_ttyp_com2 = ttyp; |
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369 | termios_tx_hold_com2 = 0; |
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370 | termios_tx_hold_valid_com2 = 0; |
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371 | } |
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372 | |
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373 | return; |
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374 | } |
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375 | |
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376 | int |
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377 | BSP_uart_termios_write_com1(int minor, const char *buf, int len) |
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378 | { |
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379 | assert(buf != NULL); |
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380 | |
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381 | if(len <= 0) |
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382 | { |
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383 | return 0; |
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384 | } |
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385 | |
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386 | /* If there TX buffer is busy - something is royally screwed up */ |
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387 | assert((uread(BSP_UART_COM1, LSR) & THRE) != 0); |
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388 | |
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389 | if(termios_stopped_com1) |
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390 | { |
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391 | /* CTS low */ |
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392 | termios_tx_hold_com1 = *buf; |
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393 | termios_tx_hold_valid_com1 = 1; |
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394 | return 0; |
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395 | } |
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396 | |
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397 | /* Write character */ |
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398 | uwrite(BSP_UART_COM1, THR, *buf & 0xff); |
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399 | |
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400 | /* Enable interrupts if necessary */ |
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401 | if(!termios_tx_active_com1) |
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402 | { |
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403 | termios_tx_active_com1 = 1; |
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404 | uwrite(BSP_UART_COM1, IER, |
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405 | (RECEIVE_ENABLE | |
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406 | TRANSMIT_ENABLE | |
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407 | RECEIVER_LINE_ST_ENABLE |
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408 | ) |
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409 | ); |
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410 | } |
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411 | |
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412 | return 0; |
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413 | } |
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414 | |
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415 | int |
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416 | BSP_uart_termios_write_com2(int minor, const char *buf, int len) |
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417 | { |
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418 | assert(buf != NULL); |
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419 | |
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420 | if(len <= 0) |
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421 | { |
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422 | return 0; |
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423 | } |
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424 | |
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425 | |
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426 | /* If there TX buffer is busy - something is royally screwed up */ |
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427 | assert((uread(BSP_UART_COM2, LSR) & THRE) != 0); |
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428 | |
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429 | if(termios_stopped_com2) |
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430 | { |
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431 | /* CTS low */ |
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432 | termios_tx_hold_com2 = *buf; |
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433 | termios_tx_hold_valid_com2 = 1; |
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434 | return 0; |
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435 | } |
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436 | |
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437 | /* Write character */ |
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438 | |
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439 | uwrite(BSP_UART_COM2, THR, *buf & 0xff); |
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440 | |
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441 | /* Enable interrupts if necessary */ |
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442 | if(!termios_tx_active_com2) |
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443 | { |
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444 | termios_tx_active_com2 = 1; |
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445 | uwrite(BSP_UART_COM2, IER, |
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446 | (RECEIVE_ENABLE | |
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447 | TRANSMIT_ENABLE | |
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448 | RECEIVER_LINE_ST_ENABLE |
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449 | ) |
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450 | ); |
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451 | } |
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452 | |
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453 | return 0; |
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454 | } |
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455 | |
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456 | |
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457 | void |
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458 | BSP_uart_termios_isr_com1(void) |
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459 | { |
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460 | unsigned char buf[40]; |
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461 | int off, ret, vect; |
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462 | |
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463 | off = 0; |
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464 | |
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465 | for(;;) |
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466 | { |
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467 | vect = uread(BSP_UART_COM1, IIR) & 0xf; |
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468 | |
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469 | switch(vect) |
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470 | { |
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471 | case NO_MORE_INTR : |
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472 | /* No more interrupts */ |
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473 | if(off != 0) |
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474 | { |
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475 | /* Update rx buffer */ |
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476 | rtems_termios_enqueue_raw_characters(termios_ttyp_com1, |
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477 | (char *)buf, |
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478 | off); |
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479 | } |
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480 | return; |
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481 | case TRANSMITTER_HODING_REGISTER_EMPTY : |
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482 | /* |
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483 | * TX holding empty: we have to disable these interrupts |
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484 | * if there is nothing more to send. |
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485 | */ |
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486 | |
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487 | ret = rtems_termios_dequeue_characters(termios_ttyp_com1, 1); |
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488 | |
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489 | /* If nothing else to send disable interrupts */ |
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490 | if(ret == 0) |
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491 | { |
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492 | uwrite(BSP_UART_COM1, IER, |
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493 | (RECEIVE_ENABLE | |
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494 | RECEIVER_LINE_ST_ENABLE |
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495 | ) |
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496 | ); |
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497 | termios_tx_active_com1 = 0; |
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498 | } |
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499 | break; |
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500 | case RECEIVER_DATA_AVAIL : |
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501 | case CHARACTER_TIMEOUT_INDICATION: |
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502 | /* RX data ready */ |
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503 | assert(off < sizeof(buf)); |
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504 | buf[off++] = uread(BSP_UART_COM1, RBR); |
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505 | break; |
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506 | case RECEIVER_ERROR: |
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507 | /* RX error: eat character */ |
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508 | uartError(BSP_UART_COM1); |
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509 | break; |
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510 | default: |
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511 | /* Should not happen */ |
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512 | assert(0); |
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513 | return; |
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514 | } |
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515 | } |
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516 | } |
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517 | |
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518 | void |
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519 | BSP_uart_termios_isr_com2() |
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520 | { |
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521 | unsigned char buf[40]; |
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522 | int off, ret, vect; |
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523 | |
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524 | off = 0; |
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525 | |
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526 | for(;;) |
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527 | { |
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528 | vect = uread(BSP_UART_COM2, IIR) & 0xf; |
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529 | |
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530 | switch(vect) |
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531 | { |
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532 | case NO_MORE_INTR : |
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533 | /* No more interrupts */ |
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534 | if(off != 0) |
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535 | { |
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536 | /* Update rx buffer */ |
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537 | rtems_termios_enqueue_raw_characters(termios_ttyp_com2, |
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538 | (char *)buf, |
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539 | off); |
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540 | } |
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541 | return; |
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542 | case TRANSMITTER_HODING_REGISTER_EMPTY : |
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543 | /* |
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544 | * TX holding empty: we have to disable these interrupts |
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545 | * if there is nothing more to send. |
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546 | */ |
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547 | |
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548 | ret = rtems_termios_dequeue_characters(termios_ttyp_com2, 1); |
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549 | |
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550 | /* If nothing else to send disable interrupts */ |
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551 | if(ret == 0) |
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552 | { |
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553 | uwrite(BSP_UART_COM2, IER, |
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554 | (RECEIVE_ENABLE | |
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555 | RECEIVER_LINE_ST_ENABLE |
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556 | ) |
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557 | ); |
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558 | termios_tx_active_com2 = 0; |
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559 | } |
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560 | break; |
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561 | case RECEIVER_DATA_AVAIL : |
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562 | case CHARACTER_TIMEOUT_INDICATION: |
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563 | /* RX data ready */ |
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564 | assert(off < sizeof(buf)); |
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565 | buf[off++] = uread(BSP_UART_COM2, RBR); |
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566 | break; |
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567 | case RECEIVER_ERROR: |
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568 | /* RX error: eat character */ |
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569 | uartError(BSP_UART_COM2); |
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570 | break; |
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571 | default: |
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572 | /* Should not happen */ |
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573 | assert(0); |
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574 | return; |
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575 | } |
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576 | } |
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577 | } |
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