[08330bf] | 1 | /* |
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| 2 | * This software is Copyright (C) 1998 by T.sqware - all rights limited |
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| 3 | * It is provided in to the public domain "as is", can be freely modified |
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| 4 | * as far as this copyight notice is kept unchanged, but does not imply |
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| 5 | * an endorsement by T.sqware of the product in which it is included. |
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| 6 | * |
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| 7 | * COPYRIGHT (c) 2000 Canon Research France SA. |
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| 8 | * Emmanuel Raguet, mailto:raguet@crf.canon.fr |
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| 9 | * |
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| 10 | * The license and distribution terms for this file may be |
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[15ca4e7] | 11 | * found in the file LICENSE in this distribution or at |
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[85aa609] | 12 | * http://www.rtems.com/license/LICENSE. |
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[08330bf] | 13 | */ |
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| 14 | |
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| 15 | #include <bsp.h> |
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| 16 | #include <irq.h> |
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| 17 | #include <registers.h> |
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| 18 | #include <uart.h> |
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| 19 | #include <rtems/libio.h> |
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| 20 | #include <assert.h> |
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| 21 | |
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| 22 | /* |
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| 23 | * Basic 16552 driver |
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| 24 | */ |
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| 25 | |
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| 26 | struct uart_data |
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| 27 | { |
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| 28 | int hwFlow; |
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| 29 | int baud; |
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| 30 | }; |
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| 31 | |
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| 32 | static struct uart_data uart_data[2]; |
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| 33 | |
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[6128a4a] | 34 | /* |
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[08330bf] | 35 | * Macros to read/wirte register of uart, if configuration is |
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| 36 | * different just rewrite these macros |
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[6128a4a] | 37 | */ |
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[08330bf] | 38 | |
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| 39 | static inline unsigned char |
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| 40 | uread(int uart, unsigned int reg) |
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| 41 | { |
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| 42 | register unsigned char val; |
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| 43 | |
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| 44 | val = Regs[reg]; |
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[6128a4a] | 45 | |
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[08330bf] | 46 | return val; |
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| 47 | } |
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| 48 | |
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[6128a4a] | 49 | static inline void |
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[08330bf] | 50 | uwrite(int uart, int reg, unsigned int val) |
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| 51 | { |
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| 52 | |
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| 53 | Regs[reg] = val; |
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| 54 | |
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| 55 | } |
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| 56 | |
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| 57 | #ifdef UARTDEBUG |
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| 58 | static void |
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| 59 | uartError(int uart) |
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| 60 | { |
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| 61 | unsigned char uartStatus, dummy; |
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| 62 | |
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| 63 | uartStatus = uread(uart, LSR); |
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| 64 | dummy = uread(uart, RBR); |
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| 65 | |
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| 66 | if (uartStatus & OE) |
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| 67 | printk("********* Over run Error **********\n"); |
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| 68 | if (uartStatus & PE) |
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| 69 | printk("********* Parity Error **********\n"); |
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| 70 | if (uartStatus & FE) |
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| 71 | printk("********* Framing Error **********\n"); |
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| 72 | if (uartStatus & BI) |
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| 73 | printk("********* Parity Error **********\n"); |
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| 74 | if (uartStatus & ERFIFO) |
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| 75 | printk("********* Error receive Fifo **********\n"); |
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| 76 | |
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| 77 | } |
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| 78 | #else |
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| 79 | inline void uartError(int uart) |
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| 80 | { |
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| 81 | unsigned char uartStatus; |
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[6128a4a] | 82 | |
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[08330bf] | 83 | uartStatus = uread(uart, LSR); |
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| 84 | uartStatus = uread(uart, RBR); |
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| 85 | } |
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| 86 | #endif |
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| 87 | |
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[6128a4a] | 88 | /* |
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[08330bf] | 89 | * Uart initialization, it is hardcoded to 8 bit, no parity, |
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| 90 | * one stop bit, FIFO, things to be changed |
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| 91 | * are baud rate and nad hw flow control, |
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| 92 | * and longest rx fifo setting |
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| 93 | */ |
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| 94 | void |
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| 95 | BSP_uart_init(int uart, int baud, int hwFlow) |
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| 96 | { |
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| 97 | unsigned char tmp; |
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[6128a4a] | 98 | |
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[08330bf] | 99 | /* Sanity check */ |
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| 100 | assert(uart == BSP_UART_COM1 || uart == BSP_UART_COM2); |
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[6128a4a] | 101 | |
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[08330bf] | 102 | switch(baud) |
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| 103 | { |
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| 104 | case 50: |
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| 105 | case 75: |
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| 106 | case 110: |
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| 107 | case 134: |
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| 108 | case 300: |
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| 109 | case 600: |
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| 110 | case 1200: |
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| 111 | case 2400: |
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| 112 | case 9600: |
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| 113 | case 19200: |
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| 114 | case 38400: |
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| 115 | case 57600: |
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| 116 | case 115200: |
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| 117 | break; |
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| 118 | default: |
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| 119 | assert(0); |
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| 120 | return; |
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| 121 | } |
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[6128a4a] | 122 | |
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[08330bf] | 123 | /* Enable UART block */ |
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| 124 | uwrite(uart, CNT, UART_ENABLE | PAD_ENABLE); |
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| 125 | |
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| 126 | /* Set DLAB bit to 1 */ |
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| 127 | uwrite(uart, LCR, DLAB); |
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[6128a4a] | 128 | |
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[08330bf] | 129 | /* Set baud rate */ |
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[6128a4a] | 130 | uwrite(uart, DLL, (BSPBaseBaud/baud) & 0xff); |
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| 131 | uwrite(uart, DLM, ((BSPBaseBaud/baud) >> 8) & 0xff); |
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[08330bf] | 132 | |
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| 133 | /* 8-bit, no parity , 1 stop */ |
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| 134 | uwrite(uart, LCR, CHR_8_BITS); |
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[6128a4a] | 135 | |
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[08330bf] | 136 | /* Enable FIFO */ |
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| 137 | uwrite(uart, FCR, FIFO_EN | XMIT_RESET | RCV_RESET | RECEIVE_FIFO_TRIGGER12); |
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| 138 | |
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| 139 | /* Disable Interrupts */ |
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| 140 | uwrite(uart, IER, 0); |
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| 141 | |
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| 142 | /* Read status to clear them */ |
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| 143 | tmp = uread(uart, LSR); |
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| 144 | tmp = uread(uart, RBR); |
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| 145 | |
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| 146 | /* Remember state */ |
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| 147 | uart_data[uart].hwFlow = hwFlow; |
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| 148 | uart_data[uart].baud = baud; |
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| 149 | return; |
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| 150 | } |
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| 151 | |
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[6128a4a] | 152 | /* |
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[08330bf] | 153 | * Set baud |
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| 154 | */ |
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| 155 | void |
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| 156 | BSP_uart_set_baud(int uart, int baud) |
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| 157 | { |
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| 158 | unsigned char ier; |
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| 159 | |
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| 160 | /* Sanity check */ |
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| 161 | assert(uart == BSP_UART_COM1 || uart == BSP_UART_COM2); |
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[6128a4a] | 162 | |
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| 163 | /* |
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[08330bf] | 164 | * This function may be called whenever TERMIOS parameters |
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[6128a4a] | 165 | * are changed, so we have to make sure that baud change is |
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[08330bf] | 166 | * indeed required |
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| 167 | */ |
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| 168 | |
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| 169 | if(baud == uart_data[uart].baud) |
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| 170 | { |
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| 171 | return; |
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| 172 | } |
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| 173 | |
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| 174 | ier = uread(uart, IER); |
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| 175 | |
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| 176 | BSP_uart_init(uart, baud, uart_data[uart].hwFlow); |
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| 177 | |
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| 178 | uwrite(uart, IER, ier); |
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[6128a4a] | 179 | |
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[08330bf] | 180 | return; |
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| 181 | } |
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| 182 | |
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| 183 | /* |
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[6128a4a] | 184 | * Enable/disable interrupts |
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[08330bf] | 185 | */ |
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[6128a4a] | 186 | void |
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[08330bf] | 187 | BSP_uart_intr_ctrl(int uart, int cmd) |
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| 188 | { |
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| 189 | |
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| 190 | assert(uart == BSP_UART_COM1 || uart == BSP_UART_COM2); |
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| 191 | |
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| 192 | switch(cmd) |
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| 193 | { |
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| 194 | case BSP_UART_INTR_CTRL_DISABLE: |
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| 195 | uwrite(uart, IER, INTERRUPT_DISABLE); |
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| 196 | break; |
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| 197 | case BSP_UART_INTR_CTRL_ENABLE: |
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| 198 | uwrite(uart, IER, |
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| 199 | (RECEIVE_ENABLE | |
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| 200 | TRANSMIT_ENABLE | |
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| 201 | RECEIVER_LINE_ST_ENABLE |
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| 202 | ) |
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| 203 | ); |
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| 204 | break; |
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| 205 | case BSP_UART_INTR_CTRL_TERMIOS: |
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| 206 | uwrite(uart, IER, |
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| 207 | (RECEIVE_ENABLE | |
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| 208 | RECEIVER_LINE_ST_ENABLE |
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| 209 | ) |
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| 210 | ); |
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| 211 | break; |
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| 212 | case BSP_UART_INTR_CTRL_GDB: |
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| 213 | uwrite(uart, IER, RECEIVE_ENABLE); |
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| 214 | break; |
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| 215 | default: |
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| 216 | assert(0); |
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| 217 | break; |
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| 218 | } |
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[6128a4a] | 219 | |
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[08330bf] | 220 | return; |
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| 221 | } |
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| 222 | |
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| 223 | /* |
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| 224 | * Status function, -1 if error |
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| 225 | * detected, 0 if no received chars available, |
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| 226 | * 1 if received char available, 2 if break |
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[6128a4a] | 227 | * is detected, it will eat break and error |
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| 228 | * chars. It ignores overruns - we cannot do |
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[08330bf] | 229 | * anything about - it execpt count statistics |
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| 230 | * and we are not counting it. |
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| 231 | */ |
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[6128a4a] | 232 | int |
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[08330bf] | 233 | BSP_uart_polled_status(int uart) |
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| 234 | { |
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| 235 | unsigned char val; |
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| 236 | |
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| 237 | assert(uart == BSP_UART_COM1 || uart == BSP_UART_COM2); |
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| 238 | |
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| 239 | val = uread(uart, LSR); |
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| 240 | |
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| 241 | if(val & BI) |
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| 242 | { |
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| 243 | /* BREAK found, eat character */ |
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| 244 | uread(uart, RBR); |
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| 245 | return BSP_UART_STATUS_BREAK; |
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| 246 | } |
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| 247 | |
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| 248 | if((val & (DR | OE | FE)) == 1) |
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| 249 | { |
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[6128a4a] | 250 | /* No error, character present */ |
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[08330bf] | 251 | return BSP_UART_STATUS_CHAR; |
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| 252 | } |
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| 253 | |
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| 254 | if((val & (DR | OE | FE)) == 0) |
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| 255 | { |
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| 256 | /* Nothing */ |
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| 257 | return BSP_UART_STATUS_NOCHAR; |
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| 258 | } |
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| 259 | |
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[6128a4a] | 260 | /* |
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[08330bf] | 261 | * Framing or parity error |
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| 262 | * eat character |
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| 263 | */ |
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| 264 | uread(uart, RBR); |
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[6128a4a] | 265 | |
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[08330bf] | 266 | return BSP_UART_STATUS_ERROR; |
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| 267 | } |
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| 268 | |
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| 269 | /* |
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| 270 | * Polled mode write function |
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| 271 | */ |
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[6128a4a] | 272 | void |
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[08330bf] | 273 | BSP_uart_polled_write(int uart, int val) |
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| 274 | { |
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| 275 | unsigned char val1; |
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[6128a4a] | 276 | |
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[08330bf] | 277 | /* Sanity check */ |
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| 278 | assert(uart == BSP_UART_COM1 || uart == BSP_UART_COM2); |
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[6128a4a] | 279 | |
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[08330bf] | 280 | for(;;) |
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| 281 | { |
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[6128a4a] | 282 | if((val1=uread(uart, LSR)) & THRE) |
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[08330bf] | 283 | { |
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| 284 | break; |
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| 285 | } |
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| 286 | } |
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| 287 | |
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| 288 | uwrite(uart, THR, val & 0xff); |
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[6128a4a] | 289 | |
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[08330bf] | 290 | return; |
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| 291 | } |
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| 292 | |
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| 293 | void |
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| 294 | BSP_output_char_via_serial(int val) |
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| 295 | { |
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| 296 | BSP_uart_polled_write(BSPConsolePort, val); |
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| 297 | if (val == '\n') BSP_uart_polled_write(BSPConsolePort,'\r'); |
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| 298 | } |
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| 299 | |
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[6128a4a] | 300 | /* |
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[08330bf] | 301 | * Polled mode read function |
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| 302 | */ |
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[6128a4a] | 303 | int |
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[08330bf] | 304 | BSP_uart_polled_read(int uart) |
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| 305 | { |
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| 306 | unsigned char val; |
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| 307 | |
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| 308 | assert(uart == BSP_UART_COM1 || uart == BSP_UART_COM2); |
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[6128a4a] | 309 | |
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[08330bf] | 310 | for(;;) |
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| 311 | { |
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| 312 | if(uread(uart, LSR) & DR) |
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| 313 | { |
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| 314 | break; |
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| 315 | } |
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| 316 | } |
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[6128a4a] | 317 | |
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[08330bf] | 318 | val = uread(uart, RBR); |
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| 319 | |
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| 320 | return (int)(val & 0xff); |
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| 321 | } |
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| 322 | |
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[6128a4a] | 323 | unsigned |
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[08330bf] | 324 | BSP_poll_char_via_serial() |
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| 325 | { |
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| 326 | return BSP_uart_polled_read(BSPConsolePort); |
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| 327 | } |
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| 328 | |
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| 329 | /* ================ Termios support =================*/ |
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| 330 | |
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| 331 | static volatile int termios_stopped_com1 = 0; |
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| 332 | static volatile int termios_tx_active_com1 = 0; |
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| 333 | static void* termios_ttyp_com1 = NULL; |
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| 334 | static char termios_tx_hold_com1 = 0; |
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| 335 | static volatile char termios_tx_hold_valid_com1 = 0; |
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| 336 | |
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| 337 | static volatile int termios_stopped_com2 = 0; |
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| 338 | static volatile int termios_tx_active_com2 = 0; |
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| 339 | static void* termios_ttyp_com2 = NULL; |
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| 340 | static char termios_tx_hold_com2 = 0; |
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| 341 | static volatile char termios_tx_hold_valid_com2 = 0; |
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| 342 | |
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| 343 | /* |
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[6128a4a] | 344 | * Set channel parameters |
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[08330bf] | 345 | */ |
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| 346 | void |
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| 347 | BSP_uart_termios_set(int uart, void *ttyp) |
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| 348 | { |
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| 349 | assert(uart == BSP_UART_COM1 || uart == BSP_UART_COM2); |
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[6128a4a] | 350 | |
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[08330bf] | 351 | if(uart == BSP_UART_COM1) |
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| 352 | { |
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| 353 | termios_stopped_com1 = 0; |
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| 354 | termios_tx_active_com1 = 0; |
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| 355 | termios_ttyp_com1 = ttyp; |
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[6128a4a] | 356 | termios_tx_hold_com1 = 0; |
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[08330bf] | 357 | termios_tx_hold_valid_com1 = 0; |
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| 358 | } |
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| 359 | else |
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| 360 | { |
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| 361 | termios_stopped_com2 = 0; |
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| 362 | termios_tx_active_com2 = 0; |
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| 363 | termios_ttyp_com2 = ttyp; |
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[6128a4a] | 364 | termios_tx_hold_com2 = 0; |
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[08330bf] | 365 | termios_tx_hold_valid_com2 = 0; |
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| 366 | } |
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| 367 | |
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| 368 | return; |
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| 369 | } |
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| 370 | |
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| 371 | int |
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| 372 | BSP_uart_termios_write_com1(int minor, const char *buf, int len) |
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| 373 | { |
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| 374 | assert(buf != NULL); |
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| 375 | |
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| 376 | if(len <= 0) |
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| 377 | { |
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| 378 | return 0; |
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| 379 | } |
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| 380 | |
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| 381 | /* If there TX buffer is busy - something is royally screwed up */ |
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[6128a4a] | 382 | assert((uread(BSP_UART_COM1, LSR) & THRE) != 0); |
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[08330bf] | 383 | |
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| 384 | if(termios_stopped_com1) |
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| 385 | { |
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| 386 | /* CTS low */ |
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| 387 | termios_tx_hold_com1 = *buf; |
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| 388 | termios_tx_hold_valid_com1 = 1; |
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| 389 | return 0; |
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| 390 | } |
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| 391 | |
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| 392 | /* Write character */ |
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| 393 | uwrite(BSP_UART_COM1, THR, *buf & 0xff); |
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| 394 | |
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| 395 | /* Enable interrupts if necessary */ |
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| 396 | if(!termios_tx_active_com1) |
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| 397 | { |
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| 398 | termios_tx_active_com1 = 1; |
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[6128a4a] | 399 | uwrite(BSP_UART_COM1, IER, |
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[08330bf] | 400 | (RECEIVE_ENABLE | |
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| 401 | TRANSMIT_ENABLE | |
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| 402 | RECEIVER_LINE_ST_ENABLE |
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| 403 | ) |
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| 404 | ); |
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| 405 | } |
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| 406 | |
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| 407 | return 0; |
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| 408 | } |
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| 409 | |
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| 410 | int |
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| 411 | BSP_uart_termios_write_com2(int minor, const char *buf, int len) |
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| 412 | { |
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| 413 | assert(buf != NULL); |
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| 414 | |
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| 415 | if(len <= 0) |
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| 416 | { |
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| 417 | return 0; |
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| 418 | } |
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| 419 | |
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| 420 | /* If there TX buffer is busy - something is royally screwed up */ |
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| 421 | assert((uread(BSP_UART_COM2, LSR) & THRE) != 0); |
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| 422 | |
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| 423 | if(termios_stopped_com2) |
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| 424 | { |
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| 425 | /* CTS low */ |
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| 426 | termios_tx_hold_com2 = *buf; |
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| 427 | termios_tx_hold_valid_com2 = 1; |
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| 428 | return 0; |
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| 429 | } |
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| 430 | |
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| 431 | /* Write character */ |
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| 432 | |
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| 433 | uwrite(BSP_UART_COM2, THR, *buf & 0xff); |
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| 434 | |
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| 435 | /* Enable interrupts if necessary */ |
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| 436 | if(!termios_tx_active_com2) |
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| 437 | { |
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| 438 | termios_tx_active_com2 = 1; |
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| 439 | uwrite(BSP_UART_COM2, IER, |
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| 440 | (RECEIVE_ENABLE | |
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| 441 | TRANSMIT_ENABLE | |
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| 442 | RECEIVER_LINE_ST_ENABLE |
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| 443 | ) |
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| 444 | ); |
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| 445 | } |
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| 446 | |
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| 447 | return 0; |
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| 448 | } |
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| 449 | |
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| 450 | void |
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| 451 | BSP_uart_termios_isr_com1(void) |
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| 452 | { |
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| 453 | unsigned char buf[40]; |
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| 454 | int off, ret, vect; |
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| 455 | |
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| 456 | off = 0; |
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| 457 | |
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| 458 | for(;;) |
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| 459 | { |
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| 460 | vect = uread(BSP_UART_COM1, IIR) & 0xf; |
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[6128a4a] | 461 | |
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[08330bf] | 462 | switch(vect) |
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| 463 | { |
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| 464 | case NO_MORE_INTR : |
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| 465 | /* No more interrupts */ |
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| 466 | if(off != 0) |
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| 467 | { |
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| 468 | /* Update rx buffer */ |
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| 469 | rtems_termios_enqueue_raw_characters(termios_ttyp_com1, |
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| 470 | (char *)buf, |
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| 471 | off); |
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| 472 | } |
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| 473 | return; |
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| 474 | case TRANSMITTER_HODING_REGISTER_EMPTY : |
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[6128a4a] | 475 | /* |
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| 476 | * TX holding empty: we have to disable these interrupts |
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| 477 | * if there is nothing more to send. |
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[08330bf] | 478 | */ |
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| 479 | |
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| 480 | ret = rtems_termios_dequeue_characters(termios_ttyp_com1, 1); |
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| 481 | |
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| 482 | /* If nothing else to send disable interrupts */ |
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| 483 | if(ret == 0) |
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| 484 | { |
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| 485 | uwrite(BSP_UART_COM1, IER, |
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| 486 | (RECEIVE_ENABLE | |
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| 487 | RECEIVER_LINE_ST_ENABLE |
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| 488 | ) |
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| 489 | ); |
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| 490 | termios_tx_active_com1 = 0; |
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| 491 | } |
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| 492 | break; |
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| 493 | case RECEIVER_DATA_AVAIL : |
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| 494 | case CHARACTER_TIMEOUT_INDICATION: |
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| 495 | /* RX data ready */ |
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| 496 | assert(off < sizeof(buf)); |
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| 497 | buf[off++] = uread(BSP_UART_COM1, RBR); |
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| 498 | break; |
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| 499 | case RECEIVER_ERROR: |
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| 500 | /* RX error: eat character */ |
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| 501 | uartError(BSP_UART_COM1); |
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| 502 | break; |
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| 503 | default: |
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| 504 | /* Should not happen */ |
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| 505 | assert(0); |
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| 506 | return; |
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| 507 | } |
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| 508 | } |
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| 509 | } |
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[6128a4a] | 510 | |
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[08330bf] | 511 | void |
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| 512 | BSP_uart_termios_isr_com2() |
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| 513 | { |
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| 514 | unsigned char buf[40]; |
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| 515 | int off, ret, vect; |
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| 516 | |
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| 517 | off = 0; |
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| 518 | |
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| 519 | for(;;) |
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| 520 | { |
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| 521 | vect = uread(BSP_UART_COM2, IIR) & 0xf; |
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[6128a4a] | 522 | |
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[08330bf] | 523 | switch(vect) |
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| 524 | { |
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| 525 | case NO_MORE_INTR : |
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| 526 | /* No more interrupts */ |
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| 527 | if(off != 0) |
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| 528 | { |
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| 529 | /* Update rx buffer */ |
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| 530 | rtems_termios_enqueue_raw_characters(termios_ttyp_com2, |
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| 531 | (char *)buf, |
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| 532 | off); |
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| 533 | } |
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| 534 | return; |
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| 535 | case TRANSMITTER_HODING_REGISTER_EMPTY : |
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[6128a4a] | 536 | /* |
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| 537 | * TX holding empty: we have to disable these interrupts |
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[08330bf] | 538 | * if there is nothing more to send. |
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| 539 | */ |
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| 540 | |
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| 541 | ret = rtems_termios_dequeue_characters(termios_ttyp_com2, 1); |
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| 542 | |
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| 543 | /* If nothing else to send disable interrupts */ |
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| 544 | if(ret == 0) |
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| 545 | { |
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| 546 | uwrite(BSP_UART_COM2, IER, |
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| 547 | (RECEIVE_ENABLE | |
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| 548 | RECEIVER_LINE_ST_ENABLE |
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| 549 | ) |
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| 550 | ); |
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| 551 | termios_tx_active_com2 = 0; |
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| 552 | } |
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| 553 | break; |
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| 554 | case RECEIVER_DATA_AVAIL : |
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| 555 | case CHARACTER_TIMEOUT_INDICATION: |
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| 556 | /* RX data ready */ |
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| 557 | assert(off < sizeof(buf)); |
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| 558 | buf[off++] = uread(BSP_UART_COM2, RBR); |
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| 559 | break; |
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| 560 | case RECEIVER_ERROR: |
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| 561 | /* RX error: eat character */ |
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| 562 | uartError(BSP_UART_COM2); |
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| 563 | break; |
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| 564 | default: |
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| 565 | /* Should not happen */ |
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| 566 | assert(0); |
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| 567 | return; |
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| 568 | } |
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| 569 | } |
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| 570 | } |
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