source: rtems/c/src/lib/libbsp/arm/shared/armv7m/include/cache_.h @ f2e0f8e

5
Last change on this file since f2e0f8e was f2e0f8e, checked in by Sebastian Huber <sebastian.huber@…>, on Jan 14, 2016 at 3:03:51 PM

bsp/atsam: New

Close #2529.

  • Property mode set to 100644
File size: 2.8 KB
Line 
1/*
2 * Copyright (c) 2016 embedded brains GmbH.  All rights reserved.
3 *
4 *  embedded brains GmbH
5 *  Dornierstr. 4
6 *  82178 Puchheim
7 *  Germany
8 *  <rtems@embedded-brains.de>
9 *
10 * The license and distribution terms for this file may be
11 * found in the file LICENSE in this distribution or at
12 * http://www.rtems.org/license/LICENSE.
13 */
14
15#ifndef LIBBSP_ARM_ARMV7M_CACHE__H
16#define LIBBSP_ARM_ARMV7M_CACHE__H
17
18#include <rtems.h>
19#include <chip.h>
20
21#define CPU_DATA_CACHE_ALIGNMENT 32
22
23#define CPU_INSTRUCTION_CACHE_ALIGNMENT 32
24
25#define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS
26
27static inline void _CPU_cache_flush_data_range(
28  const void *d_addr,
29  size_t n_bytes
30)
31{
32  SCB_CleanInvalidateDCache_by_Addr(
33    RTEMS_DECONST(uint32_t *, (const uint32_t *) d_addr),
34    n_bytes
35  );
36}
37
38static inline void _CPU_cache_invalidate_data_range(
39  const void *d_addr,
40  size_t n_bytes
41)
42{
43  SCB_InvalidateDCache_by_Addr(
44    RTEMS_DECONST(uint32_t *, (const uint32_t *) d_addr),
45    n_bytes
46  );
47}
48
49static inline void _CPU_cache_freeze_data(void)
50{
51  /* TODO */
52}
53
54static inline void _CPU_cache_unfreeze_data(void)
55{
56  /* TODO */
57}
58
59static inline void _CPU_cache_invalidate_instruction_range(
60  const void *i_addr,
61  size_t n_bytes
62)
63{
64  rtems_interrupt_level level;
65
66  rtems_interrupt_disable(level);
67  SCB_InvalidateICache();
68  rtems_interrupt_enable(level);
69}
70
71static inline void _CPU_cache_freeze_instruction(void)
72{
73  /* TODO */
74}
75
76static inline void _CPU_cache_unfreeze_instruction(void)
77{
78  /* TODO */
79}
80
81static inline void _CPU_cache_flush_entire_data(void)
82{
83  rtems_interrupt_level level;
84
85  rtems_interrupt_disable(level);
86  SCB_CleanDCache();
87  rtems_interrupt_enable(level);
88}
89
90static inline void _CPU_cache_invalidate_entire_data(void)
91{
92  rtems_interrupt_level level;
93
94  rtems_interrupt_disable(level);
95  SCB_InvalidateDCache();
96  rtems_interrupt_enable(level);
97}
98
99static inline void _CPU_cache_enable_data(void)
100{
101  rtems_interrupt_level level;
102
103  rtems_interrupt_disable(level);
104  SCB_EnableDCache();
105  rtems_interrupt_enable(level);
106}
107
108static inline void _CPU_cache_disable_data(void)
109{
110  rtems_interrupt_level level;
111
112  rtems_interrupt_disable(level);
113  SCB_DisableDCache();
114  rtems_interrupt_enable(level);
115}
116
117static inline void _CPU_cache_invalidate_entire_instruction(void)
118{
119  rtems_interrupt_level level;
120
121  rtems_interrupt_disable(level);
122  SCB_InvalidateICache();
123  rtems_interrupt_enable(level);
124}
125
126static inline void _CPU_cache_enable_instruction(void)
127{
128  rtems_interrupt_level level;
129
130  rtems_interrupt_disable(level);
131  SCB_EnableICache();
132  rtems_interrupt_enable(level);
133}
134
135static inline void _CPU_cache_disable_instruction(void)
136{
137  rtems_interrupt_level level;
138
139  rtems_interrupt_disable(level);
140  SCB_DisableICache();
141  rtems_interrupt_enable(level);
142}
143
144#endif /* LIBBSP_ARM_ARMV7M_CACHE__H */
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