source: rtems/c/src/lib/libbsp/arm/shared/armv467ar-basic-cache/cache_.h @ 612297e8

Last change on this file since 612297e8 was 612297e8, checked in by Joel Sherrill <joel@…>, on Jul 12, 2016 at 10:44:17 AM

Misc: Spell length correctly

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File size: 3.6 KB
Line 
1/**
2 * @file
3 *
4 * @ingroup arm
5 *
6 * @brief ARM cache defines and implementation.
7 */
8
9/*
10 * Copyright (c) 2009-2011 embedded brains GmbH.  All rights reserved.
11 *
12 *  embedded brains GmbH
13 *  Obere Lagerstr. 30
14 *  82178 Puchheim
15 *  Germany
16 *  <rtems@embedded-brains.de>
17 *
18 * The license and distribution terms for this file may be
19 * found in the file LICENSE in this distribution or at
20 * http://www.rtems.org/license/LICENSE.
21 */
22
23#ifndef LIBBSP_ARM_ARMV467AR_BASIC_CACHE_H
24#define LIBBSP_ARM_ARMV467AR_BASIC_CACHE_H
25
26#include <libcpu/arm-cp15.h>
27#include "../include/arm-cache-l1.h"
28
29#define CPU_DATA_CACHE_ALIGNMENT 32
30#define CPU_INSTRUCTION_CACHE_ALIGNMENT 32
31#if defined(__ARM_ARCH_7A__)
32/* Some/many ARM Cortex-A cores have L1 data line length 64 bytes */
33#define CPU_MAXIMAL_CACHE_ALIGNMENT 64
34#endif
35
36#define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS \
37          ARM_CACHE_L1_CPU_SUPPORT_PROVIDES_RANGE_FUNCTIONS
38
39
40static inline void _CPU_cache_flush_1_data_line(const void *d_addr)
41{
42  arm_cache_l1_flush_1_data_line(d_addr);
43}
44
45static inline void
46_CPU_cache_flush_data_range(
47  const void *d_addr,
48  size_t      n_bytes
49)
50{
51  _ARM_Data_synchronization_barrier();
52  arm_cp15_drain_write_buffer();
53  arm_cache_l1_flush_data_range(
54    d_addr,
55    n_bytes
56  );
57}
58
59static inline void _CPU_cache_invalidate_1_data_line(const void *d_addr)
60{
61  arm_cache_l1_invalidate_1_data_line(d_addr);
62}
63
64static inline void
65_CPU_cache_invalidate_data_range(
66  const void *addr_first,
67  size_t     n_bytes
68)
69{
70  arm_cache_l1_invalidate_data_range(
71    addr_first,
72    n_bytes
73  );
74}
75
76static inline void _CPU_cache_freeze_data(void)
77{
78  /* TODO */
79}
80
81static inline void _CPU_cache_unfreeze_data(void)
82{
83  /* TODO */
84}
85
86static inline void _CPU_cache_invalidate_1_instruction_line(const void *d_addr)
87{
88  arm_cache_l1_invalidate_1_instruction_line(d_addr);
89}
90
91static inline void
92_CPU_cache_invalidate_instruction_range( const void *i_addr, size_t n_bytes)
93{
94  arm_cache_l1_invalidate_instruction_range( i_addr, n_bytes );
95}
96
97static inline void _CPU_cache_freeze_instruction(void)
98{
99  /* TODO */
100}
101
102static inline void _CPU_cache_unfreeze_instruction(void)
103{
104  /* TODO */
105}
106
107static inline void _CPU_cache_flush_entire_data(void)
108{
109  arm_cp15_data_cache_test_and_clean();
110}
111
112static inline void _CPU_cache_invalidate_entire_data(void)
113{
114  arm_cp15_data_cache_invalidate();
115}
116
117static inline void _CPU_cache_enable_data(void)
118{
119  rtems_interrupt_level level;
120  uint32_t ctrl;
121
122  rtems_interrupt_local_disable(level);
123  ctrl = arm_cp15_get_control();
124  ctrl |= ARM_CP15_CTRL_C;
125  arm_cp15_set_control(ctrl);
126  rtems_interrupt_local_enable(level);
127}
128
129static inline void _CPU_cache_disable_data(void)
130{
131  rtems_interrupt_level level;
132  uint32_t ctrl;
133
134  rtems_interrupt_local_disable(level);
135  arm_cp15_data_cache_test_and_clean_and_invalidate();
136  ctrl = arm_cp15_get_control();
137  ctrl &= ~ARM_CP15_CTRL_C;
138  arm_cp15_set_control(ctrl);
139  rtems_interrupt_local_enable(level);
140}
141
142static inline void _CPU_cache_invalidate_entire_instruction(void)
143{
144  arm_cp15_instruction_cache_invalidate();
145}
146
147static inline void _CPU_cache_enable_instruction(void)
148{
149  rtems_interrupt_level level;
150  uint32_t ctrl;
151
152  rtems_interrupt_local_disable(level);
153  ctrl = arm_cp15_get_control();
154  ctrl |= ARM_CP15_CTRL_I;
155  arm_cp15_set_control(ctrl);
156  rtems_interrupt_local_enable(level);
157}
158
159static inline void _CPU_cache_disable_instruction(void)
160{
161  rtems_interrupt_level level;
162  uint32_t ctrl;
163
164  rtems_interrupt_local_disable(level);
165  ctrl = arm_cp15_get_control();
166  ctrl &= ~ARM_CP15_CTRL_I;
167  arm_cp15_set_control(ctrl);
168  rtems_interrupt_local_enable(level);
169}
170
171#endif /* LIBBSP_ARM_ARMV467AR_BASIC_CACHE_H */
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