1 | /** |
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2 | * @file cache_.h |
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3 | * |
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4 | * @ingroup L2C-310_cache |
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5 | * |
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6 | * @brief Cache definitions and functions. |
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7 | * |
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8 | * This file implements handling for the ARM L2C-310 cache controller |
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9 | */ |
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10 | |
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11 | /* |
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12 | * Authorship |
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13 | * ---------- |
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14 | * This software was created by |
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15 | * R. Claus <claus@slac.stanford.edu>, 2013, |
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16 | * Stanford Linear Accelerator Center, Stanford University. |
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17 | * |
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18 | * Acknowledgement of sponsorship |
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19 | * ------------------------------ |
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20 | * This software was produced by |
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21 | * the Stanford Linear Accelerator Center, Stanford University, |
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22 | * under Contract DE-AC03-76SFO0515 with the Department of Energy. |
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23 | * |
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24 | * Government disclaimer of liability |
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25 | * ---------------------------------- |
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26 | * Neither the United States nor the United States Department of Energy, |
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27 | * nor any of their employees, makes any warranty, express or implied, or |
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28 | * assumes any legal liability or responsibility for the accuracy, |
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29 | * completeness, or usefulness of any data, apparatus, product, or process |
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30 | * disclosed, or represents that its use would not infringe privately owned |
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31 | * rights. |
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32 | * |
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33 | * Stanford disclaimer of liability |
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34 | * -------------------------------- |
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35 | * Stanford University makes no representations or warranties, express or |
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36 | * implied, nor assumes any liability for the use of this software. |
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37 | * |
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38 | * Stanford disclaimer of copyright |
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39 | * -------------------------------- |
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40 | * Stanford University, owner of the copyright, hereby disclaims its |
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41 | * copyright and all other rights in this software. Hence, anyone may |
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42 | * freely use it for any purpose without restriction. |
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43 | * |
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44 | * Maintenance of notices |
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45 | * ---------------------- |
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46 | * In the interest of clarity regarding the origin and status of this |
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47 | * SLAC software, this and all the preceding Stanford University notices |
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48 | * are to remain affixed to any copy or derivative of this software made |
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49 | * or distributed by the recipient and are to be affixed to any copy of |
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50 | * software made or distributed by the recipient that contains a copy or |
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51 | * derivative of this software. |
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52 | * |
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53 | * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 |
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54 | */ |
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55 | |
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56 | #ifndef LIBBSP_ARM_SHARED_L2C_310_CACHE_H |
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57 | #define LIBBSP_ARM_SHARED_L2C_310_CACHE_H |
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58 | |
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59 | #include <assert.h> |
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60 | #include <bsp.h> |
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61 | #include <bsp/fatal.h> |
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62 | #include <libcpu/arm-cp15.h> |
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63 | #include <rtems/rtems/intr.h> |
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64 | #include <bsp/arm-release-id.h> |
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65 | #include <bsp/arm-errata.h> |
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66 | #include "../include/arm-cache-l1.h" |
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67 | |
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68 | #ifdef __cplusplus |
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69 | extern "C" { |
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70 | #endif /* __cplusplus */ |
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71 | |
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72 | /* These two defines also ensure that the rtems_cache_* functions have bodies */ |
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73 | #define CPU_DATA_CACHE_ALIGNMENT ARM_CACHE_L1_CPU_DATA_ALIGNMENT |
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74 | #define CPU_INSTRUCTION_CACHE_ALIGNMENT ARM_CACHE_L1_CPU_INSTRUCTION_ALIGNMENT |
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75 | #define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS \ |
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76 | ARM_CACHE_L1_CPU_SUPPORT_PROVIDES_RANGE_FUNCTIONS |
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77 | #define CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS |
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78 | |
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79 | #define L2C_310_DATA_LINE_MASK ( CPU_DATA_CACHE_ALIGNMENT - 1 ) |
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80 | #define L2C_310_INSTRUCTION_LINE_MASK \ |
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81 | ( CPU_INSTRUCTION_CACHE_ALIGNMENT \ |
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82 | - 1 ) |
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83 | #define L2C_310_NUM_WAYS 8 |
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84 | #define L2C_310_WAY_MASK ( ( 1 << L2C_310_NUM_WAYS ) - 1 ) |
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85 | |
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86 | #define L2C_310_MIN( a, b ) \ |
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87 | ((a < b) ? (a) : (b)) |
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88 | |
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89 | #define L2C_310_MAX_LOCKING_BYTES (4 * 1024) |
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90 | |
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91 | |
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92 | /* RTL release number as can be read from cache_id register */ |
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93 | typedef enum { |
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94 | L2C_310_RTL_RELEASE_R0_P0 = 0x0, |
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95 | L2C_310_RTL_RELEASE_R1_P0 = 0x2, |
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96 | L2C_310_RTL_RELEASE_R2_P0 = 0x4, |
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97 | L2C_310_RTL_RELEASE_R3_P0 = 0x5, |
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98 | L2C_310_RTL_RELEASE_R3_P1 = 0x6, |
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99 | L2C_310_RTL_RELEASE_R3_P2 = 0x8, |
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100 | L2C_310_RTL_RELEASE_R3_P3 = 0x9 |
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101 | } cache_l2c_310_rtl_release; |
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102 | |
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103 | /** |
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104 | * @defgroup L2C-310_cache Cache Support |
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105 | * @ingroup arm_shared |
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106 | * @brief Cache Functions and Defitions |
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107 | * @{ |
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108 | */ |
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109 | |
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110 | |
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111 | /** |
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112 | * @brief L2CC Register Offsets |
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113 | */ |
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114 | typedef struct { |
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115 | /** @brief Cache ID */ |
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116 | uint32_t cache_id; |
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117 | #define L2C_310_ID_RTL_MASK 0x3f |
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118 | #define L2C_310_ID_PART_MASK ( 0xf << 6 ) |
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119 | #define L2C_310_ID_PART_L210 ( 1 << 6 ) |
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120 | #define L2C_310_ID_PART_L310 ( 3 << 6 ) |
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121 | #define L2C_310_ID_IMPL_MASK ( 0xff << 24 ) |
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122 | /** @brief Cache type */ |
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123 | uint32_t cache_type; |
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124 | /** @brief 1 if data banking implemented, 0 if not */ |
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125 | #define L2C_310_TYPE_DATA_BANKING_MASK 0x80000000 |
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126 | /** @brief 11xy, where: x=1 if pl310_LOCKDOWN_BY_MASTER is defined, otherwise 0 */ |
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127 | #define L2C_310_TYPE_CTYPE_MASK 0x1E000000 |
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128 | /** @brief y=1 if pl310_LOCKDOWN_BY_LINE is defined, otherwise 0. */ |
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129 | #define L2C_310_TYPE_CTYPE_SHIFT 25 |
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130 | /** @brief 1 for Harvard architecture, 0 for unified architecture */ |
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131 | #define L2C_310_TYPE_HARVARD_MASK 0x01000000 |
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132 | /** @brief Data cache way size = 2 Exp(value + 2) KB */ |
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133 | #define L2C_310_TYPE_SIZE_D_WAYS_MASK 0x00700000 |
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134 | #define L2C_310_TYPE_SIZE_D_WAYS_SHIFT 20 |
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135 | /** @brief Assoziativity aka number of data ways = (value * 8) + 8 */ |
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136 | #define L2C_310_TYPE_NUM_D_WAYS_MASK 0x00040000 |
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137 | #define L2C_310_TYPE_NUM_D_WAYS_SHIFT 18 |
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138 | /** @brief Data cache line length 00 - 32 */ |
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139 | #define L2C_310_TYPE_LENGTH_D_LINE_MASK 0x00003000 |
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140 | #define L2C_310_TYPE_LENGTH_D_LINE_SHIFT 12 |
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141 | #define L2C_310_TYPE_LENGTH_D_LINE_VAL_32 0x0 |
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142 | /** @brief Instruction cache way size = 2 Exp(value + 2) KB */ |
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143 | #define L2C_310_TYPE_SIZE_I_WAYS_MASK 0x00000700 |
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144 | #define L2C_310_TYPE_SIZE_I_WAYS_SHIFT 8 |
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145 | /** @brief Assoziativity aka number of instruction ways = (value * 8) + 8 */ |
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146 | #define L2C_310_TYPE_NUM_I_WAYS_MASK 0x00000040 |
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147 | #define L2C_310_TYPE_NUM_I_WAYS_SHIFT 6 |
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148 | /** @brief Instruction cache line length 00 - 32 */ |
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149 | #define L2C_310_TYPE_LENGTH_I_LINE_MASK 0x00000003 |
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150 | #define L2C_310_TYPE_LENGTH_I_LINE_SHIFT 0 |
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151 | #define L2C_310_TYPE_LENGTH_I_LINE_VAL_32 0x0 |
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152 | |
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153 | uint8_t reserved_8[0x100 - 8]; |
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154 | uint32_t ctrl; /* Control */ |
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155 | /** @brief Enables the L2CC */ |
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156 | #define L2C_310_ENABLE_MASK 0x00000001 |
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157 | |
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158 | /** @brief Auxiliary control */ |
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159 | uint32_t aux_ctrl; |
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160 | |
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161 | /** @brief Early BRESP Enable */ |
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162 | #define L2C_310_AUX_EBRESPE_MASK 0x40000000 |
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163 | |
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164 | /** @brief Instruction Prefetch Enable */ |
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165 | #define L2C_310_AUX_IPFE_MASK 0x20000000 |
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166 | |
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167 | /** @brief Data Prefetch Enable */ |
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168 | #define L2C_310_AUX_DPFE_MASK 0x10000000 |
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169 | |
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170 | /** @brief Non-secure interrupt access control */ |
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171 | #define L2C_310_AUX_NSIC_MASK 0x08000000 |
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172 | |
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173 | /** @brief Non-secure lockdown enable */ |
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174 | #define L2C_310_AUX_NSLE_MASK 0x04000000 |
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175 | |
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176 | /** @brief Cache replacement policy */ |
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177 | #define L2C_310_AUX_CRP_MASK 0x02000000 |
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178 | |
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179 | /** @brief Force write allocate */ |
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180 | #define L2C_310_AUX_FWE_MASK 0x01800000 |
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181 | |
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182 | /** @brief Shared attribute override enable */ |
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183 | #define L2C_310_AUX_SAOE_MASK 0x00400000 |
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184 | |
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185 | /** @brief Parity enable */ |
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186 | #define L2C_310_AUX_PE_MASK 0x00200000 |
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187 | |
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188 | /** @brief Event monitor bus enable */ |
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189 | #define L2C_310_AUX_EMBE_MASK 0x00100000 |
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190 | |
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191 | /** @brief Way-size */ |
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192 | #define L2C_310_AUX_WAY_SIZE_MASK 0x000E0000 |
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193 | #define L2C_310_AUX_WAY_SIZE_SHIFT 17 |
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194 | |
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195 | /** @brief Way-size */ |
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196 | #define L2C_310_AUX_ASSOC_MASK 0x00010000 |
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197 | |
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198 | /** @brief Shared attribute invalidate enable */ |
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199 | #define L2C_310_AUX_SAIE_MASK 0x00002000 |
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200 | |
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201 | /** @brief Exclusive cache configuration */ |
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202 | #define L2C_310_AUX_EXCL_CACHE_MASK 0x00001000 |
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203 | |
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204 | /** @brief Store buffer device limitation Enable */ |
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205 | #define L2C_310_AUX_SBDLE_MASK 0x00000800 |
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206 | |
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207 | /** @brief High Priority for SO and Dev Reads Enable */ |
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208 | #define L2C_310_AUX_HPSODRE_MASK 0x00000400 |
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209 | |
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210 | /** @brief Full line of zero enable */ |
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211 | #define L2C_310_AUX_FLZE_MASK 0x00000001 |
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212 | |
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213 | /** @brief Enable all prefetching, */ |
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214 | #define L2C_310_AUX_REG_DEFAULT_MASK \ |
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215 | ( L2C_310_AUX_WAY_SIZE_MASK & ( 0x3 << L2C_310_AUX_WAY_SIZE_SHIFT ) ) \ |
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216 | | L2C_310_AUX_PE_MASK /* Prefetch enable */ \ |
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217 | | L2C_310_AUX_SAOE_MASK /* Shared attribute override enable */ \ |
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218 | | L2C_310_AUX_CRP_MASK /* Cache replacement policy */ \ |
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219 | | L2C_310_AUX_DPFE_MASK /* Data prefetch enable */ \ |
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220 | | L2C_310_AUX_IPFE_MASK /* Instruction prefetch enable */ \ |
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221 | | L2C_310_AUX_EBRESPE_MASK /* Early BRESP enable */ |
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222 | |
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223 | #define L2C_310_AUX_REG_ZERO_MASK 0xFFF1FFFF |
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224 | |
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225 | /** @brief 1 cycle of latency, there is no additional latency fot tag RAM */ |
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226 | #define L2C_310_RAM_1_CYCLE_LAT_VAL 0x00000000 |
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227 | /** @brief 2 cycles of latency for tag RAM */ |
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228 | #define L2C_310_RAM_2_CYCLE_LAT_VAL 0x00000001 |
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229 | /** @brief 3 cycles of latency for tag RAM */ |
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230 | #define L2C_310_RAM_3_CYCLE_LAT_VAL 0x00000002 |
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231 | /** @brief 4 cycles of latency for tag RAM */ |
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232 | #define L2C_310_RAM_4_CYCLE_LAT_VAL 0x00000003 |
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233 | /** @brief 5 cycles of latency for tag RAM */ |
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234 | #define L2C_310_RAM_5_CYCLE_LAT_VAL 0x00000004 |
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235 | /** @brief 6 cycles of latency for tag RAM */ |
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236 | #define L2C_310_RAM_6_CYCLE_LAT_VAL 0x00000005 |
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237 | /** @brief 7 cycles of latency for tag RAM */ |
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238 | #define L2C_310_RAM_7_CYCLE_LAT_VAL 0x00000006 |
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239 | /** @brief 8 cycles of latency for tag RAM */ |
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240 | #define L2C_310_RAM_8_CYCLE_LAT_VAL 0x00000007 |
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241 | /** @brief Shift left setup latency values by this value */ |
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242 | #define L2C_310_RAM_SETUP_SHIFT 0x00000000 |
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243 | /** @brief Shift left read latency values by this value */ |
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244 | #define L2C_310_RAM_READ_SHIFT 0x00000004 |
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245 | /** @brief Shift left write latency values by this value */ |
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246 | #define L2C_310_RAM_WRITE_SHIFT 0x00000008 |
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247 | /** @brief Mask for RAM setup latency */ |
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248 | #define L2C_310_RAM_SETUP_LAT_MASK 0x00000007 |
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249 | /** @brief Mask for RAM read latency */ |
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250 | #define L2C_310_RAM_READ_LAT_MASK 0x00000070 |
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251 | /** @brief Mask for RAM read latency */ |
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252 | #define L2C_310_RAM_WRITE_LAT_MASK 0x00000700 |
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253 | /** @brief Latency for tag RAM */ |
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254 | uint32_t tag_ram_ctrl; |
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255 | /* @brief Latency for tag RAM */ |
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256 | #define L2C_310_TAG_RAM_DEFAULT_LAT \ |
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257 | ( ( L2C_310_RAM_2_CYCLE_LAT_VAL << L2C_310_RAM_SETUP_SHIFT ) \ |
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258 | | ( L2C_310_RAM_2_CYCLE_LAT_VAL << L2C_310_RAM_READ_SHIFT ) \ |
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259 | | ( L2C_310_RAM_2_CYCLE_LAT_VAL << L2C_310_RAM_WRITE_SHIFT ) ) |
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260 | /** @brief Latency for data RAM */ |
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261 | uint32_t data_ram_ctrl; |
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262 | /** @brief Latency for data RAM */ |
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263 | #define L2C_310_DATA_RAM_DEFAULT_MASK \ |
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264 | ( ( L2C_310_RAM_2_CYCLE_LAT_VAL << L2C_310_RAM_SETUP_SHIFT ) \ |
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265 | | ( L2C_310_RAM_3_CYCLE_LAT_VAL << L2C_310_RAM_READ_SHIFT ) \ |
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266 | | ( L2C_310_RAM_2_CYCLE_LAT_VAL << L2C_310_RAM_WRITE_SHIFT ) ) |
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267 | |
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268 | uint8_t reserved_110[0x200 - 0x110]; |
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269 | |
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270 | /** @brief Event counter control */ |
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271 | uint32_t ev_ctrl; |
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272 | |
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273 | /** @brief Event counter 1 configuration */ |
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274 | uint32_t ev_cnt1_cfg; |
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275 | |
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276 | /** @brief Event counter 0 configuration */ |
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277 | uint32_t ev_cnt0_cfg; |
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278 | |
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279 | /** @brief Event counter 1 value */ |
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280 | uint32_t ev_cnt1; |
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281 | |
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282 | /** @brief Event counter 0 value */ |
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283 | uint32_t ev_cnt0; |
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284 | |
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285 | /** @brief Interrupt enable mask */ |
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286 | uint32_t int_mask; |
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287 | |
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288 | /** @brief Masked interrupt status (read-only)*/ |
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289 | uint32_t int_mask_status; |
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290 | |
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291 | /** @brief Unmasked interrupt status */ |
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292 | uint32_t int_raw_status; |
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293 | |
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294 | /** @brief Interrupt clear */ |
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295 | uint32_t int_clr; |
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296 | |
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297 | /** |
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298 | * @name Interrupt bit masks |
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299 | * |
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300 | * @{ |
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301 | */ |
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302 | |
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303 | /** @brief DECERR from L3 */ |
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304 | #define L2C_310_INT_DECERR_MASK 0x00000100 |
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305 | |
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306 | /** @brief SLVERR from L3 */ |
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307 | #define L2C_310_INT_SLVERR_MASK 0x00000080 |
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308 | |
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309 | /** @brief Error on L2 data RAM (Read) */ |
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310 | #define L2C_310_INT_ERRRD_MASK 0x00000040 |
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311 | |
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312 | /** @brief Error on L2 tag RAM (Read) */ |
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313 | #define L2C_310_INT_ERRRT_MASK 0x00000020 |
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314 | |
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315 | /** @brief Error on L2 data RAM (Write) */ |
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316 | #define L2C_310_INT_ERRWD_MASK 0x00000010 |
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317 | |
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318 | /** @brief Error on L2 tag RAM (Write) */ |
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319 | #define L2C_310_INT_ERRWT_MASK 0x00000008 |
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320 | |
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321 | /** @brief Parity Error on L2 data RAM (Read) */ |
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322 | #define L2C_310_INT_PARRD_MASK 0x00000004 |
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323 | |
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324 | /** @brief Parity Error on L2 tag RAM (Read) */ |
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325 | #define L2C_310_INT_PARRT_MASK 0x00000002 |
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326 | |
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327 | /** @brief Event Counter1/0 Overflow Increment */ |
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328 | #define L2C_310_INT_ECNTR_MASK 0x00000001 |
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329 | |
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330 | /** @} */ |
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331 | |
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332 | uint8_t reserved_224[0x730 - 0x224]; |
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333 | |
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334 | /** @brief Drain the STB */ |
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335 | uint32_t cache_sync; |
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336 | uint8_t reserved_734[0x740 - 0x734]; |
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337 | /** @brief ARM Errata 753970 for pl310-r3p0 */ |
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338 | uint32_t dummy_cache_sync_reg; |
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339 | uint8_t reserved_744[0x770 - 0x744]; |
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340 | |
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341 | /** @brief Invalidate line by PA */ |
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342 | uint32_t inv_pa; |
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343 | uint8_t reserved_774[0x77c - 0x774]; |
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344 | |
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345 | /** @brief Invalidate by Way */ |
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346 | uint32_t inv_way; |
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347 | uint8_t reserved_780[0x7b0 - 0x780]; |
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348 | |
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349 | /** @brief Clean Line by PA */ |
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350 | uint32_t clean_pa; |
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351 | uint8_t reserved_7b4[0x7b8 - 0x7b4]; |
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352 | |
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353 | /** @brief Clean Line by Set/Way */ |
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354 | uint32_t clean_index; |
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355 | |
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356 | /** @brief Clean by Way */ |
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357 | uint32_t clean_way; |
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358 | uint8_t reserved_7c0[0x7f0 - 0x7c0]; |
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359 | |
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360 | /** @brief Clean and Invalidate Line by PA */ |
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361 | uint32_t clean_inv_pa; |
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362 | uint8_t reserved_7f4[0x7f8 - 0x7f4]; |
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363 | |
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364 | /** @brief Clean and Invalidate Line by Set/Way */ |
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365 | uint32_t clean_inv_indx; |
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366 | |
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367 | /** @brief Clean and Invalidate by Way */ |
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368 | uint32_t clean_inv_way; |
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369 | |
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370 | /** @brief Data lock down 0 */ |
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371 | uint32_t d_lockdown_0; |
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372 | |
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373 | /** @brief Instruction lock down 0 */ |
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374 | uint32_t i_lockdown_0; |
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375 | |
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376 | /** @brief Data lock down 1 */ |
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377 | uint32_t d_lockdown_1; |
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378 | |
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379 | /** @brief Instruction lock down 1 */ |
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380 | uint32_t i_lockdown_1; |
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381 | |
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382 | /** @brief Data lock down 2 */ |
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383 | uint32_t d_lockdown_2; |
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384 | |
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385 | /** @brief Instruction lock down 2 */ |
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386 | uint32_t i_lockdown_2; |
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387 | |
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388 | /** @brief Data lock down 3 */ |
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389 | uint32_t d_lockdown_3; |
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390 | |
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391 | /** @brief Instruction lock down 3 */ |
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392 | uint32_t i_lockdown_3; |
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393 | |
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394 | /** @brief Data lock down 4 */ |
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395 | uint32_t d_lockdown_4; |
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396 | |
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397 | /** @brief Instruction lock down 4 */ |
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398 | uint32_t i_lockdown_4; |
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399 | |
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400 | /** @brief Data lock down 5 */ |
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401 | uint32_t d_lockdown_5; |
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402 | |
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403 | /** @brief Instruction lock down 5 */ |
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404 | uint32_t i_lockdown_5; |
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405 | |
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406 | /** @brief Data lock down 6 */ |
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407 | uint32_t d_lockdown_6; |
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408 | |
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409 | /** @brief Instruction lock down 6 */ |
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410 | uint32_t i_lockdown_6; |
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411 | |
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412 | /** @brief Data lock down 7 */ |
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413 | uint32_t d_lockdown_7; |
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414 | |
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415 | /** @brief Instruction lock down 7 */ |
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416 | uint32_t i_lockdown_7; |
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417 | |
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418 | uint8_t reserved_940[0x950 - 0x940]; |
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419 | |
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420 | /** @brief Lockdown by Line Enable */ |
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421 | uint32_t lock_line_en; |
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422 | |
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423 | /** @brief Cache lockdown by way */ |
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424 | uint32_t unlock_way; |
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425 | |
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426 | uint8_t reserved_958[0xc00 - 0x958]; |
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427 | |
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428 | /** @brief Address range redirect, part 1 */ |
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429 | uint32_t addr_filtering_start; |
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430 | |
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431 | /** @brief Address range redirect, part 2 */ |
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432 | uint32_t addr_filtering_end; |
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433 | |
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434 | /** @brief Address filtering valid bits*/ |
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435 | #define L2C_310_ADDR_FILTER_VALID_MASK 0xFFF00000 |
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436 | |
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437 | /** @brief Address filtering enable bit*/ |
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438 | #define L2C_310_ADDR_FILTER_ENABLE_MASK 0x00000001 |
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439 | |
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440 | uint8_t reserved_c08[0xf40 - 0xc08]; |
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441 | |
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442 | /** @brief Debug control */ |
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443 | uint32_t debug_ctrl; |
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444 | |
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445 | /** @brief Debug SPIDEN bit */ |
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446 | #define L2C_310_DEBUG_SPIDEN_MASK 0x00000004 |
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447 | |
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448 | /** @brief Debug DWB bit, forces write through */ |
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449 | #define L2C_310_DEBUG_DWB_MASK 0x00000002 |
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450 | |
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451 | /** @brief Debug DCL bit, disables cache line fill */ |
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452 | #define L2C_310_DEBUG_DCL_MASK 0x00000002 |
---|
453 | |
---|
454 | uint8_t reserved_f44[0xf60 - 0xf44]; |
---|
455 | |
---|
456 | /** @brief Purpose prefetch enables */ |
---|
457 | uint32_t prefetch_ctrl; |
---|
458 | /** @brief Prefetch offset */ |
---|
459 | #define L2C_310_PREFETCH_OFFSET_MASK 0x0000001F |
---|
460 | uint8_t reserved_f64[0xf80 - 0xf64]; |
---|
461 | |
---|
462 | /** @brief Purpose power controls */ |
---|
463 | uint32_t power_ctrl; |
---|
464 | } L2CC; |
---|
465 | |
---|
466 | rtems_interrupt_lock l2c_310_cache_lock = RTEMS_INTERRUPT_LOCK_INITIALIZER( |
---|
467 | "cache" |
---|
468 | ); |
---|
469 | |
---|
470 | /* Errata table for the LC2 310 Level 2 cache from ARM. |
---|
471 | * Information taken from ARMs |
---|
472 | * "CoreLink controllers and peripherals |
---|
473 | * - System controllers |
---|
474 | * - L2C-310 Level 2 Cache Controller |
---|
475 | * - Revision r3p3 |
---|
476 | * - Software Developer Errata Notice |
---|
477 | * - ARM CoreLink Level 2 Cache Controller (L2C-310 or PL310), |
---|
478 | * r3 releases Software Developers Errata Notice" |
---|
479 | * Please see this document for more information on these erratas */ |
---|
480 | static bool l2c_310_cache_errata_is_applicable_753970( |
---|
481 | cache_l2c_310_rtl_release rtl_release |
---|
482 | ) |
---|
483 | { |
---|
484 | bool is_applicable = false; |
---|
485 | |
---|
486 | switch ( rtl_release ) { |
---|
487 | case L2C_310_RTL_RELEASE_R3_P3: |
---|
488 | case L2C_310_RTL_RELEASE_R3_P2: |
---|
489 | case L2C_310_RTL_RELEASE_R3_P1: |
---|
490 | case L2C_310_RTL_RELEASE_R2_P0: |
---|
491 | case L2C_310_RTL_RELEASE_R1_P0: |
---|
492 | case L2C_310_RTL_RELEASE_R0_P0: |
---|
493 | is_applicable = false; |
---|
494 | break; |
---|
495 | case L2C_310_RTL_RELEASE_R3_P0: |
---|
496 | is_applicable = true; |
---|
497 | break; |
---|
498 | default: |
---|
499 | assert( 0 ); |
---|
500 | break; |
---|
501 | } |
---|
502 | |
---|
503 | return is_applicable; |
---|
504 | } |
---|
505 | |
---|
506 | static bool l2c_310_cache_errata_is_applicable_727913( |
---|
507 | cache_l2c_310_rtl_release rtl_release |
---|
508 | ) |
---|
509 | { |
---|
510 | bool is_applicable = false; |
---|
511 | |
---|
512 | switch ( rtl_release ) { |
---|
513 | case L2C_310_RTL_RELEASE_R3_P3: |
---|
514 | case L2C_310_RTL_RELEASE_R3_P2: |
---|
515 | case L2C_310_RTL_RELEASE_R3_P1: |
---|
516 | case L2C_310_RTL_RELEASE_R2_P0: |
---|
517 | case L2C_310_RTL_RELEASE_R1_P0: |
---|
518 | case L2C_310_RTL_RELEASE_R0_P0: |
---|
519 | is_applicable = false; |
---|
520 | break; |
---|
521 | case L2C_310_RTL_RELEASE_R3_P0: |
---|
522 | is_applicable = true; |
---|
523 | break; |
---|
524 | default: |
---|
525 | assert( 0 ); |
---|
526 | break; |
---|
527 | } |
---|
528 | |
---|
529 | return is_applicable; |
---|
530 | } |
---|
531 | |
---|
532 | static bool l2c_310_cache_errata_is_applicable_727914( |
---|
533 | cache_l2c_310_rtl_release rtl_release |
---|
534 | ) |
---|
535 | { |
---|
536 | bool is_applicable = false; |
---|
537 | |
---|
538 | switch ( rtl_release ) { |
---|
539 | case L2C_310_RTL_RELEASE_R3_P3: |
---|
540 | case L2C_310_RTL_RELEASE_R3_P2: |
---|
541 | case L2C_310_RTL_RELEASE_R3_P1: |
---|
542 | case L2C_310_RTL_RELEASE_R2_P0: |
---|
543 | case L2C_310_RTL_RELEASE_R1_P0: |
---|
544 | case L2C_310_RTL_RELEASE_R0_P0: |
---|
545 | is_applicable = false; |
---|
546 | break; |
---|
547 | case L2C_310_RTL_RELEASE_R3_P0: |
---|
548 | is_applicable = true; |
---|
549 | break; |
---|
550 | default: |
---|
551 | assert( 0 ); |
---|
552 | break; |
---|
553 | } |
---|
554 | |
---|
555 | return is_applicable; |
---|
556 | } |
---|
557 | |
---|
558 | static bool l2c_310_cache_errata_is_applicable_727915( |
---|
559 | cache_l2c_310_rtl_release rtl_release |
---|
560 | ) |
---|
561 | { |
---|
562 | bool is_applicable = false; |
---|
563 | |
---|
564 | switch ( rtl_release ) { |
---|
565 | case L2C_310_RTL_RELEASE_R3_P3: |
---|
566 | case L2C_310_RTL_RELEASE_R3_P2: |
---|
567 | case L2C_310_RTL_RELEASE_R3_P1: |
---|
568 | case L2C_310_RTL_RELEASE_R1_P0: |
---|
569 | case L2C_310_RTL_RELEASE_R0_P0: |
---|
570 | is_applicable = false; |
---|
571 | break; |
---|
572 | case L2C_310_RTL_RELEASE_R3_P0: |
---|
573 | case L2C_310_RTL_RELEASE_R2_P0: |
---|
574 | is_applicable = true; |
---|
575 | break; |
---|
576 | default: |
---|
577 | assert( 0 ); |
---|
578 | break; |
---|
579 | } |
---|
580 | |
---|
581 | return is_applicable; |
---|
582 | } |
---|
583 | |
---|
584 | static bool l2c_310_cache_errata_is_applicable_729806( |
---|
585 | cache_l2c_310_rtl_release rtl_release |
---|
586 | ) |
---|
587 | { |
---|
588 | bool is_applicable = false; |
---|
589 | |
---|
590 | switch ( rtl_release ) { |
---|
591 | case L2C_310_RTL_RELEASE_R3_P3: |
---|
592 | case L2C_310_RTL_RELEASE_R3_P2: |
---|
593 | case L2C_310_RTL_RELEASE_R2_P0: |
---|
594 | case L2C_310_RTL_RELEASE_R1_P0: |
---|
595 | case L2C_310_RTL_RELEASE_R0_P0: |
---|
596 | is_applicable = false; |
---|
597 | break; |
---|
598 | case L2C_310_RTL_RELEASE_R3_P1: |
---|
599 | case L2C_310_RTL_RELEASE_R3_P0: |
---|
600 | is_applicable = true; |
---|
601 | break; |
---|
602 | default: |
---|
603 | assert( 0 ); |
---|
604 | break; |
---|
605 | } |
---|
606 | |
---|
607 | return is_applicable; |
---|
608 | } |
---|
609 | |
---|
610 | static bool l2c_310_cache_errata_is_applicable_729815( |
---|
611 | cache_l2c_310_rtl_release rtl_release |
---|
612 | ) |
---|
613 | { |
---|
614 | bool is_applicable = false; |
---|
615 | |
---|
616 | switch ( rtl_release ) { |
---|
617 | case L2C_310_RTL_RELEASE_R3_P3: |
---|
618 | case L2C_310_RTL_RELEASE_R1_P0: |
---|
619 | case L2C_310_RTL_RELEASE_R0_P0: |
---|
620 | is_applicable = false; |
---|
621 | break; |
---|
622 | case L2C_310_RTL_RELEASE_R3_P2: |
---|
623 | case L2C_310_RTL_RELEASE_R3_P1: |
---|
624 | case L2C_310_RTL_RELEASE_R3_P0: |
---|
625 | case L2C_310_RTL_RELEASE_R2_P0: |
---|
626 | is_applicable = true; |
---|
627 | break; |
---|
628 | default: |
---|
629 | assert( 0 ); |
---|
630 | break; |
---|
631 | } |
---|
632 | |
---|
633 | return is_applicable; |
---|
634 | } |
---|
635 | |
---|
636 | static bool l2c_310_cache_errata_is_applicable_742884( |
---|
637 | cache_l2c_310_rtl_release rtl_release |
---|
638 | ) |
---|
639 | { |
---|
640 | bool is_applicable = false; |
---|
641 | |
---|
642 | switch ( rtl_release ) { |
---|
643 | case L2C_310_RTL_RELEASE_R3_P3: |
---|
644 | case L2C_310_RTL_RELEASE_R3_P2: |
---|
645 | case L2C_310_RTL_RELEASE_R3_P0: |
---|
646 | case L2C_310_RTL_RELEASE_R2_P0: |
---|
647 | case L2C_310_RTL_RELEASE_R1_P0: |
---|
648 | case L2C_310_RTL_RELEASE_R0_P0: |
---|
649 | is_applicable = false; |
---|
650 | break; |
---|
651 | case L2C_310_RTL_RELEASE_R3_P1: |
---|
652 | is_applicable = true; |
---|
653 | break; |
---|
654 | default: |
---|
655 | assert( 0 ); |
---|
656 | break; |
---|
657 | } |
---|
658 | |
---|
659 | return is_applicable; |
---|
660 | } |
---|
661 | |
---|
662 | static bool l2c_310_cache_errata_is_applicable_752271( |
---|
663 | cache_l2c_310_rtl_release rtl_release |
---|
664 | ) |
---|
665 | { |
---|
666 | bool is_applicable = false; |
---|
667 | |
---|
668 | switch ( rtl_release ) { |
---|
669 | case L2C_310_RTL_RELEASE_R3_P3: |
---|
670 | case L2C_310_RTL_RELEASE_R3_P2: |
---|
671 | case L2C_310_RTL_RELEASE_R2_P0: |
---|
672 | case L2C_310_RTL_RELEASE_R1_P0: |
---|
673 | case L2C_310_RTL_RELEASE_R0_P0: |
---|
674 | is_applicable = false; |
---|
675 | break; |
---|
676 | case L2C_310_RTL_RELEASE_R3_P1: |
---|
677 | case L2C_310_RTL_RELEASE_R3_P0: |
---|
678 | is_applicable = true; |
---|
679 | break; |
---|
680 | default: |
---|
681 | assert( 0 ); |
---|
682 | break; |
---|
683 | } |
---|
684 | |
---|
685 | return is_applicable; |
---|
686 | } |
---|
687 | |
---|
688 | static bool l2c_310_cache_errata_is_applicable_765569( |
---|
689 | cache_l2c_310_rtl_release rtl_release |
---|
690 | ) |
---|
691 | { |
---|
692 | bool is_applicable = false; |
---|
693 | |
---|
694 | switch ( rtl_release ) { |
---|
695 | case L2C_310_RTL_RELEASE_R3_P3: |
---|
696 | case L2C_310_RTL_RELEASE_R3_P2: |
---|
697 | case L2C_310_RTL_RELEASE_R3_P1: |
---|
698 | case L2C_310_RTL_RELEASE_R3_P0: |
---|
699 | case L2C_310_RTL_RELEASE_R2_P0: |
---|
700 | case L2C_310_RTL_RELEASE_R1_P0: |
---|
701 | case L2C_310_RTL_RELEASE_R0_P0: |
---|
702 | is_applicable = true; |
---|
703 | break; |
---|
704 | default: |
---|
705 | assert( 0 ); |
---|
706 | break; |
---|
707 | } |
---|
708 | |
---|
709 | return is_applicable; |
---|
710 | } |
---|
711 | |
---|
712 | static bool l2c_310_cache_errata_is_applicable_769419( |
---|
713 | cache_l2c_310_rtl_release rtl_release |
---|
714 | ) |
---|
715 | { |
---|
716 | bool is_applicable = false; |
---|
717 | |
---|
718 | switch ( rtl_release ) { |
---|
719 | case L2C_310_RTL_RELEASE_R3_P3: |
---|
720 | case L2C_310_RTL_RELEASE_R3_P2: |
---|
721 | is_applicable = false; |
---|
722 | break; |
---|
723 | case L2C_310_RTL_RELEASE_R3_P1: |
---|
724 | case L2C_310_RTL_RELEASE_R3_P0: |
---|
725 | case L2C_310_RTL_RELEASE_R2_P0: |
---|
726 | case L2C_310_RTL_RELEASE_R1_P0: |
---|
727 | case L2C_310_RTL_RELEASE_R0_P0: |
---|
728 | is_applicable = true; |
---|
729 | break; |
---|
730 | default: |
---|
731 | assert( 0 ); |
---|
732 | break; |
---|
733 | } |
---|
734 | |
---|
735 | return is_applicable; |
---|
736 | } |
---|
737 | |
---|
738 | static bool l2c_310_cache_errata_is_applicable_588369( |
---|
739 | cache_l2c_310_rtl_release rtl_release |
---|
740 | ) |
---|
741 | { |
---|
742 | bool is_applicable = false; |
---|
743 | |
---|
744 | switch ( rtl_release ) { |
---|
745 | case L2C_310_RTL_RELEASE_R3_P3: |
---|
746 | case L2C_310_RTL_RELEASE_R3_P2: |
---|
747 | case L2C_310_RTL_RELEASE_R3_P1: |
---|
748 | case L2C_310_RTL_RELEASE_R3_P0: |
---|
749 | case L2C_310_RTL_RELEASE_R2_P0: |
---|
750 | is_applicable = false; |
---|
751 | break; |
---|
752 | case L2C_310_RTL_RELEASE_R1_P0: |
---|
753 | case L2C_310_RTL_RELEASE_R0_P0: |
---|
754 | is_applicable = true; |
---|
755 | break; |
---|
756 | default: |
---|
757 | assert( 0 ); |
---|
758 | break; |
---|
759 | } |
---|
760 | |
---|
761 | return is_applicable; |
---|
762 | } |
---|
763 | |
---|
764 | #ifdef CACHE_ERRATA_CHECKS_FOR_IMPLEMENTED_ERRATAS |
---|
765 | static bool l2c_310_cache_errata_is_applicable_754670( |
---|
766 | cache_l2c_310_rtl_release rtl_release |
---|
767 | ) |
---|
768 | { |
---|
769 | bool is_applicable = false; |
---|
770 | |
---|
771 | switch ( rtl_release ) { |
---|
772 | case L2C_310_RTL_RELEASE_R3_P3: |
---|
773 | case L2C_310_RTL_RELEASE_R3_P2: |
---|
774 | case L2C_310_RTL_RELEASE_R3_P1: |
---|
775 | case L2C_310_RTL_RELEASE_R3_P0: |
---|
776 | case L2C_310_RTL_RELEASE_R2_P0: |
---|
777 | case L2C_310_RTL_RELEASE_R1_P0: |
---|
778 | case L2C_310_RTL_RELEASE_R0_P0: |
---|
779 | is_applicable = true; |
---|
780 | break; |
---|
781 | default: |
---|
782 | assert( 0 ); |
---|
783 | break; |
---|
784 | } |
---|
785 | |
---|
786 | return is_applicable; |
---|
787 | } |
---|
788 | #endif /* CACHE_ERRATA_CHECKS_FOR_IMPLEMENTED_ERRATAS */ |
---|
789 | |
---|
790 | /* The common workaround for this erratum would be to add a |
---|
791 | * data synchronization barrier to the beginning of the abort handler. |
---|
792 | * But for RTEMS a call of the abort handler means a fatal condition anyway. |
---|
793 | * So there is no need to handle this erratum */ |
---|
794 | #define CACHE_ARM_ERRATA_775420_HANDLER() \ |
---|
795 | if( arm_errata_is_applicable_processor_errata_775420 ) { \ |
---|
796 | } \ |
---|
797 | |
---|
798 | static void l2c_310_cache_check_errata( cache_l2c_310_rtl_release rtl_release ) |
---|
799 | { |
---|
800 | /* This erratum gets handled within the sources */ |
---|
801 | /* Unhandled erratum present: 588369 Errata 588369 says that clean + inv may |
---|
802 | * keep the cache line if it was clean. See ARMs documentation on the erratum |
---|
803 | * for a workaround */ |
---|
804 | /* assert( ! l2c_310_cache_errata_is_applicable_588369( rtl_release ) ); */ |
---|
805 | |
---|
806 | /* Unhandled erratum present: 727913 Prefetch dropping feature can cause |
---|
807 | * incorrect behavior when PL310 handles reads that cross cache line |
---|
808 | * boundary */ |
---|
809 | assert( ! l2c_310_cache_errata_is_applicable_727913( rtl_release ) ); |
---|
810 | |
---|
811 | /* Unhandled erratum present: 727914 Double linefill feature can cause |
---|
812 | * deadlock */ |
---|
813 | assert( ! l2c_310_cache_errata_is_applicable_727914( rtl_release ) ); |
---|
814 | |
---|
815 | /* Unhandled erratum present: 727915 Background Clean and Invalidate by Way |
---|
816 | * operation can cause data corruption */ |
---|
817 | assert( ! l2c_310_cache_errata_is_applicable_727915( rtl_release ) ); |
---|
818 | |
---|
819 | /* Unhandled erratum present: 729806 Speculative reads from the Cortex-A9 |
---|
820 | * MPCore processor can cause deadlock */ |
---|
821 | assert( ! l2c_310_cache_errata_is_applicable_729806( rtl_release ) ); |
---|
822 | |
---|
823 | if( l2c_310_cache_errata_is_applicable_729815( rtl_release ) ) |
---|
824 | { |
---|
825 | volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; |
---|
826 | |
---|
827 | assert( 0 == ( l2cc->aux_ctrl & L2C_310_AUX_HPSODRE_MASK ) ); |
---|
828 | |
---|
829 | /* Erratum: 729815 The âHigh Priority for SO and Dev readsâ feature can |
---|
830 | * cause Quality of Service issues to cacheable read transactions*/ |
---|
831 | |
---|
832 | /* Conditions |
---|
833 | This problem occurs when the following conditions are met: |
---|
834 | 1. Bit[10] âHigh Priority for SO and Dev reads enableâ of the PL310 |
---|
835 | Auxiliary Control Register is set to 1. |
---|
836 | 2. PL310 receives a cacheable read that misses in the L2 cache. |
---|
837 | 3. PL310 receives a continuous flow of Strongly Ordered or Device |
---|
838 | reads that take all address slots in the master interface. |
---|
839 | Workaround |
---|
840 | A workaround is only necessary in systems that are able to issue a |
---|
841 | continuous flow of Strongly Ordered or Device reads. In such a case, |
---|
842 | the workaround is to disable the âHigh Priority for SO and Dev readsâ |
---|
843 | feature. This is the default behavior.*/ |
---|
844 | } |
---|
845 | |
---|
846 | /* Unhandled erratum present: 742884 Double linefill feature might introduce |
---|
847 | * circular dependency and deadlock */ |
---|
848 | assert( ! l2c_310_cache_errata_is_applicable_742884( rtl_release ) ); |
---|
849 | |
---|
850 | /* Unhandled erratum present: 752271 Double linefill feature can cause data |
---|
851 | * corruption */ |
---|
852 | assert( ! l2c_310_cache_errata_is_applicable_752271( rtl_release ) ); |
---|
853 | |
---|
854 | /* This erratum can not be worked around: 754670 A continuous write flow can |
---|
855 | * stall a read targeting the same memory area |
---|
856 | * But this erratum does not lead to any data corruption */ |
---|
857 | /* assert( ! l2c_310_cache_errata_is_applicable_754670() ); */ |
---|
858 | |
---|
859 | if( l2c_310_cache_errata_is_applicable_765569( rtl_release ) ) |
---|
860 | { |
---|
861 | volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; |
---|
862 | |
---|
863 | assert( !( ( l2cc->aux_ctrl & L2C_310_AUX_IPFE_MASK |
---|
864 | || l2cc->aux_ctrl & L2C_310_AUX_DPFE_MASK ) |
---|
865 | && ( ( l2cc->prefetch_ctrl & L2C_310_PREFETCH_OFFSET_MASK ) |
---|
866 | == 23 ) ) ); |
---|
867 | |
---|
868 | /* Unhandled erratum present: 765569 Prefetcher can cross 4KB boundary if |
---|
869 | * offset is programmed with value 23 */ |
---|
870 | |
---|
871 | /* Conditions |
---|
872 | This problem occurs when the following conditions are met: |
---|
873 | 1. One of the Prefetch Enable bits (bits [29:28] of the Auxiliary or |
---|
874 | Prefetch Control Register) is set HIGH. |
---|
875 | 2. The prefetch offset bits are programmed with value 23 (5'b10111). |
---|
876 | Workaround |
---|
877 | A workaround for this erratum is to program the prefetch offset with any |
---|
878 | value except 23.*/ |
---|
879 | } |
---|
880 | |
---|
881 | /* Unhandled erratum present: 769419 No automatic Store Buffer drain, |
---|
882 | * visibility of written data requires an explicit Cache */ |
---|
883 | assert( ! l2c_310_cache_errata_is_applicable_769419( rtl_release ) ); |
---|
884 | } |
---|
885 | |
---|
886 | static inline void |
---|
887 | cache_l2c_310_sync( void ) |
---|
888 | { |
---|
889 | volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; |
---|
890 | cache_l2c_310_rtl_release rtl_release = |
---|
891 | l2cc->cache_id & L2C_310_ID_RTL_MASK; |
---|
892 | |
---|
893 | if( l2c_310_cache_errata_is_applicable_753970( rtl_release ) ) { |
---|
894 | l2cc->dummy_cache_sync_reg = 0; |
---|
895 | } else { |
---|
896 | l2cc->cache_sync = 0; |
---|
897 | } |
---|
898 | } |
---|
899 | |
---|
900 | static inline void |
---|
901 | cache_l2c_310_flush_1_line( |
---|
902 | const void *d_addr, |
---|
903 | const bool is_errata_588369applicable |
---|
904 | ) |
---|
905 | { |
---|
906 | volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; |
---|
907 | |
---|
908 | if( is_errata_588369applicable ) { |
---|
909 | /* |
---|
910 | * Errata 588369 says that clean + inv may keep the |
---|
911 | * cache line if it was clean, the recommended |
---|
912 | * workaround is to clean then invalidate the cache |
---|
913 | * line, with write-back and cache linefill disabled. |
---|
914 | */ |
---|
915 | l2cc->clean_pa = (uint32_t) d_addr; |
---|
916 | cache_l2c_310_sync(); |
---|
917 | l2cc->inv_pa = (uint32_t) d_addr; |
---|
918 | } else { |
---|
919 | l2cc->clean_inv_pa = (uint32_t) d_addr; |
---|
920 | } |
---|
921 | } |
---|
922 | |
---|
923 | static inline void |
---|
924 | cache_l2c_310_flush_range( const void* d_addr, const size_t n_bytes ) |
---|
925 | { |
---|
926 | rtems_interrupt_lock_context lock_context; |
---|
927 | /* Back starting address up to start of a line and invalidate until ADDR_LAST */ |
---|
928 | uint32_t adx = (uint32_t)d_addr |
---|
929 | & ~L2C_310_DATA_LINE_MASK; |
---|
930 | const uint32_t ADDR_LAST = |
---|
931 | (uint32_t)( (size_t)d_addr + n_bytes - 1 ); |
---|
932 | uint32_t block_end = |
---|
933 | L2C_310_MIN( ADDR_LAST, adx + L2C_310_MAX_LOCKING_BYTES ); |
---|
934 | volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; |
---|
935 | cache_l2c_310_rtl_release rtl_release = |
---|
936 | l2cc->cache_id & L2C_310_ID_RTL_MASK; |
---|
937 | bool is_errata_588369_applicable = |
---|
938 | l2c_310_cache_errata_is_applicable_588369( rtl_release ); |
---|
939 | |
---|
940 | rtems_interrupt_lock_acquire( &l2c_310_cache_lock, &lock_context ); |
---|
941 | |
---|
942 | for (; |
---|
943 | adx <= ADDR_LAST; |
---|
944 | adx = block_end + 1, |
---|
945 | block_end = L2C_310_MIN( ADDR_LAST, adx + L2C_310_MAX_LOCKING_BYTES )) { |
---|
946 | for (; adx <= block_end; adx += CPU_DATA_CACHE_ALIGNMENT ) { |
---|
947 | cache_l2c_310_flush_1_line( (void*)adx, is_errata_588369_applicable ); |
---|
948 | } |
---|
949 | if( block_end < ADDR_LAST ) { |
---|
950 | rtems_interrupt_lock_release( &l2c_310_cache_lock, &lock_context ); |
---|
951 | rtems_interrupt_lock_acquire( &l2c_310_cache_lock, &lock_context ); |
---|
952 | } |
---|
953 | } |
---|
954 | cache_l2c_310_sync(); |
---|
955 | rtems_interrupt_lock_release( &l2c_310_cache_lock, &lock_context ); |
---|
956 | } |
---|
957 | |
---|
958 | static inline void |
---|
959 | cache_l2c_310_flush_entire( void ) |
---|
960 | { |
---|
961 | volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; |
---|
962 | rtems_interrupt_lock_context lock_context; |
---|
963 | |
---|
964 | /* Only flush if level 2 cache is active */ |
---|
965 | if( ( l2cc->ctrl & L2C_310_ENABLE_MASK ) != 0 ) { |
---|
966 | |
---|
967 | /* ensure ordering with previous memory accesses */ |
---|
968 | _ARM_Data_memory_barrier(); |
---|
969 | |
---|
970 | rtems_interrupt_lock_acquire( &l2c_310_cache_lock, &lock_context ); |
---|
971 | l2cc->clean_inv_way = L2C_310_WAY_MASK; |
---|
972 | |
---|
973 | while ( l2cc->clean_inv_way & L2C_310_WAY_MASK ) {}; |
---|
974 | |
---|
975 | /* Wait for the flush to complete */ |
---|
976 | cache_l2c_310_sync(); |
---|
977 | |
---|
978 | rtems_interrupt_lock_release( &l2c_310_cache_lock, &lock_context ); |
---|
979 | } |
---|
980 | } |
---|
981 | |
---|
982 | static inline void |
---|
983 | cache_l2c_310_invalidate_1_line( const void *d_addr ) |
---|
984 | { |
---|
985 | volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; |
---|
986 | |
---|
987 | |
---|
988 | l2cc->inv_pa = (uint32_t) d_addr; |
---|
989 | cache_l2c_310_sync(); |
---|
990 | } |
---|
991 | |
---|
992 | static inline void |
---|
993 | cache_l2c_310_invalidate_range( uint32_t adx, const uint32_t ADDR_LAST ) |
---|
994 | { |
---|
995 | volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; |
---|
996 | rtems_interrupt_lock_context lock_context; |
---|
997 | |
---|
998 | rtems_interrupt_lock_acquire( &l2c_310_cache_lock, &lock_context ); |
---|
999 | for (; |
---|
1000 | adx <= ADDR_LAST; |
---|
1001 | adx += CPU_INSTRUCTION_CACHE_ALIGNMENT ) { |
---|
1002 | /* Invalidate L2 cache line */ |
---|
1003 | l2cc->inv_pa = adx; |
---|
1004 | } |
---|
1005 | cache_l2c_310_sync(); |
---|
1006 | rtems_interrupt_lock_release( &l2c_310_cache_lock, &lock_context ); |
---|
1007 | } |
---|
1008 | |
---|
1009 | static inline void |
---|
1010 | cache_l2c_310_invalidate_entire( void ) |
---|
1011 | { |
---|
1012 | volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; |
---|
1013 | |
---|
1014 | /* Invalidate the caches */ |
---|
1015 | |
---|
1016 | /* ensure ordering with previous memory accesses */ |
---|
1017 | _ARM_Data_memory_barrier(); |
---|
1018 | |
---|
1019 | l2cc->inv_way = L2C_310_WAY_MASK; |
---|
1020 | |
---|
1021 | while ( l2cc->inv_way & L2C_310_WAY_MASK ) ; |
---|
1022 | |
---|
1023 | /* Wait for the invalidate to complete */ |
---|
1024 | cache_l2c_310_sync(); |
---|
1025 | } |
---|
1026 | |
---|
1027 | static inline void |
---|
1028 | cache_l2c_310_clean_and_invalidate_entire( void ) |
---|
1029 | { |
---|
1030 | volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; |
---|
1031 | rtems_interrupt_lock_context lock_context; |
---|
1032 | |
---|
1033 | if( ( l2cc->ctrl & L2C_310_ENABLE_MASK ) != 0 ) { |
---|
1034 | /* Invalidate the caches */ |
---|
1035 | |
---|
1036 | /* ensure ordering with previous memory accesses */ |
---|
1037 | _ARM_Data_memory_barrier(); |
---|
1038 | |
---|
1039 | rtems_interrupt_lock_acquire( &l2c_310_cache_lock, &lock_context ); |
---|
1040 | l2cc->clean_inv_way = L2C_310_WAY_MASK; |
---|
1041 | |
---|
1042 | while ( l2cc->clean_inv_way & L2C_310_WAY_MASK ) ; |
---|
1043 | |
---|
1044 | /* Wait for the invalidate to complete */ |
---|
1045 | cache_l2c_310_sync(); |
---|
1046 | |
---|
1047 | rtems_interrupt_lock_release( &l2c_310_cache_lock, &lock_context ); |
---|
1048 | } |
---|
1049 | } |
---|
1050 | |
---|
1051 | static inline void |
---|
1052 | cache_l2c_310_freeze( void ) |
---|
1053 | { |
---|
1054 | /* To be implemented as needed, if supported |
---|
1055 | by hardware at all */ |
---|
1056 | } |
---|
1057 | |
---|
1058 | static inline void |
---|
1059 | cache_l2c_310_unfreeze( void ) |
---|
1060 | { |
---|
1061 | /* To be implemented as needed, if supported |
---|
1062 | by hardware at all */ |
---|
1063 | } |
---|
1064 | |
---|
1065 | static inline size_t |
---|
1066 | cache_l2c_310_get_cache_size( void ) |
---|
1067 | { |
---|
1068 | size_t size = 0; |
---|
1069 | volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; |
---|
1070 | uint32_t cache_type = l2cc->cache_type; |
---|
1071 | uint32_t way_size; |
---|
1072 | uint32_t num_ways; |
---|
1073 | |
---|
1074 | way_size = (cache_type & L2C_310_TYPE_SIZE_D_WAYS_MASK) |
---|
1075 | >> L2C_310_TYPE_SIZE_D_WAYS_SHIFT; |
---|
1076 | num_ways = (cache_type & L2C_310_TYPE_NUM_D_WAYS_MASK) |
---|
1077 | >> L2C_310_TYPE_NUM_D_WAYS_SHIFT; |
---|
1078 | |
---|
1079 | assert( way_size <= 0x07 ); |
---|
1080 | assert( num_ways <= 0x01 ); |
---|
1081 | if( way_size <= 0x07 && num_ways <= 0x01 ) { |
---|
1082 | if( way_size == 0x00 ) { |
---|
1083 | way_size = 16 * 1024; |
---|
1084 | } else if( way_size == 0x07 ) { |
---|
1085 | way_size = 512 * 1024; |
---|
1086 | } else { |
---|
1087 | way_size = (1 << (way_size - 1)) * 16 * 1024; |
---|
1088 | } |
---|
1089 | switch( num_ways ) { |
---|
1090 | case 0: |
---|
1091 | num_ways = 8; |
---|
1092 | break; |
---|
1093 | case 1: |
---|
1094 | num_ways = 16; |
---|
1095 | break; |
---|
1096 | default: |
---|
1097 | num_ways = 0; |
---|
1098 | break; |
---|
1099 | } |
---|
1100 | size = way_size * num_ways; |
---|
1101 | } |
---|
1102 | return size; |
---|
1103 | } |
---|
1104 | |
---|
1105 | static void cache_l2c_310_unlock( volatile L2CC *l2cc ) |
---|
1106 | { |
---|
1107 | l2cc->d_lockdown_0 = 0; |
---|
1108 | l2cc->i_lockdown_0 = 0; |
---|
1109 | l2cc->d_lockdown_1 = 0; |
---|
1110 | l2cc->i_lockdown_1 = 0; |
---|
1111 | l2cc->d_lockdown_2 = 0; |
---|
1112 | l2cc->i_lockdown_2 = 0; |
---|
1113 | l2cc->d_lockdown_3 = 0; |
---|
1114 | l2cc->i_lockdown_3 = 0; |
---|
1115 | l2cc->d_lockdown_4 = 0; |
---|
1116 | l2cc->i_lockdown_4 = 0; |
---|
1117 | l2cc->d_lockdown_5 = 0; |
---|
1118 | l2cc->i_lockdown_5 = 0; |
---|
1119 | l2cc->d_lockdown_6 = 0; |
---|
1120 | l2cc->i_lockdown_6 = 0; |
---|
1121 | l2cc->d_lockdown_7 = 0; |
---|
1122 | l2cc->i_lockdown_7 = 0; |
---|
1123 | } |
---|
1124 | |
---|
1125 | static void cache_l2c_310_wait_for_background_ops( volatile L2CC *l2cc ) |
---|
1126 | { |
---|
1127 | while ( l2cc->inv_way & L2C_310_WAY_MASK ) ; |
---|
1128 | |
---|
1129 | while ( l2cc->clean_way & L2C_310_WAY_MASK ) ; |
---|
1130 | |
---|
1131 | while ( l2cc->clean_inv_way & L2C_310_WAY_MASK ) ; |
---|
1132 | } |
---|
1133 | |
---|
1134 | /* We support only the L2C-310 revisions r3p2 and r3p3 cache controller */ |
---|
1135 | |
---|
1136 | #if (BSP_ARM_L2C_310_ID & L2C_310_ID_PART_MASK) \ |
---|
1137 | != L2C_310_ID_PART_L310 |
---|
1138 | #error "invalid L2-310 cache controller part number" |
---|
1139 | #endif |
---|
1140 | |
---|
1141 | #if ((BSP_ARM_L2C_310_ID & L2C_310_ID_RTL_MASK) != 0x8) \ |
---|
1142 | && ((BSP_ARM_L2C_310_ID & L2C_310_ID_RTL_MASK) != 0x9) |
---|
1143 | #error "invalid L2-310 cache controller RTL revision" |
---|
1144 | #endif |
---|
1145 | |
---|
1146 | static inline void |
---|
1147 | cache_l2c_310_enable( void ) |
---|
1148 | { |
---|
1149 | volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; |
---|
1150 | uint32_t cache_id = l2cc->cache_id; |
---|
1151 | cache_l2c_310_rtl_release rtl_release = |
---|
1152 | cache_id & L2C_310_ID_RTL_MASK; |
---|
1153 | uint32_t id_mask = |
---|
1154 | L2C_310_ID_IMPL_MASK | L2C_310_ID_PART_MASK; |
---|
1155 | |
---|
1156 | /* |
---|
1157 | * Do we actually have an L2C-310 cache controller? Has BSP_ARM_L2C_310_BASE |
---|
1158 | * been configured correctly? |
---|
1159 | */ |
---|
1160 | if ( |
---|
1161 | (BSP_ARM_L2C_310_ID & id_mask) != (cache_id & id_mask) |
---|
1162 | || rtl_release < (BSP_ARM_L2C_310_ID & L2C_310_ID_RTL_MASK) |
---|
1163 | ) { |
---|
1164 | bsp_fatal( ARM_FATAL_L2C_310_UNEXPECTED_ID ); |
---|
1165 | } |
---|
1166 | |
---|
1167 | l2c_310_cache_check_errata( rtl_release ); |
---|
1168 | |
---|
1169 | /* Only enable if L2CC is currently disabled */ |
---|
1170 | if( ( l2cc->ctrl & L2C_310_ENABLE_MASK ) == 0 ) { |
---|
1171 | uint32_t aux_ctrl; |
---|
1172 | int ways; |
---|
1173 | |
---|
1174 | /* Make sure that I&D is not locked down when starting */ |
---|
1175 | cache_l2c_310_unlock( l2cc ); |
---|
1176 | |
---|
1177 | cache_l2c_310_wait_for_background_ops( l2cc ); |
---|
1178 | |
---|
1179 | aux_ctrl = l2cc->aux_ctrl; |
---|
1180 | |
---|
1181 | if ( (aux_ctrl & ( 1 << 16 )) != 0 ) { |
---|
1182 | ways = 16; |
---|
1183 | } else { |
---|
1184 | ways = 8; |
---|
1185 | } |
---|
1186 | |
---|
1187 | if ( ways != L2C_310_NUM_WAYS ) { |
---|
1188 | bsp_fatal( ARM_FATAL_L2C_310_UNEXPECTED_NUM_WAYS ); |
---|
1189 | } |
---|
1190 | |
---|
1191 | /* Set up the way size */ |
---|
1192 | aux_ctrl &= L2C_310_AUX_REG_ZERO_MASK; /* Set way_size to 0 */ |
---|
1193 | aux_ctrl |= L2C_310_AUX_REG_DEFAULT_MASK; |
---|
1194 | |
---|
1195 | l2cc->aux_ctrl = aux_ctrl; |
---|
1196 | |
---|
1197 | /* Set up the latencies */ |
---|
1198 | l2cc->tag_ram_ctrl = L2C_310_TAG_RAM_DEFAULT_LAT; |
---|
1199 | l2cc->data_ram_ctrl = L2C_310_DATA_RAM_DEFAULT_MASK; |
---|
1200 | |
---|
1201 | cache_l2c_310_invalidate_entire(); |
---|
1202 | |
---|
1203 | /* Clear the pending interrupts */ |
---|
1204 | l2cc->int_clr = l2cc->int_raw_status; |
---|
1205 | |
---|
1206 | /* Enable the L2CC */ |
---|
1207 | l2cc->ctrl |= L2C_310_ENABLE_MASK; |
---|
1208 | } |
---|
1209 | } |
---|
1210 | |
---|
1211 | static inline void |
---|
1212 | cache_l2c_310_disable( void ) |
---|
1213 | { |
---|
1214 | volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; |
---|
1215 | rtems_interrupt_lock_context lock_context; |
---|
1216 | |
---|
1217 | if ( l2cc->ctrl & L2C_310_ENABLE_MASK ) { |
---|
1218 | /* Clean and Invalidate L2 Cache */ |
---|
1219 | cache_l2c_310_flush_entire(); |
---|
1220 | rtems_interrupt_lock_acquire( &l2c_310_cache_lock, &lock_context ); |
---|
1221 | |
---|
1222 | cache_l2c_310_wait_for_background_ops( l2cc ); |
---|
1223 | |
---|
1224 | /* Disable the L2 cache */ |
---|
1225 | l2cc->ctrl &= ~L2C_310_ENABLE_MASK; |
---|
1226 | rtems_interrupt_lock_release( &l2c_310_cache_lock, &lock_context ); |
---|
1227 | } |
---|
1228 | } |
---|
1229 | |
---|
1230 | static inline void |
---|
1231 | _CPU_cache_enable_data( void ) |
---|
1232 | { |
---|
1233 | cache_l2c_310_enable(); |
---|
1234 | } |
---|
1235 | |
---|
1236 | static inline void |
---|
1237 | _CPU_cache_disable_data( void ) |
---|
1238 | { |
---|
1239 | arm_cache_l1_disable_data(); |
---|
1240 | cache_l2c_310_disable(); |
---|
1241 | } |
---|
1242 | |
---|
1243 | static inline void |
---|
1244 | _CPU_cache_enable_instruction( void ) |
---|
1245 | { |
---|
1246 | cache_l2c_310_enable(); |
---|
1247 | } |
---|
1248 | |
---|
1249 | static inline void |
---|
1250 | _CPU_cache_disable_instruction( void ) |
---|
1251 | { |
---|
1252 | arm_cache_l1_disable_instruction(); |
---|
1253 | cache_l2c_310_disable(); |
---|
1254 | } |
---|
1255 | |
---|
1256 | static inline void |
---|
1257 | _CPU_cache_flush_data_range( |
---|
1258 | const void *d_addr, |
---|
1259 | size_t n_bytes |
---|
1260 | ) |
---|
1261 | { |
---|
1262 | if ( n_bytes != 0 ) { |
---|
1263 | arm_cache_l1_flush_data_range( |
---|
1264 | d_addr, |
---|
1265 | n_bytes |
---|
1266 | ); |
---|
1267 | cache_l2c_310_flush_range( |
---|
1268 | d_addr, |
---|
1269 | n_bytes |
---|
1270 | ); |
---|
1271 | } |
---|
1272 | } |
---|
1273 | |
---|
1274 | static inline void |
---|
1275 | _CPU_cache_flush_entire_data( void ) |
---|
1276 | { |
---|
1277 | arm_cache_l1_flush_entire_data(); |
---|
1278 | cache_l2c_310_flush_entire(); |
---|
1279 | } |
---|
1280 | |
---|
1281 | static inline void |
---|
1282 | _CPU_cache_invalidate_data_range( |
---|
1283 | const void *addr_first, |
---|
1284 | size_t n_bytes |
---|
1285 | ) |
---|
1286 | { |
---|
1287 | if ( n_bytes > 0 ) { |
---|
1288 | /* Back starting address up to start of a line and invalidate until ADDR_LAST */ |
---|
1289 | uint32_t adx = (uint32_t) addr_first |
---|
1290 | & ~L2C_310_DATA_LINE_MASK; |
---|
1291 | const uint32_t ADDR_LAST = |
---|
1292 | (uint32_t)( (size_t)addr_first + n_bytes - 1 ); |
---|
1293 | uint32_t block_end = |
---|
1294 | L2C_310_MIN( ADDR_LAST, adx + L2C_310_MAX_LOCKING_BYTES ); |
---|
1295 | |
---|
1296 | /* We have to apply a lock. Thus we will operate only L2C_310_MAX_LOCKING_BYTES |
---|
1297 | * at a time */ |
---|
1298 | for (; |
---|
1299 | adx <= ADDR_LAST; |
---|
1300 | adx = block_end + 1, |
---|
1301 | block_end = L2C_310_MIN( ADDR_LAST, adx + L2C_310_MAX_LOCKING_BYTES )) { |
---|
1302 | cache_l2c_310_invalidate_range( |
---|
1303 | adx, |
---|
1304 | block_end |
---|
1305 | ); |
---|
1306 | } |
---|
1307 | arm_cache_l1_invalidate_data_range( |
---|
1308 | addr_first, |
---|
1309 | n_bytes |
---|
1310 | ); |
---|
1311 | |
---|
1312 | adx = (uint32_t)addr_first & ~L2C_310_DATA_LINE_MASK; |
---|
1313 | block_end = L2C_310_MIN( ADDR_LAST, adx + L2C_310_MAX_LOCKING_BYTES ); |
---|
1314 | for (; |
---|
1315 | adx <= ADDR_LAST; |
---|
1316 | adx = block_end + 1, |
---|
1317 | block_end = L2C_310_MIN( ADDR_LAST, adx + L2C_310_MAX_LOCKING_BYTES )) { |
---|
1318 | cache_l2c_310_invalidate_range( |
---|
1319 | adx, |
---|
1320 | block_end |
---|
1321 | ); |
---|
1322 | } |
---|
1323 | arm_cache_l1_invalidate_data_range( |
---|
1324 | addr_first, |
---|
1325 | n_bytes |
---|
1326 | ); |
---|
1327 | } |
---|
1328 | } |
---|
1329 | |
---|
1330 | static inline void |
---|
1331 | _CPU_cache_invalidate_entire_data( void ) |
---|
1332 | { |
---|
1333 | /* This is broadcast within the cluster */ |
---|
1334 | arm_cache_l1_flush_entire_data(); |
---|
1335 | |
---|
1336 | /* forces the address out past level 2 */ |
---|
1337 | cache_l2c_310_clean_and_invalidate_entire(); |
---|
1338 | |
---|
1339 | /*This is broadcast within the cluster */ |
---|
1340 | arm_cache_l1_clean_and_invalidate_entire_data(); |
---|
1341 | } |
---|
1342 | |
---|
1343 | static inline void |
---|
1344 | _CPU_cache_freeze_data( void ) |
---|
1345 | { |
---|
1346 | arm_cache_l1_freeze_data(); |
---|
1347 | cache_l2c_310_freeze(); |
---|
1348 | } |
---|
1349 | |
---|
1350 | static inline void |
---|
1351 | _CPU_cache_unfreeze_data( void ) |
---|
1352 | { |
---|
1353 | arm_cache_l1_unfreeze_data(); |
---|
1354 | cache_l2c_310_unfreeze(); |
---|
1355 | } |
---|
1356 | |
---|
1357 | static inline void |
---|
1358 | _CPU_cache_invalidate_instruction_range( const void *i_addr, size_t n_bytes) |
---|
1359 | { |
---|
1360 | arm_cache_l1_invalidate_instruction_range( i_addr, n_bytes ); |
---|
1361 | } |
---|
1362 | |
---|
1363 | static inline void |
---|
1364 | _CPU_cache_invalidate_entire_instruction( void ) |
---|
1365 | { |
---|
1366 | arm_cache_l1_invalidate_entire_instruction(); |
---|
1367 | } |
---|
1368 | |
---|
1369 | static inline void |
---|
1370 | _CPU_cache_freeze_instruction( void ) |
---|
1371 | { |
---|
1372 | arm_cache_l1_freeze_instruction(); |
---|
1373 | cache_l2c_310_freeze(); |
---|
1374 | } |
---|
1375 | |
---|
1376 | static inline void |
---|
1377 | _CPU_cache_unfreeze_instruction( void ) |
---|
1378 | { |
---|
1379 | arm_cache_l1_unfreeze_instruction(); |
---|
1380 | cache_l2c_310_unfreeze(); |
---|
1381 | } |
---|
1382 | |
---|
1383 | static inline size_t |
---|
1384 | _CPU_cache_get_data_cache_size( const uint32_t level ) |
---|
1385 | { |
---|
1386 | size_t size = 0; |
---|
1387 | |
---|
1388 | switch( level ) |
---|
1389 | { |
---|
1390 | case 1: |
---|
1391 | size = arm_cache_l1_get_data_cache_size(); |
---|
1392 | break; |
---|
1393 | case 0: |
---|
1394 | case 2: |
---|
1395 | size = cache_l2c_310_get_cache_size(); |
---|
1396 | break; |
---|
1397 | default: |
---|
1398 | size = 0; |
---|
1399 | break; |
---|
1400 | } |
---|
1401 | return size; |
---|
1402 | } |
---|
1403 | |
---|
1404 | static inline size_t |
---|
1405 | _CPU_cache_get_instruction_cache_size( const uint32_t level ) |
---|
1406 | { |
---|
1407 | size_t size = 0; |
---|
1408 | |
---|
1409 | switch( level ) |
---|
1410 | { |
---|
1411 | case 1: |
---|
1412 | size = arm_cache_l1_get_instruction_cache_size(); |
---|
1413 | break; |
---|
1414 | case 0: |
---|
1415 | case 2: |
---|
1416 | size = cache_l2c_310_get_cache_size(); |
---|
1417 | break; |
---|
1418 | default: |
---|
1419 | size = 0; |
---|
1420 | break; |
---|
1421 | } |
---|
1422 | return size; |
---|
1423 | } |
---|
1424 | |
---|
1425 | |
---|
1426 | /** @} */ |
---|
1427 | |
---|
1428 | #ifdef __cplusplus |
---|
1429 | } |
---|
1430 | #endif /* __cplusplus */ |
---|
1431 | |
---|
1432 | #endif /* LIBBSP_ARM_SHARED_L2C_310_CACHE_H */ |
---|