1 | /** |
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2 | * @file cache_.h |
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3 | * |
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4 | * @ingroup L2C-310_cache |
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5 | * |
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6 | * @brief Cache definitions and functions. |
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7 | * |
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8 | * This file implements handling for the ARM L2C-310 cache controller |
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9 | */ |
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10 | |
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11 | /* |
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12 | * Authorship |
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13 | * ---------- |
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14 | * This software was created by |
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15 | * R. Claus <claus@slac.stanford.edu>, 2013, |
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16 | * Stanford Linear Accelerator Center, Stanford University. |
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17 | * |
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18 | * Acknowledgement of sponsorship |
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19 | * ------------------------------ |
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20 | * This software was produced by |
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21 | * the Stanford Linear Accelerator Center, Stanford University, |
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22 | * under Contract DE-AC03-76SFO0515 with the Department of Energy. |
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23 | * |
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24 | * Government disclaimer of liability |
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25 | * ---------------------------------- |
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26 | * Neither the United States nor the United States Department of Energy, |
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27 | * nor any of their employees, makes any warranty, express or implied, or |
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28 | * assumes any legal liability or responsibility for the accuracy, |
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29 | * completeness, or usefulness of any data, apparatus, product, or process |
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30 | * disclosed, or represents that its use would not infringe privately owned |
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31 | * rights. |
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32 | * |
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33 | * Stanford disclaimer of liability |
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34 | * -------------------------------- |
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35 | * Stanford University makes no representations or warranties, express or |
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36 | * implied, nor assumes any liability for the use of this software. |
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37 | * |
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38 | * Stanford disclaimer of copyright |
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39 | * -------------------------------- |
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40 | * Stanford University, owner of the copyright, hereby disclaims its |
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41 | * copyright and all other rights in this software. Hence, anyone may |
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42 | * freely use it for any purpose without restriction. |
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43 | * |
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44 | * Maintenance of notices |
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45 | * ---------------------- |
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46 | * In the interest of clarity regarding the origin and status of this |
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47 | * SLAC software, this and all the preceding Stanford University notices |
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48 | * are to remain affixed to any copy or derivative of this software made |
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49 | * or distributed by the recipient and are to be affixed to any copy of |
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50 | * software made or distributed by the recipient that contains a copy or |
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51 | * derivative of this software. |
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52 | * |
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53 | * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 |
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54 | */ |
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55 | |
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56 | #ifndef LIBBSP_ARM_SHARED_L2C_310_CACHE_H |
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57 | #define LIBBSP_ARM_SHARED_L2C_310_CACHE_H |
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58 | |
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59 | #include <assert.h> |
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60 | #include <bsp.h> |
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61 | #include <libcpu/arm-cp15.h> |
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62 | #include <rtems/rtems/intr.h> |
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63 | #include <bsp/arm-release-id.h> |
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64 | #include <bsp/arm-errata.h> |
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65 | #include "../include/arm-cache-l1.h" |
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66 | |
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67 | #ifdef __cplusplus |
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68 | extern "C" { |
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69 | #endif /* __cplusplus */ |
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70 | |
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71 | /* These two defines also ensure that the rtems_cache_* functions have bodies */ |
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72 | #define CPU_DATA_CACHE_ALIGNMENT ARM_CACHE_L1_CPU_DATA_ALIGNMENT |
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73 | #define CPU_INSTRUCTION_CACHE_ALIGNMENT ARM_CACHE_L1_CPU_INSTRUCTION_ALIGNMENT |
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74 | #define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS \ |
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75 | ARM_CACHE_L1_CPU_SUPPORT_PROVIDES_RANGE_FUNCTIONS |
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76 | #define CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS |
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77 | |
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78 | #define CACHE_L2C_310_DATA_LINE_MASK ( CPU_DATA_CACHE_ALIGNMENT - 1 ) |
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79 | #define CACHE_L2C_310_INSTRUCTION_LINE_MASK \ |
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80 | ( CPU_INSTRUCTION_CACHE_ALIGNMENT \ |
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81 | - 1 ) |
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82 | #define CACHE_l2C_310_NUM_WAYS 8 |
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83 | #define CACHE_l2C_310_WAY_MASK ( ( 1 << CACHE_l2C_310_NUM_WAYS ) - 1 ) |
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84 | |
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85 | #define CACHE_MIN( a, b ) \ |
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86 | ((a < b) ? (a) : (b)) |
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87 | |
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88 | #define CACHE_MAX_LOCKING_BYTES (4 * 1024) |
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89 | |
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90 | |
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91 | /* RTL release number as can be read from cache_id register */ |
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92 | typedef enum { |
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93 | CACHE_L2C_310_RTL_RELEASE_R0_P0 = 0x0, |
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94 | CACHE_L2C_310_RTL_RELEASE_R1_P0 = 0x2, |
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95 | CACHE_L2C_310_RTL_RELEASE_R2_P0 = 0x4, |
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96 | CACHE_L2C_310_RTL_RELEASE_R3_P0 = 0x5, |
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97 | CACHE_L2C_310_RTL_RELEASE_R3_P1 = 0x6, |
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98 | CACHE_L2C_310_RTL_RELEASE_R3_P2 = 0x8, |
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99 | CACHE_L2C_310_RTL_RELEASE_R3_P3 = 0x9 |
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100 | } cache_l2c_310_rtl_release; |
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101 | |
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102 | /** |
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103 | * @defgroup L2C-310_cache Cache Support |
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104 | * @ingroup arm_shared |
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105 | * @brief Cache Functions and Defitions |
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106 | * @{ |
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107 | */ |
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108 | |
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109 | |
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110 | /** |
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111 | * @brief L2CC Register Offsets |
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112 | */ |
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113 | typedef struct { |
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114 | /** @brief Cache ID */ |
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115 | uint32_t cache_id; |
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116 | #define CACHE_L2C_310_L2CC_ID_RTL_MASK 0x3f |
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117 | #define CACHE_L2C_310_L2CC_ID_PART_MASK ( 0xf << 6 ) |
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118 | #define CACHE_L2C_310_L2CC_ID_PART_L210 ( 1 << 6 ) |
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119 | #define CACHE_L2C_310_L2CC_ID_PART_L310 ( 3 << 6 ) |
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120 | /** @brief Cache type */ |
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121 | uint32_t cache_type; |
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122 | /** @brief 1 if data banking implemented, 0 if not */ |
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123 | #define CACHE_L2C_310_L2CC_TYPE_DATA_BANKING_MASK 0x80000000 |
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124 | /** @brief 11xy, where: x=1 if pl310_LOCKDOWN_BY_MASTER is defined, otherwise 0 */ |
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125 | #define CACHE_L2C_310_L2CC_TYPE_CTYPE_MASK 0x1E000000 |
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126 | /** @brief y=1 if pl310_LOCKDOWN_BY_LINE is defined, otherwise 0. */ |
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127 | #define CACHE_L2C_310_L2CC_TYPE_CTYPE_SHIFT 25 |
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128 | /** @brief 1 for Harvard architecture, 0 for unified architecture */ |
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129 | #define CACHE_L2C_310_L2CC_TYPE_HARVARD_MASK 0x01000000 |
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130 | /** @brief Data cache way size = 2 Exp(value + 2) KB */ |
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131 | #define CACHE_L2C_310_L2CC_TYPE_SIZE_D_WAYS_MASK 0x00700000 |
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132 | #define CACHE_L2C_310_L2CC_TYPE_SIZE_D_WAYS_SHIFT 20 |
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133 | /** @brief Assoziativity aka number of data ways = (value * 8) + 8 */ |
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134 | #define CACHE_L2C_310_L2CC_TYPE_NUM_D_WAYS_MASK 0x00040000 |
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135 | #define CACHE_L2C_310_L2CC_TYPE_NUM_D_WAYS_SHIFT 18 |
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136 | /** @brief Data cache line length 00 - 32 */ |
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137 | #define CACHE_L2C_310_L2CC_TYPE_LENGTH_D_LINE_MASK 0x00003000 |
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138 | #define CACHE_L2C_310_L2CC_TYPE_LENGTH_D_LINE_SHIFT 12 |
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139 | #define CACHE_L2C_310_L2CC_TYPE_LENGTH_D_LINE_VAL_32 0x0 |
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140 | /** @brief Instruction cache way size = 2 Exp(value + 2) KB */ |
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141 | #define CACHE_L2C_310_L2CC_TYPE_SIZE_I_WAYS_MASK 0x00000700 |
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142 | #define CACHE_L2C_310_L2CC_TYPE_SIZE_I_WAYS_SHIFT 8 |
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143 | /** @brief Assoziativity aka number of instruction ways = (value * 8) + 8 */ |
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144 | #define CACHE_L2C_310_L2CC_TYPE_NUM_I_WAYS_MASK 0x00000040 |
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145 | #define CACHE_L2C_310_L2CC_TYPE_NUM_I_WAYS_SHIFT 6 |
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146 | /** @brief Instruction cache line length 00 - 32 */ |
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147 | #define CACHE_L2C_310_L2CC_TYPE_LENGTH_I_LINE_MASK 0x00000003 |
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148 | #define CACHE_L2C_310_L2CC_TYPE_LENGTH_I_LINE_SHIFT 0 |
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149 | #define CACHE_L2C_310_L2CC_TYPE_LENGTH_I_LINE_VAL_32 0x0 |
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150 | |
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151 | uint8_t reserved_8[0x100 - 8]; |
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152 | uint32_t ctrl; /* Control */ |
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153 | /** @brief Enables the L2CC */ |
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154 | #define CACHE_L2C_310_L2CC_ENABLE_MASK 0x00000001 |
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155 | |
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156 | /** @brief Auxiliary control */ |
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157 | uint32_t aux_ctrl; |
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158 | |
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159 | /** @brief Early BRESP Enable */ |
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160 | #define CACHE_L2C_310_L2CC_AUX_EBRESPE_MASK 0x40000000 |
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161 | |
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162 | /** @brief Instruction Prefetch Enable */ |
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163 | #define CACHE_L2C_310_L2CC_AUX_IPFE_MASK 0x20000000 |
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164 | |
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165 | /** @brief Data Prefetch Enable */ |
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166 | #define CACHE_L2C_310_L2CC_AUX_DPFE_MASK 0x10000000 |
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167 | |
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168 | /** @brief Non-secure interrupt access control */ |
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169 | #define CACHE_L2C_310_L2CC_AUX_NSIC_MASK 0x08000000 |
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170 | |
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171 | /** @brief Non-secure lockdown enable */ |
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172 | #define CACHE_L2C_310_L2CC_AUX_NSLE_MASK 0x04000000 |
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173 | |
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174 | /** @brief Cache replacement policy */ |
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175 | #define CACHE_L2C_310_L2CC_AUX_CRP_MASK 0x02000000 |
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176 | |
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177 | /** @brief Force write allocate */ |
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178 | #define CACHE_L2C_310_L2CC_AUX_FWE_MASK 0x01800000 |
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179 | |
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180 | /** @brief Shared attribute override enable */ |
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181 | #define CACHE_L2C_310_L2CC_AUX_SAOE_MASK 0x00400000 |
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182 | |
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183 | /** @brief Parity enable */ |
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184 | #define CACHE_L2C_310_L2CC_AUX_PE_MASK 0x00200000 |
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185 | |
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186 | /** @brief Event monitor bus enable */ |
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187 | #define CACHE_L2C_310_L2CC_AUX_EMBE_MASK 0x00100000 |
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188 | |
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189 | /** @brief Way-size */ |
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190 | #define CACHE_L2C_310_L2CC_AUX_WAY_SIZE_MASK 0x000E0000 |
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191 | #define CACHE_L2C_310_L2CC_AUX_WAY_SIZE_SHIFT 17 |
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192 | |
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193 | /** @brief Way-size */ |
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194 | #define CACHE_L2C_310_L2CC_AUX_ASSOC_MASK 0x00010000 |
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195 | |
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196 | /** @brief Shared attribute invalidate enable */ |
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197 | #define CACHE_L2C_310_L2CC_AUX_SAIE_MASK 0x00002000 |
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198 | |
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199 | /** @brief Exclusive cache configuration */ |
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200 | #define CACHE_L2C_310_L2CC_AUX_EXCL_CACHE_MASK 0x00001000 |
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201 | |
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202 | /** @brief Store buffer device limitation Enable */ |
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203 | #define CACHE_L2C_310_L2CC_AUX_SBDLE_MASK 0x00000800 |
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204 | |
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205 | /** @brief High Priority for SO and Dev Reads Enable */ |
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206 | #define CACHE_L2C_310_L2CC_AUX_HPSODRE_MASK 0x00000400 |
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207 | |
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208 | /** @brief Full line of zero enable */ |
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209 | #define CACHE_L2C_310_L2CC_AUX_FLZE_MASK 0x00000001 |
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210 | |
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211 | /** @brief Enable all prefetching, */ |
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212 | #define CACHE_L2C_310_L2CC_AUX_REG_DEFAULT_MASK \ |
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213 | ( CACHE_L2C_310_L2CC_AUX_WAY_SIZE_MASK & ( 0x3 << CACHE_L2C_310_L2CC_AUX_WAY_SIZE_SHIFT ) ) \ |
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214 | | CACHE_L2C_310_L2CC_AUX_PE_MASK /* Prefetch enable */ \ |
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215 | | CACHE_L2C_310_L2CC_AUX_SAOE_MASK /* Shared attribute override enable */ \ |
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216 | | CACHE_L2C_310_L2CC_AUX_CRP_MASK /* Cache replacement policy */ \ |
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217 | | CACHE_L2C_310_L2CC_AUX_DPFE_MASK /* Data prefetch enable */ \ |
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218 | | CACHE_L2C_310_L2CC_AUX_IPFE_MASK /* Instruction prefetch enable */ \ |
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219 | | CACHE_L2C_310_L2CC_AUX_EBRESPE_MASK /* Early BRESP enable */ |
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220 | |
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221 | #define CACHE_L2C_310_L2CC_AUX_REG_ZERO_MASK 0xFFF1FFFF |
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222 | |
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223 | /** @brief 1 cycle of latency, there is no additional latency fot tag RAM */ |
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224 | #define CACHE_L2C_310_L2CC_RAM_1_CYCLE_LAT_VAL 0x00000000 |
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225 | /** @brief 2 cycles of latency for tag RAM */ |
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226 | #define CACHE_L2C_310_L2CC_RAM_2_CYCLE_LAT_VAL 0x00000001 |
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227 | /** @brief 3 cycles of latency for tag RAM */ |
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228 | #define CACHE_L2C_310_L2CC_RAM_3_CYCLE_LAT_VAL 0x00000002 |
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229 | /** @brief 4 cycles of latency for tag RAM */ |
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230 | #define CACHE_L2C_310_L2CC_RAM_4_CYCLE_LAT_VAL 0x00000003 |
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231 | /** @brief 5 cycles of latency for tag RAM */ |
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232 | #define CACHE_L2C_310_L2CC_RAM_5_CYCLE_LAT_VAL 0x00000004 |
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233 | /** @brief 6 cycles of latency for tag RAM */ |
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234 | #define CACHE_L2C_310_L2CC_RAM_6_CYCLE_LAT_VAL 0x00000005 |
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235 | /** @brief 7 cycles of latency for tag RAM */ |
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236 | #define CACHE_L2C_310_L2CC_RAM_7_CYCLE_LAT_VAL 0x00000006 |
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237 | /** @brief 8 cycles of latency for tag RAM */ |
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238 | #define CACHE_L2C_310_L2CC_RAM_8_CYCLE_LAT_VAL 0x00000007 |
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239 | /** @brief Shift left setup latency values by this value */ |
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240 | #define CACHE_L2C_310_L2CC_RAM_SETUP_SHIFT 0x00000000 |
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241 | /** @brief Shift left read latency values by this value */ |
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242 | #define CACHE_L2C_310_L2CC_RAM_READ_SHIFT 0x00000004 |
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243 | /** @brief Shift left write latency values by this value */ |
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244 | #define CACHE_L2C_310_L2CC_RAM_WRITE_SHIFT 0x00000008 |
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245 | /** @brief Mask for RAM setup latency */ |
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246 | #define CACHE_L2C_310_L2CC_RAM_SETUP_LAT_MASK 0x00000007 |
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247 | /** @brief Mask for RAM read latency */ |
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248 | #define CACHE_L2C_310_L2CC_RAM_READ_LAT_MASK 0x00000070 |
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249 | /** @brief Mask for RAM read latency */ |
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250 | #define CACHE_L2C_310_L2CC_RAM_WRITE_LAT_MASK 0x00000700 |
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251 | /** @brief Latency for tag RAM */ |
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252 | uint32_t tag_ram_ctrl; |
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253 | /* @brief Latency for tag RAM */ |
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254 | #define CACHE_L2C_310_L2CC_TAG_RAM_DEFAULT_LAT \ |
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255 | ( ( CACHE_L2C_310_L2CC_RAM_2_CYCLE_LAT_VAL << CACHE_L2C_310_L2CC_RAM_SETUP_SHIFT ) \ |
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256 | | ( CACHE_L2C_310_L2CC_RAM_2_CYCLE_LAT_VAL << CACHE_L2C_310_L2CC_RAM_READ_SHIFT ) \ |
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257 | | ( CACHE_L2C_310_L2CC_RAM_2_CYCLE_LAT_VAL << CACHE_L2C_310_L2CC_RAM_WRITE_SHIFT ) ) |
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258 | /** @brief Latency for data RAM */ |
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259 | uint32_t data_ram_ctrl; |
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260 | /** @brief Latency for data RAM */ |
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261 | #define CACHE_L2C_310_L2CC_DATA_RAM_DEFAULT_MASK \ |
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262 | ( ( CACHE_L2C_310_L2CC_RAM_2_CYCLE_LAT_VAL << CACHE_L2C_310_L2CC_RAM_SETUP_SHIFT ) \ |
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263 | | ( CACHE_L2C_310_L2CC_RAM_3_CYCLE_LAT_VAL << CACHE_L2C_310_L2CC_RAM_READ_SHIFT ) \ |
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264 | | ( CACHE_L2C_310_L2CC_RAM_2_CYCLE_LAT_VAL << CACHE_L2C_310_L2CC_RAM_WRITE_SHIFT ) ) |
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265 | |
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266 | uint8_t reserved_110[0x200 - 0x110]; |
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267 | |
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268 | /** @brief Event counter control */ |
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269 | uint32_t ev_ctrl; |
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270 | |
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271 | /** @brief Event counter 1 configuration */ |
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272 | uint32_t ev_cnt1_cfg; |
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273 | |
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274 | /** @brief Event counter 0 configuration */ |
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275 | uint32_t ev_cnt0_cfg; |
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276 | |
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277 | /** @brief Event counter 1 value */ |
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278 | uint32_t ev_cnt1; |
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279 | |
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280 | /** @brief Event counter 0 value */ |
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281 | uint32_t ev_cnt0; |
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282 | |
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283 | /** @brief Interrupt enable mask */ |
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284 | uint32_t int_mask; |
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285 | |
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286 | /** @brief Masked interrupt status (read-only)*/ |
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287 | uint32_t int_mask_status; |
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288 | |
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289 | /** @brief Unmasked interrupt status */ |
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290 | uint32_t int_raw_status; |
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291 | |
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292 | /** @brief Interrupt clear */ |
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293 | uint32_t int_clr; |
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294 | |
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295 | /** |
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296 | * @name Interrupt bit masks |
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297 | * |
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298 | * @{ |
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299 | */ |
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300 | |
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301 | /** @brief DECERR from L3 */ |
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302 | #define CACHE_L2C_310_L2CC_INT_DECERR_MASK 0x00000100 |
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303 | |
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304 | /** @brief SLVERR from L3 */ |
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305 | #define CACHE_L2C_310_L2CC_INT_SLVERR_MASK 0x00000080 |
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306 | |
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307 | /** @brief Error on L2 data RAM (Read) */ |
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308 | #define CACHE_L2C_310_L2CC_INT_ERRRD_MASK 0x00000040 |
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309 | |
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310 | /** @brief Error on L2 tag RAM (Read) */ |
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311 | #define CACHE_L2C_310_L2CC_INT_ERRRT_MASK 0x00000020 |
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312 | |
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313 | /** @brief Error on L2 data RAM (Write) */ |
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314 | #define CACHE_L2C_310_L2CC_INT_ERRWD_MASK 0x00000010 |
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315 | |
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316 | /** @brief Error on L2 tag RAM (Write) */ |
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317 | #define CACHE_L2C_310_L2CC_INT_ERRWT_MASK 0x00000008 |
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318 | |
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319 | /** @brief Parity Error on L2 data RAM (Read) */ |
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320 | #define CACHE_L2C_310_L2CC_INT_PARRD_MASK 0x00000004 |
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321 | |
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322 | /** @brief Parity Error on L2 tag RAM (Read) */ |
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323 | #define CACHE_L2C_310_L2CC_INT_PARRT_MASK 0x00000002 |
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324 | |
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325 | /** @brief Event Counter1/0 Overflow Increment */ |
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326 | #define CACHE_L2C_310_L2CC_INT_ECNTR_MASK 0x00000001 |
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327 | |
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328 | /** @} */ |
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329 | |
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330 | uint8_t reserved_224[0x730 - 0x224]; |
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331 | |
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332 | /** @brief Drain the STB */ |
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333 | uint32_t cache_sync; |
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334 | uint8_t reserved_734[0x740 - 0x734]; |
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335 | /** @brief ARM Errata 753970 for pl310-r3p0 */ |
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336 | uint32_t dummy_cache_sync_reg; |
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337 | uint8_t reserved_744[0x770 - 0x744]; |
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338 | |
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339 | /** @brief Invalidate line by PA */ |
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340 | uint32_t inv_pa; |
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341 | uint8_t reserved_774[0x77c - 0x774]; |
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342 | |
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343 | /** @brief Invalidate by Way */ |
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344 | uint32_t inv_way; |
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345 | uint8_t reserved_780[0x7b0 - 0x780]; |
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346 | |
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347 | /** @brief Clean Line by PA */ |
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348 | uint32_t clean_pa; |
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349 | uint8_t reserved_7b4[0x7b8 - 0x7b4]; |
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350 | |
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351 | /** @brief Clean Line by Set/Way */ |
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352 | uint32_t clean_index; |
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353 | |
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354 | /** @brief Clean by Way */ |
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355 | uint32_t clean_way; |
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356 | uint8_t reserved_7c0[0x7f0 - 0x7c0]; |
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357 | |
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358 | /** @brief Clean and Invalidate Line by PA */ |
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359 | uint32_t clean_inv_pa; |
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360 | uint8_t reserved_7f4[0x7f8 - 0x7f4]; |
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361 | |
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362 | /** @brief Clean and Invalidate Line by Set/Way */ |
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363 | uint32_t clean_inv_indx; |
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364 | |
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365 | /** @brief Clean and Invalidate by Way */ |
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366 | uint32_t clean_inv_way; |
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367 | |
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368 | /** @brief Data lock down 0 */ |
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369 | uint32_t d_lockdown_0; |
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370 | |
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371 | /** @brief Instruction lock down 0 */ |
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372 | uint32_t i_lockdown_0; |
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373 | |
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374 | /** @brief Data lock down 1 */ |
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375 | uint32_t d_lockdown_1; |
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376 | |
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377 | /** @brief Instruction lock down 1 */ |
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378 | uint32_t i_lockdown_1; |
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379 | |
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380 | /** @brief Data lock down 2 */ |
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381 | uint32_t d_lockdown_2; |
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382 | |
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383 | /** @brief Instruction lock down 2 */ |
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384 | uint32_t i_lockdown_2; |
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385 | |
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386 | /** @brief Data lock down 3 */ |
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387 | uint32_t d_lockdown_3; |
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388 | |
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389 | /** @brief Instruction lock down 3 */ |
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390 | uint32_t i_lockdown_3; |
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391 | |
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392 | /** @brief Data lock down 4 */ |
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393 | uint32_t d_lockdown_4; |
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394 | |
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395 | /** @brief Instruction lock down 4 */ |
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396 | uint32_t i_lockdown_4; |
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397 | |
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398 | /** @brief Data lock down 5 */ |
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399 | uint32_t d_lockdown_5; |
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400 | |
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401 | /** @brief Instruction lock down 5 */ |
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402 | uint32_t i_lockdown_5; |
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403 | |
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404 | /** @brief Data lock down 6 */ |
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405 | uint32_t d_lockdown_6; |
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406 | |
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407 | /** @brief Instruction lock down 6 */ |
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408 | uint32_t i_lockdown_6; |
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409 | |
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410 | /** @brief Data lock down 7 */ |
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411 | uint32_t d_lockdown_7; |
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412 | |
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413 | /** @brief Instruction lock down 7 */ |
---|
414 | uint32_t i_lockdown_7; |
---|
415 | |
---|
416 | uint8_t reserved_940[0x950 - 0x940]; |
---|
417 | |
---|
418 | /** @brief Lockdown by Line Enable */ |
---|
419 | uint32_t lock_line_en; |
---|
420 | |
---|
421 | /** @brief Cache lockdown by way */ |
---|
422 | uint32_t unlock_way; |
---|
423 | |
---|
424 | uint8_t reserved_958[0xc00 - 0x958]; |
---|
425 | |
---|
426 | /** @brief Address range redirect, part 1 */ |
---|
427 | uint32_t addr_filtering_start; |
---|
428 | |
---|
429 | /** @brief Address range redirect, part 2 */ |
---|
430 | uint32_t addr_filtering_end; |
---|
431 | |
---|
432 | /** @brief Address filtering valid bits*/ |
---|
433 | #define CACHE_L2C_310_L2CC_ADDR_FILTER_VALID_MASK 0xFFF00000 |
---|
434 | |
---|
435 | /** @brief Address filtering enable bit*/ |
---|
436 | #define CACHE_L2C_310_L2CC_ADDR_FILTER_ENABLE_MASK 0x00000001 |
---|
437 | |
---|
438 | uint8_t reserved_c08[0xf40 - 0xc08]; |
---|
439 | |
---|
440 | /** @brief Debug control */ |
---|
441 | uint32_t debug_ctrl; |
---|
442 | |
---|
443 | /** @brief Debug SPIDEN bit */ |
---|
444 | #define CACHE_L2C_310_L2CC_DEBUG_SPIDEN_MASK 0x00000004 |
---|
445 | |
---|
446 | /** @brief Debug DWB bit, forces write through */ |
---|
447 | #define CACHE_L2C_310_L2CC_DEBUG_DWB_MASK 0x00000002 |
---|
448 | |
---|
449 | /** @brief Debug DCL bit, disables cache line fill */ |
---|
450 | #define CACHE_L2C_310_L2CC_DEBUG_DCL_MASK 0x00000002 |
---|
451 | |
---|
452 | uint8_t reserved_f44[0xf60 - 0xf44]; |
---|
453 | |
---|
454 | /** @brief Purpose prefetch enables */ |
---|
455 | uint32_t prefetch_ctrl; |
---|
456 | /** @brief Prefetch offset */ |
---|
457 | #define CACHE_L2C_310_L2CC_PREFETCH_OFFSET_MASK 0x0000001F |
---|
458 | uint8_t reserved_f64[0xf80 - 0xf64]; |
---|
459 | |
---|
460 | /** @brief Purpose power controls */ |
---|
461 | uint32_t power_ctrl; |
---|
462 | } L2CC; |
---|
463 | |
---|
464 | rtems_interrupt_lock l2c_310_cache_lock = RTEMS_INTERRUPT_LOCK_INITIALIZER( |
---|
465 | "cache" |
---|
466 | ); |
---|
467 | |
---|
468 | /* Errata table for the LC2 310 Level 2 cache from ARM. |
---|
469 | * Information taken from ARMs |
---|
470 | * "CoreLink controllers and peripherals |
---|
471 | * - System controllers |
---|
472 | * - L2C-310 Level 2 Cache Controller |
---|
473 | * - Revision r3p3 |
---|
474 | * - Software Developer Errata Notice |
---|
475 | * - ARM CoreLink Level 2 Cache Controller (L2C-310 or PL310), |
---|
476 | * r3 releases Software Developers Errata Notice" |
---|
477 | * Please see this document for more information on these erratas */ |
---|
478 | static bool l2c_310_cache_errata_is_applicable_753970( |
---|
479 | cache_l2c_310_rtl_release rtl_release |
---|
480 | ) |
---|
481 | { |
---|
482 | bool is_applicable = false; |
---|
483 | |
---|
484 | switch ( rtl_release ) { |
---|
485 | case CACHE_L2C_310_RTL_RELEASE_R3_P3: |
---|
486 | case CACHE_L2C_310_RTL_RELEASE_R3_P2: |
---|
487 | case CACHE_L2C_310_RTL_RELEASE_R3_P1: |
---|
488 | case CACHE_L2C_310_RTL_RELEASE_R2_P0: |
---|
489 | case CACHE_L2C_310_RTL_RELEASE_R1_P0: |
---|
490 | case CACHE_L2C_310_RTL_RELEASE_R0_P0: |
---|
491 | is_applicable = false; |
---|
492 | break; |
---|
493 | case CACHE_L2C_310_RTL_RELEASE_R3_P0: |
---|
494 | is_applicable = true; |
---|
495 | break; |
---|
496 | default: |
---|
497 | assert( 0 ); |
---|
498 | break; |
---|
499 | } |
---|
500 | |
---|
501 | return is_applicable; |
---|
502 | } |
---|
503 | |
---|
504 | static bool l2c_310_cache_errata_is_applicable_727913( |
---|
505 | cache_l2c_310_rtl_release rtl_release |
---|
506 | ) |
---|
507 | { |
---|
508 | bool is_applicable = false; |
---|
509 | |
---|
510 | switch ( rtl_release ) { |
---|
511 | case CACHE_L2C_310_RTL_RELEASE_R3_P3: |
---|
512 | case CACHE_L2C_310_RTL_RELEASE_R3_P2: |
---|
513 | case CACHE_L2C_310_RTL_RELEASE_R3_P1: |
---|
514 | case CACHE_L2C_310_RTL_RELEASE_R2_P0: |
---|
515 | case CACHE_L2C_310_RTL_RELEASE_R1_P0: |
---|
516 | case CACHE_L2C_310_RTL_RELEASE_R0_P0: |
---|
517 | is_applicable = false; |
---|
518 | break; |
---|
519 | case CACHE_L2C_310_RTL_RELEASE_R3_P0: |
---|
520 | is_applicable = true; |
---|
521 | break; |
---|
522 | default: |
---|
523 | assert( 0 ); |
---|
524 | break; |
---|
525 | } |
---|
526 | |
---|
527 | return is_applicable; |
---|
528 | } |
---|
529 | |
---|
530 | static bool l2c_310_cache_errata_is_applicable_727914( |
---|
531 | cache_l2c_310_rtl_release rtl_release |
---|
532 | ) |
---|
533 | { |
---|
534 | bool is_applicable = false; |
---|
535 | |
---|
536 | switch ( rtl_release ) { |
---|
537 | case CACHE_L2C_310_RTL_RELEASE_R3_P3: |
---|
538 | case CACHE_L2C_310_RTL_RELEASE_R3_P2: |
---|
539 | case CACHE_L2C_310_RTL_RELEASE_R3_P1: |
---|
540 | case CACHE_L2C_310_RTL_RELEASE_R2_P0: |
---|
541 | case CACHE_L2C_310_RTL_RELEASE_R1_P0: |
---|
542 | case CACHE_L2C_310_RTL_RELEASE_R0_P0: |
---|
543 | is_applicable = false; |
---|
544 | break; |
---|
545 | case CACHE_L2C_310_RTL_RELEASE_R3_P0: |
---|
546 | is_applicable = true; |
---|
547 | break; |
---|
548 | default: |
---|
549 | assert( 0 ); |
---|
550 | break; |
---|
551 | } |
---|
552 | |
---|
553 | return is_applicable; |
---|
554 | } |
---|
555 | |
---|
556 | static bool l2c_310_cache_errata_is_applicable_727915( |
---|
557 | cache_l2c_310_rtl_release rtl_release |
---|
558 | ) |
---|
559 | { |
---|
560 | bool is_applicable = false; |
---|
561 | |
---|
562 | switch ( rtl_release ) { |
---|
563 | case CACHE_L2C_310_RTL_RELEASE_R3_P3: |
---|
564 | case CACHE_L2C_310_RTL_RELEASE_R3_P2: |
---|
565 | case CACHE_L2C_310_RTL_RELEASE_R3_P1: |
---|
566 | case CACHE_L2C_310_RTL_RELEASE_R1_P0: |
---|
567 | case CACHE_L2C_310_RTL_RELEASE_R0_P0: |
---|
568 | is_applicable = false; |
---|
569 | break; |
---|
570 | case CACHE_L2C_310_RTL_RELEASE_R3_P0: |
---|
571 | case CACHE_L2C_310_RTL_RELEASE_R2_P0: |
---|
572 | is_applicable = true; |
---|
573 | break; |
---|
574 | default: |
---|
575 | assert( 0 ); |
---|
576 | break; |
---|
577 | } |
---|
578 | |
---|
579 | return is_applicable; |
---|
580 | } |
---|
581 | |
---|
582 | static bool l2c_310_cache_errata_is_applicable_729806( |
---|
583 | cache_l2c_310_rtl_release rtl_release |
---|
584 | ) |
---|
585 | { |
---|
586 | bool is_applicable = false; |
---|
587 | |
---|
588 | switch ( rtl_release ) { |
---|
589 | case CACHE_L2C_310_RTL_RELEASE_R3_P3: |
---|
590 | case CACHE_L2C_310_RTL_RELEASE_R3_P2: |
---|
591 | case CACHE_L2C_310_RTL_RELEASE_R2_P0: |
---|
592 | case CACHE_L2C_310_RTL_RELEASE_R1_P0: |
---|
593 | case CACHE_L2C_310_RTL_RELEASE_R0_P0: |
---|
594 | is_applicable = false; |
---|
595 | break; |
---|
596 | case CACHE_L2C_310_RTL_RELEASE_R3_P1: |
---|
597 | case CACHE_L2C_310_RTL_RELEASE_R3_P0: |
---|
598 | is_applicable = true; |
---|
599 | break; |
---|
600 | default: |
---|
601 | assert( 0 ); |
---|
602 | break; |
---|
603 | } |
---|
604 | |
---|
605 | return is_applicable; |
---|
606 | } |
---|
607 | |
---|
608 | static bool l2c_310_cache_errata_is_applicable_729815( |
---|
609 | cache_l2c_310_rtl_release rtl_release |
---|
610 | ) |
---|
611 | { |
---|
612 | bool is_applicable = false; |
---|
613 | |
---|
614 | switch ( rtl_release ) { |
---|
615 | case CACHE_L2C_310_RTL_RELEASE_R3_P3: |
---|
616 | case CACHE_L2C_310_RTL_RELEASE_R1_P0: |
---|
617 | case CACHE_L2C_310_RTL_RELEASE_R0_P0: |
---|
618 | is_applicable = false; |
---|
619 | break; |
---|
620 | case CACHE_L2C_310_RTL_RELEASE_R3_P2: |
---|
621 | case CACHE_L2C_310_RTL_RELEASE_R3_P1: |
---|
622 | case CACHE_L2C_310_RTL_RELEASE_R3_P0: |
---|
623 | case CACHE_L2C_310_RTL_RELEASE_R2_P0: |
---|
624 | is_applicable = true; |
---|
625 | break; |
---|
626 | default: |
---|
627 | assert( 0 ); |
---|
628 | break; |
---|
629 | } |
---|
630 | |
---|
631 | return is_applicable; |
---|
632 | } |
---|
633 | |
---|
634 | static bool l2c_310_cache_errata_is_applicable_742884( |
---|
635 | cache_l2c_310_rtl_release rtl_release |
---|
636 | ) |
---|
637 | { |
---|
638 | bool is_applicable = false; |
---|
639 | |
---|
640 | switch ( rtl_release ) { |
---|
641 | case CACHE_L2C_310_RTL_RELEASE_R3_P3: |
---|
642 | case CACHE_L2C_310_RTL_RELEASE_R3_P2: |
---|
643 | case CACHE_L2C_310_RTL_RELEASE_R3_P0: |
---|
644 | case CACHE_L2C_310_RTL_RELEASE_R2_P0: |
---|
645 | case CACHE_L2C_310_RTL_RELEASE_R1_P0: |
---|
646 | case CACHE_L2C_310_RTL_RELEASE_R0_P0: |
---|
647 | is_applicable = false; |
---|
648 | break; |
---|
649 | case CACHE_L2C_310_RTL_RELEASE_R3_P1: |
---|
650 | is_applicable = true; |
---|
651 | break; |
---|
652 | default: |
---|
653 | assert( 0 ); |
---|
654 | break; |
---|
655 | } |
---|
656 | |
---|
657 | return is_applicable; |
---|
658 | } |
---|
659 | |
---|
660 | static bool l2c_310_cache_errata_is_applicable_752271( |
---|
661 | cache_l2c_310_rtl_release rtl_release |
---|
662 | ) |
---|
663 | { |
---|
664 | bool is_applicable = false; |
---|
665 | |
---|
666 | switch ( rtl_release ) { |
---|
667 | case CACHE_L2C_310_RTL_RELEASE_R3_P3: |
---|
668 | case CACHE_L2C_310_RTL_RELEASE_R3_P2: |
---|
669 | case CACHE_L2C_310_RTL_RELEASE_R2_P0: |
---|
670 | case CACHE_L2C_310_RTL_RELEASE_R1_P0: |
---|
671 | case CACHE_L2C_310_RTL_RELEASE_R0_P0: |
---|
672 | is_applicable = false; |
---|
673 | break; |
---|
674 | case CACHE_L2C_310_RTL_RELEASE_R3_P1: |
---|
675 | case CACHE_L2C_310_RTL_RELEASE_R3_P0: |
---|
676 | is_applicable = true; |
---|
677 | break; |
---|
678 | default: |
---|
679 | assert( 0 ); |
---|
680 | break; |
---|
681 | } |
---|
682 | |
---|
683 | return is_applicable; |
---|
684 | } |
---|
685 | |
---|
686 | static bool l2c_310_cache_errata_is_applicable_765569( |
---|
687 | cache_l2c_310_rtl_release rtl_release |
---|
688 | ) |
---|
689 | { |
---|
690 | bool is_applicable = false; |
---|
691 | |
---|
692 | switch ( rtl_release ) { |
---|
693 | case CACHE_L2C_310_RTL_RELEASE_R3_P3: |
---|
694 | case CACHE_L2C_310_RTL_RELEASE_R3_P2: |
---|
695 | case CACHE_L2C_310_RTL_RELEASE_R3_P1: |
---|
696 | case CACHE_L2C_310_RTL_RELEASE_R3_P0: |
---|
697 | case CACHE_L2C_310_RTL_RELEASE_R2_P0: |
---|
698 | case CACHE_L2C_310_RTL_RELEASE_R1_P0: |
---|
699 | case CACHE_L2C_310_RTL_RELEASE_R0_P0: |
---|
700 | is_applicable = true; |
---|
701 | break; |
---|
702 | default: |
---|
703 | assert( 0 ); |
---|
704 | break; |
---|
705 | } |
---|
706 | |
---|
707 | return is_applicable; |
---|
708 | } |
---|
709 | |
---|
710 | static bool l2c_310_cache_errata_is_applicable_769419( |
---|
711 | cache_l2c_310_rtl_release rtl_release |
---|
712 | ) |
---|
713 | { |
---|
714 | bool is_applicable = false; |
---|
715 | |
---|
716 | switch ( rtl_release ) { |
---|
717 | case CACHE_L2C_310_RTL_RELEASE_R3_P3: |
---|
718 | case CACHE_L2C_310_RTL_RELEASE_R3_P2: |
---|
719 | is_applicable = false; |
---|
720 | break; |
---|
721 | case CACHE_L2C_310_RTL_RELEASE_R3_P1: |
---|
722 | case CACHE_L2C_310_RTL_RELEASE_R3_P0: |
---|
723 | case CACHE_L2C_310_RTL_RELEASE_R2_P0: |
---|
724 | case CACHE_L2C_310_RTL_RELEASE_R1_P0: |
---|
725 | case CACHE_L2C_310_RTL_RELEASE_R0_P0: |
---|
726 | is_applicable = true; |
---|
727 | break; |
---|
728 | default: |
---|
729 | assert( 0 ); |
---|
730 | break; |
---|
731 | } |
---|
732 | |
---|
733 | return is_applicable; |
---|
734 | } |
---|
735 | |
---|
736 | static bool l2c_310_cache_errata_is_applicable_588369( |
---|
737 | cache_l2c_310_rtl_release rtl_release |
---|
738 | ) |
---|
739 | { |
---|
740 | bool is_applicable = false; |
---|
741 | |
---|
742 | switch ( rtl_release ) { |
---|
743 | case CACHE_L2C_310_RTL_RELEASE_R3_P3: |
---|
744 | case CACHE_L2C_310_RTL_RELEASE_R3_P2: |
---|
745 | case CACHE_L2C_310_RTL_RELEASE_R3_P1: |
---|
746 | case CACHE_L2C_310_RTL_RELEASE_R3_P0: |
---|
747 | case CACHE_L2C_310_RTL_RELEASE_R2_P0: |
---|
748 | is_applicable = false; |
---|
749 | break; |
---|
750 | case CACHE_L2C_310_RTL_RELEASE_R1_P0: |
---|
751 | case CACHE_L2C_310_RTL_RELEASE_R0_P0: |
---|
752 | is_applicable = true; |
---|
753 | break; |
---|
754 | default: |
---|
755 | assert( 0 ); |
---|
756 | break; |
---|
757 | } |
---|
758 | |
---|
759 | return is_applicable; |
---|
760 | } |
---|
761 | |
---|
762 | #ifdef CACHE_ERRATA_CHECKS_FOR_IMPLEMENTED_ERRATAS |
---|
763 | static bool l2c_310_cache_errata_is_applicable_754670( |
---|
764 | cache_l2c_310_rtl_release rtl_release |
---|
765 | ) |
---|
766 | { |
---|
767 | bool is_applicable = false; |
---|
768 | |
---|
769 | switch ( rtl_release ) { |
---|
770 | case CACHE_L2C_310_RTL_RELEASE_R3_P3: |
---|
771 | case CACHE_L2C_310_RTL_RELEASE_R3_P2: |
---|
772 | case CACHE_L2C_310_RTL_RELEASE_R3_P1: |
---|
773 | case CACHE_L2C_310_RTL_RELEASE_R3_P0: |
---|
774 | case CACHE_L2C_310_RTL_RELEASE_R2_P0: |
---|
775 | case CACHE_L2C_310_RTL_RELEASE_R1_P0: |
---|
776 | case CACHE_L2C_310_RTL_RELEASE_R0_P0: |
---|
777 | is_applicable = true; |
---|
778 | break; |
---|
779 | default: |
---|
780 | assert( 0 ); |
---|
781 | break; |
---|
782 | } |
---|
783 | |
---|
784 | return is_applicable; |
---|
785 | } |
---|
786 | #endif /* CACHE_ERRATA_CHECKS_FOR_IMPLEMENTED_ERRATAS */ |
---|
787 | |
---|
788 | /* The common workaround for this erratum would be to add a |
---|
789 | * data synchronization barrier to the beginning of the abort handler. |
---|
790 | * But for RTEMS a call of the abort handler means a fatal condition anyway. |
---|
791 | * So there is no need to handle this erratum */ |
---|
792 | #define CACHE_ARM_ERRATA_775420_HANDLER() \ |
---|
793 | if( arm_errata_is_applicable_processor_errata_775420 ) { \ |
---|
794 | } \ |
---|
795 | |
---|
796 | static void l2c_310_cache_check_errata( cache_l2c_310_rtl_release rtl_release ) |
---|
797 | { |
---|
798 | /* This erratum gets handled within the sources */ |
---|
799 | /* Unhandled erratum present: 588369 Errata 588369 says that clean + inv may |
---|
800 | * keep the cache line if it was clean. See ARMs documentation on the erratum |
---|
801 | * for a workaround */ |
---|
802 | /* assert( ! l2c_310_cache_errata_is_applicable_588369( rtl_release ) ); */ |
---|
803 | |
---|
804 | /* Unhandled erratum present: 727913 Prefetch dropping feature can cause |
---|
805 | * incorrect behavior when PL310 handles reads that cross cache line |
---|
806 | * boundary */ |
---|
807 | assert( ! l2c_310_cache_errata_is_applicable_727913( rtl_release ) ); |
---|
808 | |
---|
809 | /* Unhandled erratum present: 727914 Double linefill feature can cause |
---|
810 | * deadlock */ |
---|
811 | assert( ! l2c_310_cache_errata_is_applicable_727914( rtl_release ) ); |
---|
812 | |
---|
813 | /* Unhandled erratum present: 727915 Background Clean and Invalidate by Way |
---|
814 | * operation can cause data corruption */ |
---|
815 | assert( ! l2c_310_cache_errata_is_applicable_727915( rtl_release ) ); |
---|
816 | |
---|
817 | /* Unhandled erratum present: 729806 Speculative reads from the Cortex-A9 |
---|
818 | * MPCore processor can cause deadlock */ |
---|
819 | assert( ! l2c_310_cache_errata_is_applicable_729806( rtl_release ) ); |
---|
820 | |
---|
821 | if( l2c_310_cache_errata_is_applicable_729815( rtl_release ) ) |
---|
822 | { |
---|
823 | volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; |
---|
824 | |
---|
825 | assert( 0 == ( l2cc->aux_ctrl & CACHE_L2C_310_L2CC_AUX_HPSODRE_MASK ) ); |
---|
826 | |
---|
827 | /* Erratum: 729815 The âHigh Priority for SO and Dev readsâ feature can |
---|
828 | * cause Quality of Service issues to cacheable read transactions*/ |
---|
829 | |
---|
830 | /* Conditions |
---|
831 | This problem occurs when the following conditions are met: |
---|
832 | 1. Bit[10] âHigh Priority for SO and Dev reads enableâ of the PL310 |
---|
833 | Auxiliary Control Register is set to 1. |
---|
834 | 2. PL310 receives a cacheable read that misses in the L2 cache. |
---|
835 | 3. PL310 receives a continuous flow of Strongly Ordered or Device |
---|
836 | reads that take all address slots in the master interface. |
---|
837 | Workaround |
---|
838 | A workaround is only necessary in systems that are able to issue a |
---|
839 | continuous flow of Strongly Ordered or Device reads. In such a case, |
---|
840 | the workaround is to disable the âHigh Priority for SO and Dev readsâ |
---|
841 | feature. This is the default behavior.*/ |
---|
842 | } |
---|
843 | |
---|
844 | /* Unhandled erratum present: 742884 Double linefill feature might introduce |
---|
845 | * circular dependency and deadlock */ |
---|
846 | assert( ! l2c_310_cache_errata_is_applicable_742884( rtl_release ) ); |
---|
847 | |
---|
848 | /* Unhandled erratum present: 752271 Double linefill feature can cause data |
---|
849 | * corruption */ |
---|
850 | assert( ! l2c_310_cache_errata_is_applicable_752271( rtl_release ) ); |
---|
851 | |
---|
852 | /* This erratum can not be worked around: 754670 A continuous write flow can |
---|
853 | * stall a read targeting the same memory area |
---|
854 | * But this erratum does not lead to any data corruption */ |
---|
855 | /* assert( ! l2c_310_cache_errata_is_applicable_754670() ); */ |
---|
856 | |
---|
857 | if( l2c_310_cache_errata_is_applicable_765569( rtl_release ) ) |
---|
858 | { |
---|
859 | volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; |
---|
860 | |
---|
861 | assert( !( ( l2cc->aux_ctrl & CACHE_L2C_310_L2CC_AUX_IPFE_MASK |
---|
862 | || l2cc->aux_ctrl & CACHE_L2C_310_L2CC_AUX_DPFE_MASK ) |
---|
863 | && ( ( l2cc->prefetch_ctrl & CACHE_L2C_310_L2CC_PREFETCH_OFFSET_MASK ) |
---|
864 | == 23 ) ) ); |
---|
865 | |
---|
866 | /* Unhandled erratum present: 765569 Prefetcher can cross 4KB boundary if |
---|
867 | * offset is programmed with value 23 */ |
---|
868 | |
---|
869 | /* Conditions |
---|
870 | This problem occurs when the following conditions are met: |
---|
871 | 1. One of the Prefetch Enable bits (bits [29:28] of the Auxiliary or |
---|
872 | Prefetch Control Register) is set HIGH. |
---|
873 | 2. The prefetch offset bits are programmed with value 23 (5'b10111). |
---|
874 | Workaround |
---|
875 | A workaround for this erratum is to program the prefetch offset with any |
---|
876 | value except 23.*/ |
---|
877 | } |
---|
878 | |
---|
879 | /* Unhandled erratum present: 769419 No automatic Store Buffer drain, |
---|
880 | * visibility of written data requires an explicit Cache */ |
---|
881 | assert( ! l2c_310_cache_errata_is_applicable_769419( rtl_release ) ); |
---|
882 | } |
---|
883 | |
---|
884 | static inline void |
---|
885 | cache_l2c_310_sync( void ) |
---|
886 | { |
---|
887 | volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; |
---|
888 | cache_l2c_310_rtl_release rtl_release = |
---|
889 | l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK; |
---|
890 | |
---|
891 | if( l2c_310_cache_errata_is_applicable_753970( rtl_release ) ) { |
---|
892 | l2cc->dummy_cache_sync_reg = 0; |
---|
893 | } else { |
---|
894 | l2cc->cache_sync = 0; |
---|
895 | } |
---|
896 | } |
---|
897 | |
---|
898 | static inline void |
---|
899 | cache_l2c_310_flush_1_line( |
---|
900 | const void *d_addr, |
---|
901 | const bool is_errata_588369applicable |
---|
902 | ) |
---|
903 | { |
---|
904 | volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; |
---|
905 | |
---|
906 | if( is_errata_588369applicable ) { |
---|
907 | /* |
---|
908 | * Errata 588369 says that clean + inv may keep the |
---|
909 | * cache line if it was clean, the recommended |
---|
910 | * workaround is to clean then invalidate the cache |
---|
911 | * line, with write-back and cache linefill disabled. |
---|
912 | */ |
---|
913 | l2cc->clean_pa = (uint32_t) d_addr; |
---|
914 | cache_l2c_310_sync(); |
---|
915 | l2cc->inv_pa = (uint32_t) d_addr; |
---|
916 | } else { |
---|
917 | l2cc->clean_inv_pa = (uint32_t) d_addr; |
---|
918 | } |
---|
919 | } |
---|
920 | |
---|
921 | static inline void |
---|
922 | cache_l2c_310_flush_range( const void* d_addr, const size_t n_bytes ) |
---|
923 | { |
---|
924 | rtems_interrupt_lock_context lock_context; |
---|
925 | /* Back starting address up to start of a line and invalidate until ADDR_LAST */ |
---|
926 | uint32_t adx = (uint32_t)d_addr |
---|
927 | & ~CACHE_L2C_310_DATA_LINE_MASK; |
---|
928 | const uint32_t ADDR_LAST = |
---|
929 | (uint32_t)( (size_t)d_addr + n_bytes - 1 ); |
---|
930 | uint32_t block_end = |
---|
931 | CACHE_MIN( ADDR_LAST, adx + CACHE_MAX_LOCKING_BYTES ); |
---|
932 | volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; |
---|
933 | cache_l2c_310_rtl_release rtl_release = |
---|
934 | l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK; |
---|
935 | bool is_errata_588369_applicable = |
---|
936 | l2c_310_cache_errata_is_applicable_588369( rtl_release ); |
---|
937 | |
---|
938 | rtems_interrupt_lock_acquire( &l2c_310_cache_lock, &lock_context ); |
---|
939 | |
---|
940 | for (; |
---|
941 | adx <= ADDR_LAST; |
---|
942 | adx = block_end + 1, |
---|
943 | block_end = CACHE_MIN( ADDR_LAST, adx + CACHE_MAX_LOCKING_BYTES )) { |
---|
944 | for (; adx <= block_end; adx += CPU_DATA_CACHE_ALIGNMENT ) { |
---|
945 | cache_l2c_310_flush_1_line( (void*)adx, is_errata_588369_applicable ); |
---|
946 | } |
---|
947 | if( block_end < ADDR_LAST ) { |
---|
948 | rtems_interrupt_lock_release( &l2c_310_cache_lock, &lock_context ); |
---|
949 | rtems_interrupt_lock_acquire( &l2c_310_cache_lock, &lock_context ); |
---|
950 | } |
---|
951 | } |
---|
952 | cache_l2c_310_sync(); |
---|
953 | rtems_interrupt_lock_release( &l2c_310_cache_lock, &lock_context ); |
---|
954 | } |
---|
955 | |
---|
956 | static inline void |
---|
957 | cache_l2c_310_flush_entire( void ) |
---|
958 | { |
---|
959 | volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; |
---|
960 | rtems_interrupt_lock_context lock_context; |
---|
961 | |
---|
962 | /* Only flush if level 2 cache is active */ |
---|
963 | if( ( l2cc->ctrl & CACHE_L2C_310_L2CC_ENABLE_MASK ) != 0 ) { |
---|
964 | |
---|
965 | /* ensure ordering with previous memory accesses */ |
---|
966 | _ARM_Data_memory_barrier(); |
---|
967 | |
---|
968 | rtems_interrupt_lock_acquire( &l2c_310_cache_lock, &lock_context ); |
---|
969 | l2cc->clean_inv_way = CACHE_l2C_310_WAY_MASK; |
---|
970 | |
---|
971 | while ( l2cc->clean_inv_way & CACHE_l2C_310_WAY_MASK ) {}; |
---|
972 | |
---|
973 | /* Wait for the flush to complete */ |
---|
974 | cache_l2c_310_sync(); |
---|
975 | |
---|
976 | rtems_interrupt_lock_release( &l2c_310_cache_lock, &lock_context ); |
---|
977 | } |
---|
978 | } |
---|
979 | |
---|
980 | static inline void |
---|
981 | cache_l2c_310_invalidate_1_line( const void *d_addr ) |
---|
982 | { |
---|
983 | volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; |
---|
984 | |
---|
985 | |
---|
986 | l2cc->inv_pa = (uint32_t) d_addr; |
---|
987 | cache_l2c_310_sync(); |
---|
988 | } |
---|
989 | |
---|
990 | static inline void |
---|
991 | cache_l2c_310_invalidate_range( uint32_t adx, const uint32_t ADDR_LAST ) |
---|
992 | { |
---|
993 | volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; |
---|
994 | rtems_interrupt_lock_context lock_context; |
---|
995 | |
---|
996 | rtems_interrupt_lock_acquire( &l2c_310_cache_lock, &lock_context ); |
---|
997 | for (; |
---|
998 | adx <= ADDR_LAST; |
---|
999 | adx += CPU_INSTRUCTION_CACHE_ALIGNMENT ) { |
---|
1000 | /* Invalidate L2 cache line */ |
---|
1001 | l2cc->inv_pa = adx; |
---|
1002 | } |
---|
1003 | cache_l2c_310_sync(); |
---|
1004 | rtems_interrupt_lock_release( &l2c_310_cache_lock, &lock_context ); |
---|
1005 | } |
---|
1006 | |
---|
1007 | static inline void |
---|
1008 | cache_l2c_310_invalidate_entire( void ) |
---|
1009 | { |
---|
1010 | volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; |
---|
1011 | |
---|
1012 | /* Invalidate the caches */ |
---|
1013 | |
---|
1014 | /* ensure ordering with previous memory accesses */ |
---|
1015 | _ARM_Data_memory_barrier(); |
---|
1016 | |
---|
1017 | l2cc->inv_way = CACHE_l2C_310_WAY_MASK; |
---|
1018 | |
---|
1019 | while ( l2cc->inv_way & CACHE_l2C_310_WAY_MASK ) ; |
---|
1020 | |
---|
1021 | /* Wait for the invalidate to complete */ |
---|
1022 | cache_l2c_310_sync(); |
---|
1023 | } |
---|
1024 | |
---|
1025 | static inline void |
---|
1026 | cache_l2c_310_clean_and_invalidate_entire( void ) |
---|
1027 | { |
---|
1028 | volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; |
---|
1029 | rtems_interrupt_lock_context lock_context; |
---|
1030 | |
---|
1031 | if( ( l2cc->ctrl & CACHE_L2C_310_L2CC_ENABLE_MASK ) != 0 ) { |
---|
1032 | /* Invalidate the caches */ |
---|
1033 | |
---|
1034 | /* ensure ordering with previous memory accesses */ |
---|
1035 | _ARM_Data_memory_barrier(); |
---|
1036 | |
---|
1037 | rtems_interrupt_lock_acquire( &l2c_310_cache_lock, &lock_context ); |
---|
1038 | l2cc->clean_inv_way = CACHE_l2C_310_WAY_MASK; |
---|
1039 | |
---|
1040 | while ( l2cc->clean_inv_way & CACHE_l2C_310_WAY_MASK ) ; |
---|
1041 | |
---|
1042 | /* Wait for the invalidate to complete */ |
---|
1043 | cache_l2c_310_sync(); |
---|
1044 | |
---|
1045 | rtems_interrupt_lock_release( &l2c_310_cache_lock, &lock_context ); |
---|
1046 | } |
---|
1047 | } |
---|
1048 | |
---|
1049 | static inline void |
---|
1050 | cache_l2c_310_freeze( void ) |
---|
1051 | { |
---|
1052 | /* To be implemented as needed, if supported |
---|
1053 | by hardware at all */ |
---|
1054 | } |
---|
1055 | |
---|
1056 | static inline void |
---|
1057 | cache_l2c_310_unfreeze( void ) |
---|
1058 | { |
---|
1059 | /* To be implemented as needed, if supported |
---|
1060 | by hardware at all */ |
---|
1061 | } |
---|
1062 | |
---|
1063 | static inline size_t |
---|
1064 | cache_l2c_310_get_cache_size( void ) |
---|
1065 | { |
---|
1066 | size_t size = 0; |
---|
1067 | volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; |
---|
1068 | uint32_t cache_type = l2cc->cache_type; |
---|
1069 | uint32_t way_size; |
---|
1070 | uint32_t num_ways; |
---|
1071 | |
---|
1072 | way_size = (cache_type & CACHE_L2C_310_L2CC_TYPE_SIZE_D_WAYS_MASK) |
---|
1073 | >> CACHE_L2C_310_L2CC_TYPE_SIZE_D_WAYS_SHIFT; |
---|
1074 | num_ways = (cache_type & CACHE_L2C_310_L2CC_TYPE_NUM_D_WAYS_MASK) |
---|
1075 | >> CACHE_L2C_310_L2CC_TYPE_NUM_D_WAYS_SHIFT; |
---|
1076 | |
---|
1077 | assert( way_size <= 0x07 ); |
---|
1078 | assert( num_ways <= 0x01 ); |
---|
1079 | if( way_size <= 0x07 && num_ways <= 0x01 ) { |
---|
1080 | if( way_size == 0x00 ) { |
---|
1081 | way_size = 16 * 1024; |
---|
1082 | } else if( way_size == 0x07 ) { |
---|
1083 | way_size = 512 * 1024; |
---|
1084 | } else { |
---|
1085 | way_size = (1 << (way_size - 1)) * 16 * 1024; |
---|
1086 | } |
---|
1087 | switch( num_ways ) { |
---|
1088 | case 0: |
---|
1089 | num_ways = 8; |
---|
1090 | break; |
---|
1091 | case 1: |
---|
1092 | num_ways = 16; |
---|
1093 | break; |
---|
1094 | default: |
---|
1095 | num_ways = 0; |
---|
1096 | break; |
---|
1097 | } |
---|
1098 | size = way_size * num_ways; |
---|
1099 | } |
---|
1100 | return size; |
---|
1101 | } |
---|
1102 | |
---|
1103 | static void cache_l2c_310_unlock( void ) |
---|
1104 | { |
---|
1105 | volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; |
---|
1106 | |
---|
1107 | |
---|
1108 | l2cc->d_lockdown_0 = 0; |
---|
1109 | l2cc->i_lockdown_0 = 0; |
---|
1110 | l2cc->d_lockdown_1 = 0; |
---|
1111 | l2cc->i_lockdown_1 = 0; |
---|
1112 | l2cc->d_lockdown_2 = 0; |
---|
1113 | l2cc->i_lockdown_2 = 0; |
---|
1114 | l2cc->d_lockdown_3 = 0; |
---|
1115 | l2cc->i_lockdown_3 = 0; |
---|
1116 | l2cc->d_lockdown_4 = 0; |
---|
1117 | l2cc->i_lockdown_4 = 0; |
---|
1118 | l2cc->d_lockdown_5 = 0; |
---|
1119 | l2cc->i_lockdown_5 = 0; |
---|
1120 | l2cc->d_lockdown_6 = 0; |
---|
1121 | l2cc->i_lockdown_6 = 0; |
---|
1122 | l2cc->d_lockdown_7 = 0; |
---|
1123 | l2cc->i_lockdown_7 = 0; |
---|
1124 | } |
---|
1125 | |
---|
1126 | static inline void |
---|
1127 | cache_l2c_310_enable( void ) |
---|
1128 | { |
---|
1129 | volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; |
---|
1130 | cache_l2c_310_rtl_release rtl_release = |
---|
1131 | l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK; |
---|
1132 | |
---|
1133 | /* Only enable if L2CC is currently disabled */ |
---|
1134 | if( ( l2cc->ctrl & CACHE_L2C_310_L2CC_ENABLE_MASK ) == 0 ) { |
---|
1135 | uint32_t cache_id = |
---|
1136 | l2cc->cache_id & CACHE_L2C_310_L2CC_ID_PART_MASK; |
---|
1137 | int ways = 0; |
---|
1138 | |
---|
1139 | /* Do we actually have an L2C-310 cache controller? |
---|
1140 | * Has BSP_ARM_L2C_310_BASE been configured correctly? */ |
---|
1141 | switch ( cache_id ) { |
---|
1142 | case CACHE_L2C_310_L2CC_ID_PART_L310: |
---|
1143 | { |
---|
1144 | /* If this assertion fails, you have a release of the |
---|
1145 | * L2C-310 cache for which the l2c_310_cache_errata_is_applicable_ ... |
---|
1146 | * methods are not yet implemented. This means you will get incorrect |
---|
1147 | * errata handling */ |
---|
1148 | assert( rtl_release == CACHE_L2C_310_RTL_RELEASE_R3_P3 |
---|
1149 | || rtl_release == CACHE_L2C_310_RTL_RELEASE_R3_P2 |
---|
1150 | || rtl_release == CACHE_L2C_310_RTL_RELEASE_R3_P1 |
---|
1151 | || rtl_release == CACHE_L2C_310_RTL_RELEASE_R3_P0 |
---|
1152 | || rtl_release == CACHE_L2C_310_RTL_RELEASE_R2_P0 |
---|
1153 | || rtl_release == CACHE_L2C_310_RTL_RELEASE_R1_P0 |
---|
1154 | || rtl_release == CACHE_L2C_310_RTL_RELEASE_R0_P0 ); |
---|
1155 | if ( l2cc->aux_ctrl & ( 1 << 16 ) ) { |
---|
1156 | ways = 16; |
---|
1157 | } else { |
---|
1158 | ways = 8; |
---|
1159 | } |
---|
1160 | |
---|
1161 | assert( ways == CACHE_l2C_310_NUM_WAYS ); |
---|
1162 | } |
---|
1163 | break; |
---|
1164 | case CACHE_L2C_310_L2CC_ID_PART_L210: |
---|
1165 | |
---|
1166 | /* Invalid case */ |
---|
1167 | |
---|
1168 | /* Support for this type is not implemented in this driver. |
---|
1169 | * Either support needs to get added or a seperate driver needs to get |
---|
1170 | * implemented */ |
---|
1171 | assert( cache_id != CACHE_L2C_310_L2CC_ID_PART_L210 ); |
---|
1172 | break; |
---|
1173 | default: |
---|
1174 | |
---|
1175 | /* Unknown case */ |
---|
1176 | assert( cache_id == CACHE_L2C_310_L2CC_ID_PART_L310 ); |
---|
1177 | break; |
---|
1178 | } |
---|
1179 | |
---|
1180 | if ( ways > 0 ) { |
---|
1181 | uint32_t aux; |
---|
1182 | |
---|
1183 | /* Set up the way size */ |
---|
1184 | aux = l2cc->aux_ctrl; |
---|
1185 | aux &= CACHE_L2C_310_L2CC_AUX_REG_ZERO_MASK; /* Set way_size to 0 */ |
---|
1186 | aux |= CACHE_L2C_310_L2CC_AUX_REG_DEFAULT_MASK; |
---|
1187 | |
---|
1188 | /* Make sure that I&D is not locked down when starting */ |
---|
1189 | cache_l2c_310_unlock(); |
---|
1190 | |
---|
1191 | /* Level 2 configuration and control registers must not get written while |
---|
1192 | * background operations are pending */ |
---|
1193 | while ( l2cc->inv_way & CACHE_l2C_310_WAY_MASK ) ; |
---|
1194 | |
---|
1195 | while ( l2cc->clean_way & CACHE_l2C_310_WAY_MASK ) ; |
---|
1196 | |
---|
1197 | while ( l2cc->clean_inv_way & CACHE_l2C_310_WAY_MASK ) ; |
---|
1198 | |
---|
1199 | l2cc->aux_ctrl = aux; |
---|
1200 | |
---|
1201 | /* Set up the latencies */ |
---|
1202 | l2cc->tag_ram_ctrl = CACHE_L2C_310_L2CC_TAG_RAM_DEFAULT_LAT; |
---|
1203 | l2cc->data_ram_ctrl = CACHE_L2C_310_L2CC_DATA_RAM_DEFAULT_MASK; |
---|
1204 | |
---|
1205 | cache_l2c_310_invalidate_entire(); |
---|
1206 | |
---|
1207 | /* Clear the pending interrupts */ |
---|
1208 | l2cc->int_clr = l2cc->int_raw_status; |
---|
1209 | |
---|
1210 | l2c_310_cache_check_errata( rtl_release ); |
---|
1211 | |
---|
1212 | /* Enable the L2CC */ |
---|
1213 | l2cc->ctrl |= CACHE_L2C_310_L2CC_ENABLE_MASK; |
---|
1214 | } |
---|
1215 | } |
---|
1216 | } |
---|
1217 | |
---|
1218 | static inline void |
---|
1219 | cache_l2c_310_disable( void ) |
---|
1220 | { |
---|
1221 | volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; |
---|
1222 | rtems_interrupt_lock_context lock_context; |
---|
1223 | |
---|
1224 | if ( l2cc->ctrl & CACHE_L2C_310_L2CC_ENABLE_MASK ) { |
---|
1225 | /* Clean and Invalidate L2 Cache */ |
---|
1226 | cache_l2c_310_flush_entire(); |
---|
1227 | rtems_interrupt_lock_acquire( &l2c_310_cache_lock, &lock_context ); |
---|
1228 | |
---|
1229 | /* Level 2 configuration and control registers must not get written while |
---|
1230 | * background operations are pending */ |
---|
1231 | while ( l2cc->inv_way & CACHE_l2C_310_WAY_MASK ) ; |
---|
1232 | |
---|
1233 | while ( l2cc->clean_way & CACHE_l2C_310_WAY_MASK ) ; |
---|
1234 | |
---|
1235 | while ( l2cc->clean_inv_way & CACHE_l2C_310_WAY_MASK ) ; |
---|
1236 | |
---|
1237 | /* Disable the L2 cache */ |
---|
1238 | l2cc->ctrl &= ~CACHE_L2C_310_L2CC_ENABLE_MASK; |
---|
1239 | rtems_interrupt_lock_release( &l2c_310_cache_lock, &lock_context ); |
---|
1240 | } |
---|
1241 | } |
---|
1242 | |
---|
1243 | static inline void |
---|
1244 | _CPU_cache_enable_data( void ) |
---|
1245 | { |
---|
1246 | cache_l2c_310_enable(); |
---|
1247 | } |
---|
1248 | |
---|
1249 | static inline void |
---|
1250 | _CPU_cache_disable_data( void ) |
---|
1251 | { |
---|
1252 | arm_cache_l1_disable_data(); |
---|
1253 | cache_l2c_310_disable(); |
---|
1254 | } |
---|
1255 | |
---|
1256 | static inline void |
---|
1257 | _CPU_cache_enable_instruction( void ) |
---|
1258 | { |
---|
1259 | cache_l2c_310_enable(); |
---|
1260 | } |
---|
1261 | |
---|
1262 | static inline void |
---|
1263 | _CPU_cache_disable_instruction( void ) |
---|
1264 | { |
---|
1265 | arm_cache_l1_disable_instruction(); |
---|
1266 | cache_l2c_310_disable(); |
---|
1267 | } |
---|
1268 | |
---|
1269 | static inline void |
---|
1270 | _CPU_cache_flush_data_range( |
---|
1271 | const void *d_addr, |
---|
1272 | size_t n_bytes |
---|
1273 | ) |
---|
1274 | { |
---|
1275 | if ( n_bytes != 0 ) { |
---|
1276 | arm_cache_l1_flush_data_range( |
---|
1277 | d_addr, |
---|
1278 | n_bytes |
---|
1279 | ); |
---|
1280 | cache_l2c_310_flush_range( |
---|
1281 | d_addr, |
---|
1282 | n_bytes |
---|
1283 | ); |
---|
1284 | } |
---|
1285 | } |
---|
1286 | |
---|
1287 | static inline void |
---|
1288 | _CPU_cache_flush_entire_data( void ) |
---|
1289 | { |
---|
1290 | arm_cache_l1_flush_entire_data(); |
---|
1291 | cache_l2c_310_flush_entire(); |
---|
1292 | } |
---|
1293 | |
---|
1294 | static inline void |
---|
1295 | _CPU_cache_invalidate_data_range( |
---|
1296 | const void *addr_first, |
---|
1297 | size_t n_bytes |
---|
1298 | ) |
---|
1299 | { |
---|
1300 | if ( n_bytes > 0 ) { |
---|
1301 | /* Back starting address up to start of a line and invalidate until ADDR_LAST */ |
---|
1302 | uint32_t adx = (uint32_t) addr_first |
---|
1303 | & ~CACHE_L2C_310_DATA_LINE_MASK; |
---|
1304 | const uint32_t ADDR_LAST = |
---|
1305 | (uint32_t)( (size_t)addr_first + n_bytes - 1 ); |
---|
1306 | uint32_t block_end = |
---|
1307 | CACHE_MIN( ADDR_LAST, adx + CACHE_MAX_LOCKING_BYTES ); |
---|
1308 | |
---|
1309 | /* We have to apply a lock. Thus we will operate only CACHE_MAX_LOCKING_BYTES |
---|
1310 | * at a time */ |
---|
1311 | for (; |
---|
1312 | adx <= ADDR_LAST; |
---|
1313 | adx = block_end + 1, |
---|
1314 | block_end = CACHE_MIN( ADDR_LAST, adx + CACHE_MAX_LOCKING_BYTES )) { |
---|
1315 | cache_l2c_310_invalidate_range( |
---|
1316 | adx, |
---|
1317 | block_end |
---|
1318 | ); |
---|
1319 | } |
---|
1320 | arm_cache_l1_invalidate_data_range( |
---|
1321 | addr_first, |
---|
1322 | n_bytes |
---|
1323 | ); |
---|
1324 | |
---|
1325 | adx = (uint32_t)addr_first & ~CACHE_L2C_310_DATA_LINE_MASK; |
---|
1326 | block_end = CACHE_MIN( ADDR_LAST, adx + CACHE_MAX_LOCKING_BYTES ); |
---|
1327 | for (; |
---|
1328 | adx <= ADDR_LAST; |
---|
1329 | adx = block_end + 1, |
---|
1330 | block_end = CACHE_MIN( ADDR_LAST, adx + CACHE_MAX_LOCKING_BYTES )) { |
---|
1331 | cache_l2c_310_invalidate_range( |
---|
1332 | adx, |
---|
1333 | block_end |
---|
1334 | ); |
---|
1335 | } |
---|
1336 | arm_cache_l1_invalidate_data_range( |
---|
1337 | addr_first, |
---|
1338 | n_bytes |
---|
1339 | ); |
---|
1340 | } |
---|
1341 | } |
---|
1342 | |
---|
1343 | static inline void |
---|
1344 | _CPU_cache_invalidate_entire_data( void ) |
---|
1345 | { |
---|
1346 | /* This is broadcast within the cluster */ |
---|
1347 | arm_cache_l1_flush_entire_data(); |
---|
1348 | |
---|
1349 | /* forces the address out past level 2 */ |
---|
1350 | cache_l2c_310_clean_and_invalidate_entire(); |
---|
1351 | |
---|
1352 | /*This is broadcast within the cluster */ |
---|
1353 | arm_cache_l1_clean_and_invalidate_entire_data(); |
---|
1354 | } |
---|
1355 | |
---|
1356 | static inline void |
---|
1357 | _CPU_cache_freeze_data( void ) |
---|
1358 | { |
---|
1359 | arm_cache_l1_freeze_data(); |
---|
1360 | cache_l2c_310_freeze(); |
---|
1361 | } |
---|
1362 | |
---|
1363 | static inline void |
---|
1364 | _CPU_cache_unfreeze_data( void ) |
---|
1365 | { |
---|
1366 | arm_cache_l1_unfreeze_data(); |
---|
1367 | cache_l2c_310_unfreeze(); |
---|
1368 | } |
---|
1369 | |
---|
1370 | static inline void |
---|
1371 | _CPU_cache_invalidate_instruction_range( const void *i_addr, size_t n_bytes) |
---|
1372 | { |
---|
1373 | arm_cache_l1_invalidate_instruction_range( i_addr, n_bytes ); |
---|
1374 | } |
---|
1375 | |
---|
1376 | static inline void |
---|
1377 | _CPU_cache_invalidate_entire_instruction( void ) |
---|
1378 | { |
---|
1379 | arm_cache_l1_invalidate_entire_instruction(); |
---|
1380 | } |
---|
1381 | |
---|
1382 | static inline void |
---|
1383 | _CPU_cache_freeze_instruction( void ) |
---|
1384 | { |
---|
1385 | arm_cache_l1_freeze_instruction(); |
---|
1386 | cache_l2c_310_freeze(); |
---|
1387 | } |
---|
1388 | |
---|
1389 | static inline void |
---|
1390 | _CPU_cache_unfreeze_instruction( void ) |
---|
1391 | { |
---|
1392 | arm_cache_l1_unfreeze_instruction(); |
---|
1393 | cache_l2c_310_unfreeze(); |
---|
1394 | } |
---|
1395 | |
---|
1396 | static inline size_t |
---|
1397 | _CPU_cache_get_data_cache_size( const uint32_t level ) |
---|
1398 | { |
---|
1399 | size_t size = 0; |
---|
1400 | |
---|
1401 | switch( level ) |
---|
1402 | { |
---|
1403 | case 1: |
---|
1404 | size = arm_cache_l1_get_data_cache_size(); |
---|
1405 | break; |
---|
1406 | case 0: |
---|
1407 | case 2: |
---|
1408 | size = cache_l2c_310_get_cache_size(); |
---|
1409 | break; |
---|
1410 | default: |
---|
1411 | size = 0; |
---|
1412 | break; |
---|
1413 | } |
---|
1414 | return size; |
---|
1415 | } |
---|
1416 | |
---|
1417 | static inline size_t |
---|
1418 | _CPU_cache_get_instruction_cache_size( const uint32_t level ) |
---|
1419 | { |
---|
1420 | size_t size = 0; |
---|
1421 | |
---|
1422 | switch( level ) |
---|
1423 | { |
---|
1424 | case 1: |
---|
1425 | size = arm_cache_l1_get_instruction_cache_size(); |
---|
1426 | break; |
---|
1427 | case 0: |
---|
1428 | case 2: |
---|
1429 | size = cache_l2c_310_get_cache_size(); |
---|
1430 | break; |
---|
1431 | default: |
---|
1432 | size = 0; |
---|
1433 | break; |
---|
1434 | } |
---|
1435 | return size; |
---|
1436 | } |
---|
1437 | |
---|
1438 | |
---|
1439 | /** @} */ |
---|
1440 | |
---|
1441 | #ifdef __cplusplus |
---|
1442 | } |
---|
1443 | #endif /* __cplusplus */ |
---|
1444 | |
---|
1445 | #endif /* LIBBSP_ARM_SHARED_L2C_310_CACHE_H */ |
---|