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source: rtems/c/src/lib/libbsp/arm/shared/arm-l2c-310/cache_.h @ 12ab8d6

4.115

Last change on this file since 12ab8d6 was 12ab8d6, checked in by Sebastian Huber <sebastian.huber@…>, on 09/10/14 at 09:15:44
bsps/arm: Fix get cache size
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File size: 48.5 KB

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1	/**
2	* @file cache_.h
3	*
4	* @ingroup L2C-310_cache
5	*
6	* @brief Cache definitions and functions.
7	*
8	* This file implements handling for the ARM L2C-310 cache controller
9	*/
10
11	/*
12	* Authorship
13	* ----------
14	* This software was created by
15	* R. Claus <claus@slac.stanford.edu>, 2013,
16	* Stanford Linear Accelerator Center, Stanford University.
17	*
18	* Acknowledgement of sponsorship
19	* ------------------------------
20	* This software was produced by
21	* the Stanford Linear Accelerator Center, Stanford University,
22	* under Contract DE-AC03-76SFO0515 with the Department of Energy.
23	*
24	* Government disclaimer of liability
25	* ----------------------------------
26	* Neither the United States nor the United States Department of Energy,
27	* nor any of their employees, makes any warranty, express or implied, or
28	* assumes any legal liability or responsibility for the accuracy,
29	* completeness, or usefulness of any data, apparatus, product, or process
30	* disclosed, or represents that its use would not infringe privately owned
31	* rights.
32	*
33	* Stanford disclaimer of liability
34	* --------------------------------
35	* Stanford University makes no representations or warranties, express or
36	* implied, nor assumes any liability for the use of this software.
37	*
38	* Stanford disclaimer of copyright
39	* --------------------------------
40	* Stanford University, owner of the copyright, hereby disclaims its
41	* copyright and all other rights in this software. Hence, anyone may
42	* freely use it for any purpose without restriction.
43	*
44	* Maintenance of notices
45	* ----------------------
46	* In the interest of clarity regarding the origin and status of this
47	* SLAC software, this and all the preceding Stanford University notices
48	* are to remain affixed to any copy or derivative of this software made
49	* or distributed by the recipient and are to be affixed to any copy of
50	* software made or distributed by the recipient that contains a copy or
51	* derivative of this software.
52	*
53	* ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03
54	*/
55
56	#ifndef LIBBSP_ARM_SHARED_L2C_310_CACHE_H
57	#define LIBBSP_ARM_SHARED_L2C_310_CACHE_H
58
59	#include <assert.h>
60	#include <bsp.h>
61	#include <libcpu/arm-cp15.h>
62	#include <rtems/rtems/intr.h>
63	#include <bsp/arm-release-id.h>
64	#include <bsp/arm-errata.h>
65	#include "../include/arm-cache-l1.h"
66
67	#ifdef __cplusplus
68	extern "C" {
69	#endif /* __cplusplus */
70
71	/* These two defines also ensure that the rtems_cache_* functions have bodies */
72	#define CPU_DATA_CACHE_ALIGNMENT ARM_CACHE_L1_CPU_DATA_ALIGNMENT
73	#define CPU_INSTRUCTION_CACHE_ALIGNMENT ARM_CACHE_L1_CPU_INSTRUCTION_ALIGNMENT
74	#define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS \
75	ARM_CACHE_L1_CPU_SUPPORT_PROVIDES_RANGE_FUNCTIONS
76	#define CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS
77
78	#define CACHE_L2C_310_DATA_LINE_MASK ( CPU_DATA_CACHE_ALIGNMENT - 1 )
79	#define CACHE_L2C_310_INSTRUCTION_LINE_MASK \
80	( CPU_INSTRUCTION_CACHE_ALIGNMENT \
81	- 1 )
82	#define CACHE_l2C_310_NUM_WAYS 8
83	#define CACHE_l2C_310_WAY_MASK ( ( 1 << CACHE_l2C_310_NUM_WAYS ) - 1 )
84
85	#define CACHE_MIN( a, b ) \
86	((a < b) ? (a) : (b))
87
88	#define CACHE_MAX_LOCKING_BYTES (4 * 1024)
89
90
91	/* RTL release number as can be read from cache_id register */
92	typedef enum {
93	CACHE_L2C_310_RTL_RELEASE_R0_P0 = 0x0,
94	CACHE_L2C_310_RTL_RELEASE_R1_P0 = 0x2,
95	CACHE_L2C_310_RTL_RELEASE_R2_P0 = 0x4,
96	CACHE_L2C_310_RTL_RELEASE_R3_P0 = 0x5,
97	CACHE_L2C_310_RTL_RELEASE_R3_P1 = 0x6,
98	CACHE_L2C_310_RTL_RELEASE_R3_P2 = 0x8,
99	CACHE_L2C_310_RTL_RELEASE_R3_P3 = 0x9
100	} cache_l2c_310_rtl_release;
101
102	/**
103	* @defgroup L2C-310_cache Cache Support
104	* @ingroup arm_shared
105	* @brief Cache Functions and Defitions
106	* @{
107	*/
108
109
110	/**
111	* @brief L2CC Register Offsets
112	*/
113	typedef struct {
114	/** @brief Cache ID */
115	uint32_t cache_id;
116	#define CACHE_L2C_310_L2CC_ID_RTL_MASK 0x3f
117	#define CACHE_L2C_310_L2CC_ID_PART_MASK ( 0xf << 6 )
118	#define CACHE_L2C_310_L2CC_ID_PART_L210 ( 1 << 6 )
119	#define CACHE_L2C_310_L2CC_ID_PART_L310 ( 3 << 6 )
120	/** @brief Cache type */
121	uint32_t cache_type;
122	/** @brief 1 if data banking implemented, 0 if not */
123	#define CACHE_L2C_310_L2CC_TYPE_DATA_BANKING_MASK 0x80000000
124	/** @brief 11xy, where: x=1 if pl310_LOCKDOWN_BY_MASTER is defined, otherwise 0 */
125	#define CACHE_L2C_310_L2CC_TYPE_CTYPE_MASK 0x1E000000
126	/** @brief y=1 if pl310_LOCKDOWN_BY_LINE is defined, otherwise 0. */
127	#define CACHE_L2C_310_L2CC_TYPE_CTYPE_SHIFT 25
128	/** @brief 1 for Harvard architecture, 0 for unified architecture */
129	#define CACHE_L2C_310_L2CC_TYPE_HARVARD_MASK 0x01000000
130	/** @brief Data cache way size = 2 Exp(value + 2) KB */
131	#define CACHE_L2C_310_L2CC_TYPE_SIZE_D_WAYS_MASK 0x00700000
132	#define CACHE_L2C_310_L2CC_TYPE_SIZE_D_WAYS_SHIFT 20
133	/** @brief Assoziativity aka number of data ways = (value * 8) + 8 */
134	#define CACHE_L2C_310_L2CC_TYPE_NUM_D_WAYS_MASK 0x00040000
135	#define CACHE_L2C_310_L2CC_TYPE_NUM_D_WAYS_SHIFT 18
136	/** @brief Data cache line length 00 - 32 */
137	#define CACHE_L2C_310_L2CC_TYPE_LENGTH_D_LINE_MASK 0x00003000
138	#define CACHE_L2C_310_L2CC_TYPE_LENGTH_D_LINE_SHIFT 12
139	#define CACHE_L2C_310_L2CC_TYPE_LENGTH_D_LINE_VAL_32 0x0
140	/** @brief Instruction cache way size = 2 Exp(value + 2) KB */
141	#define CACHE_L2C_310_L2CC_TYPE_SIZE_I_WAYS_MASK 0x00000700
142	#define CACHE_L2C_310_L2CC_TYPE_SIZE_I_WAYS_SHIFT 8
143	/** @brief Assoziativity aka number of instruction ways = (value * 8) + 8 */
144	#define CACHE_L2C_310_L2CC_TYPE_NUM_I_WAYS_MASK 0x00000040
145	#define CACHE_L2C_310_L2CC_TYPE_NUM_I_WAYS_SHIFT 6
146	/** @brief Instruction cache line length 00 - 32 */
147	#define CACHE_L2C_310_L2CC_TYPE_LENGTH_I_LINE_MASK 0x00000003
148	#define CACHE_L2C_310_L2CC_TYPE_LENGTH_I_LINE_SHIFT 0
149	#define CACHE_L2C_310_L2CC_TYPE_LENGTH_I_LINE_VAL_32 0x0
150
151	uint8_t reserved_8[0x100 - 8];
152	uint32_t ctrl; /* Control */
153	/** @brief Enables the L2CC */
154	#define CACHE_L2C_310_L2CC_ENABLE_MASK 0x00000001
155
156	/** @brief Auxiliary control */
157	uint32_t aux_ctrl;
158
159	/** @brief Early BRESP Enable */
160	#define CACHE_L2C_310_L2CC_AUX_EBRESPE_MASK 0x40000000
161
162	/** @brief Instruction Prefetch Enable */
163	#define CACHE_L2C_310_L2CC_AUX_IPFE_MASK 0x20000000
164
165	/** @brief Data Prefetch Enable */
166	#define CACHE_L2C_310_L2CC_AUX_DPFE_MASK 0x10000000
167
168	/** @brief Non-secure interrupt access control */
169	#define CACHE_L2C_310_L2CC_AUX_NSIC_MASK 0x08000000
170
171	/** @brief Non-secure lockdown enable */
172	#define CACHE_L2C_310_L2CC_AUX_NSLE_MASK 0x04000000
173
174	/** @brief Cache replacement policy */
175	#define CACHE_L2C_310_L2CC_AUX_CRP_MASK 0x02000000
176
177	/** @brief Force write allocate */
178	#define CACHE_L2C_310_L2CC_AUX_FWE_MASK 0x01800000
179
180	/** @brief Shared attribute override enable */
181	#define CACHE_L2C_310_L2CC_AUX_SAOE_MASK 0x00400000
182
183	/** @brief Parity enable */
184	#define CACHE_L2C_310_L2CC_AUX_PE_MASK 0x00200000
185
186	/** @brief Event monitor bus enable */
187	#define CACHE_L2C_310_L2CC_AUX_EMBE_MASK 0x00100000
188
189	/** @brief Way-size */
190	#define CACHE_L2C_310_L2CC_AUX_WAY_SIZE_MASK 0x000E0000
191	#define CACHE_L2C_310_L2CC_AUX_WAY_SIZE_SHIFT 17
192
193	/** @brief Way-size */
194	#define CACHE_L2C_310_L2CC_AUX_ASSOC_MASK 0x00010000
195
196	/** @brief Shared attribute invalidate enable */
197	#define CACHE_L2C_310_L2CC_AUX_SAIE_MASK 0x00002000
198
199	/** @brief Exclusive cache configuration */
200	#define CACHE_L2C_310_L2CC_AUX_EXCL_CACHE_MASK 0x00001000
201
202	/** @brief Store buffer device limitation Enable */
203	#define CACHE_L2C_310_L2CC_AUX_SBDLE_MASK 0x00000800
204
205	/** @brief High Priority for SO and Dev Reads Enable */
206	#define CACHE_L2C_310_L2CC_AUX_HPSODRE_MASK 0x00000400
207
208	/** @brief Full line of zero enable */
209	#define CACHE_L2C_310_L2CC_AUX_FLZE_MASK 0x00000001
210
211	/** @brief Enable all prefetching, */
212	#define CACHE_L2C_310_L2CC_AUX_REG_DEFAULT_MASK \
213	( CACHE_L2C_310_L2CC_AUX_WAY_SIZE_MASK & ( 0x3 << CACHE_L2C_310_L2CC_AUX_WAY_SIZE_SHIFT ) ) \
214	\| CACHE_L2C_310_L2CC_AUX_PE_MASK /* Prefetch enable */ \
215	\| CACHE_L2C_310_L2CC_AUX_SAOE_MASK /* Shared attribute override enable */ \
216	\| CACHE_L2C_310_L2CC_AUX_CRP_MASK /* Cache replacement policy */ \
217	\| CACHE_L2C_310_L2CC_AUX_DPFE_MASK /* Data prefetch enable */ \
218	\| CACHE_L2C_310_L2CC_AUX_IPFE_MASK /* Instruction prefetch enable */ \
219	\| CACHE_L2C_310_L2CC_AUX_EBRESPE_MASK /* Early BRESP enable */
220
221	#define CACHE_L2C_310_L2CC_AUX_REG_ZERO_MASK 0xFFF1FFFF
222
223	/** @brief 1 cycle of latency, there is no additional latency fot tag RAM */
224	#define CACHE_L2C_310_L2CC_RAM_1_CYCLE_LAT_VAL 0x00000000
225	/** @brief 2 cycles of latency for tag RAM */
226	#define CACHE_L2C_310_L2CC_RAM_2_CYCLE_LAT_VAL 0x00000001
227	/** @brief 3 cycles of latency for tag RAM */
228	#define CACHE_L2C_310_L2CC_RAM_3_CYCLE_LAT_VAL 0x00000002
229	/** @brief 4 cycles of latency for tag RAM */
230	#define CACHE_L2C_310_L2CC_RAM_4_CYCLE_LAT_VAL 0x00000003
231	/** @brief 5 cycles of latency for tag RAM */
232	#define CACHE_L2C_310_L2CC_RAM_5_CYCLE_LAT_VAL 0x00000004
233	/** @brief 6 cycles of latency for tag RAM */
234	#define CACHE_L2C_310_L2CC_RAM_6_CYCLE_LAT_VAL 0x00000005
235	/** @brief 7 cycles of latency for tag RAM */
236	#define CACHE_L2C_310_L2CC_RAM_7_CYCLE_LAT_VAL 0x00000006
237	/** @brief 8 cycles of latency for tag RAM */
238	#define CACHE_L2C_310_L2CC_RAM_8_CYCLE_LAT_VAL 0x00000007
239	/** @brief Shift left setup latency values by this value */
240	#define CACHE_L2C_310_L2CC_RAM_SETUP_SHIFT 0x00000000
241	/** @brief Shift left read latency values by this value */
242	#define CACHE_L2C_310_L2CC_RAM_READ_SHIFT 0x00000004
243	/** @brief Shift left write latency values by this value */
244	#define CACHE_L2C_310_L2CC_RAM_WRITE_SHIFT 0x00000008
245	/** @brief Mask for RAM setup latency */
246	#define CACHE_L2C_310_L2CC_RAM_SETUP_LAT_MASK 0x00000007
247	/** @brief Mask for RAM read latency */
248	#define CACHE_L2C_310_L2CC_RAM_READ_LAT_MASK 0x00000070
249	/** @brief Mask for RAM read latency */
250	#define CACHE_L2C_310_L2CC_RAM_WRITE_LAT_MASK 0x00000700
251	/** @brief Latency for tag RAM */
252	uint32_t tag_ram_ctrl;
253	/* @brief Latency for tag RAM */
254	#define CACHE_L2C_310_L2CC_TAG_RAM_DEFAULT_LAT \
255	( ( CACHE_L2C_310_L2CC_RAM_2_CYCLE_LAT_VAL << CACHE_L2C_310_L2CC_RAM_SETUP_SHIFT ) \
256	\| ( CACHE_L2C_310_L2CC_RAM_2_CYCLE_LAT_VAL << CACHE_L2C_310_L2CC_RAM_READ_SHIFT ) \
257	\| ( CACHE_L2C_310_L2CC_RAM_2_CYCLE_LAT_VAL << CACHE_L2C_310_L2CC_RAM_WRITE_SHIFT ) )
258	/** @brief Latency for data RAM */
259	uint32_t data_ram_ctrl;
260	/** @brief Latency for data RAM */
261	#define CACHE_L2C_310_L2CC_DATA_RAM_DEFAULT_MASK \
262	( ( CACHE_L2C_310_L2CC_RAM_2_CYCLE_LAT_VAL << CACHE_L2C_310_L2CC_RAM_SETUP_SHIFT ) \
263	\| ( CACHE_L2C_310_L2CC_RAM_3_CYCLE_LAT_VAL << CACHE_L2C_310_L2CC_RAM_READ_SHIFT ) \
264	\| ( CACHE_L2C_310_L2CC_RAM_2_CYCLE_LAT_VAL << CACHE_L2C_310_L2CC_RAM_WRITE_SHIFT ) )
265
266	uint8_t reserved_110[0x200 - 0x110];
267
268	/** @brief Event counter control */
269	uint32_t ev_ctrl;
270
271	/** @brief Event counter 1 configuration */
272	uint32_t ev_cnt1_cfg;
273
274	/** @brief Event counter 0 configuration */
275	uint32_t ev_cnt0_cfg;
276
277	/** @brief Event counter 1 value */
278	uint32_t ev_cnt1;
279
280	/** @brief Event counter 0 value */
281	uint32_t ev_cnt0;
282
283	/** @brief Interrupt enable mask */
284	uint32_t int_mask;
285
286	/** @brief Masked interrupt status (read-only)*/
287	uint32_t int_mask_status;
288
289	/** @brief Unmasked interrupt status */
290	uint32_t int_raw_status;
291
292	/** @brief Interrupt clear */
293	uint32_t int_clr;
294
295	/**
296	* @name Interrupt bit masks
297	*
298	* @{
299	*/
300
301	/** @brief DECERR from L3 */
302	#define CACHE_L2C_310_L2CC_INT_DECERR_MASK 0x00000100
303
304	/** @brief SLVERR from L3 */
305	#define CACHE_L2C_310_L2CC_INT_SLVERR_MASK 0x00000080
306
307	/** @brief Error on L2 data RAM (Read) */
308	#define CACHE_L2C_310_L2CC_INT_ERRRD_MASK 0x00000040
309
310	/** @brief Error on L2 tag RAM (Read) */
311	#define CACHE_L2C_310_L2CC_INT_ERRRT_MASK 0x00000020
312
313	/** @brief Error on L2 data RAM (Write) */
314	#define CACHE_L2C_310_L2CC_INT_ERRWD_MASK 0x00000010
315
316	/** @brief Error on L2 tag RAM (Write) */
317	#define CACHE_L2C_310_L2CC_INT_ERRWT_MASK 0x00000008
318
319	/** @brief Parity Error on L2 data RAM (Read) */
320	#define CACHE_L2C_310_L2CC_INT_PARRD_MASK 0x00000004
321
322	/** @brief Parity Error on L2 tag RAM (Read) */
323	#define CACHE_L2C_310_L2CC_INT_PARRT_MASK 0x00000002
324
325	/** @brief Event Counter1/0 Overflow Increment */
326	#define CACHE_L2C_310_L2CC_INT_ECNTR_MASK 0x00000001
327
328	/** @} */
329
330	uint8_t reserved_224[0x730 - 0x224];
331
332	/** @brief Drain the STB */
333	uint32_t cache_sync;
334	uint8_t reserved_734[0x740 - 0x734];
335	/** @brief ARM Errata 753970 for pl310-r3p0 */
336	uint32_t dummy_cache_sync_reg;
337	uint8_t reserved_744[0x770 - 0x744];
338
339	/** @brief Invalidate line by PA */
340	uint32_t inv_pa;
341	uint8_t reserved_774[0x77c - 0x774];
342
343	/** @brief Invalidate by Way */
344	uint32_t inv_way;
345	uint8_t reserved_780[0x7b0 - 0x780];
346
347	/** @brief Clean Line by PA */
348	uint32_t clean_pa;
349	uint8_t reserved_7b4[0x7b8 - 0x7b4];
350
351	/** @brief Clean Line by Set/Way */
352	uint32_t clean_index;
353
354	/** @brief Clean by Way */
355	uint32_t clean_way;
356	uint8_t reserved_7c0[0x7f0 - 0x7c0];
357
358	/** @brief Clean and Invalidate Line by PA */
359	uint32_t clean_inv_pa;
360	uint8_t reserved_7f4[0x7f8 - 0x7f4];
361
362	/** @brief Clean and Invalidate Line by Set/Way */
363	uint32_t clean_inv_indx;
364
365	/** @brief Clean and Invalidate by Way */
366	uint32_t clean_inv_way;
367
368	/** @brief Data lock down 0 */
369	uint32_t d_lockdown_0;
370
371	/** @brief Instruction lock down 0 */
372	uint32_t i_lockdown_0;
373
374	/** @brief Data lock down 1 */
375	uint32_t d_lockdown_1;
376
377	/** @brief Instruction lock down 1 */
378	uint32_t i_lockdown_1;
379
380	/** @brief Data lock down 2 */
381	uint32_t d_lockdown_2;
382
383	/** @brief Instruction lock down 2 */
384	uint32_t i_lockdown_2;
385
386	/** @brief Data lock down 3 */
387	uint32_t d_lockdown_3;
388
389	/** @brief Instruction lock down 3 */
390	uint32_t i_lockdown_3;
391
392	/** @brief Data lock down 4 */
393	uint32_t d_lockdown_4;
394
395	/** @brief Instruction lock down 4 */
396	uint32_t i_lockdown_4;
397
398	/** @brief Data lock down 5 */
399	uint32_t d_lockdown_5;
400
401	/** @brief Instruction lock down 5 */
402	uint32_t i_lockdown_5;
403
404	/** @brief Data lock down 6 */
405	uint32_t d_lockdown_6;
406
407	/** @brief Instruction lock down 6 */
408	uint32_t i_lockdown_6;
409
410	/** @brief Data lock down 7 */
411	uint32_t d_lockdown_7;
412
413	/** @brief Instruction lock down 7 */
414	uint32_t i_lockdown_7;
415
416	uint8_t reserved_940[0x950 - 0x940];
417
418	/** @brief Lockdown by Line Enable */
419	uint32_t lock_line_en;
420
421	/** @brief Cache lockdown by way */
422	uint32_t unlock_way;
423
424	uint8_t reserved_958[0xc00 - 0x958];
425
426	/** @brief Address range redirect, part 1 */
427	uint32_t addr_filtering_start;
428
429	/** @brief Address range redirect, part 2 */
430	uint32_t addr_filtering_end;
431
432	/** @brief Address filtering valid bits*/
433	#define CACHE_L2C_310_L2CC_ADDR_FILTER_VALID_MASK 0xFFF00000
434
435	/** @brief Address filtering enable bit*/
436	#define CACHE_L2C_310_L2CC_ADDR_FILTER_ENABLE_MASK 0x00000001
437
438	uint8_t reserved_c08[0xf40 - 0xc08];
439
440	/** @brief Debug control */
441	uint32_t debug_ctrl;
442
443	/** @brief Debug SPIDEN bit */
444	#define CACHE_L2C_310_L2CC_DEBUG_SPIDEN_MASK 0x00000004
445
446	/** @brief Debug DWB bit, forces write through */
447	#define CACHE_L2C_310_L2CC_DEBUG_DWB_MASK 0x00000002
448
449	/** @brief Debug DCL bit, disables cache line fill */
450	#define CACHE_L2C_310_L2CC_DEBUG_DCL_MASK 0x00000002
451
452	uint8_t reserved_f44[0xf60 - 0xf44];
453
454	/** @brief Purpose prefetch enables */
455	uint32_t prefetch_ctrl;
456	/** @brief Prefetch offset */
457	#define CACHE_L2C_310_L2CC_PREFETCH_OFFSET_MASK 0x0000001F
458	uint8_t reserved_f64[0xf80 - 0xf64];
459
460	/** @brief Purpose power controls */
461	uint32_t power_ctrl;
462	} L2CC;
463
464	rtems_interrupt_lock l2c_310_cache_lock = RTEMS_INTERRUPT_LOCK_INITIALIZER(
465	"cache"
466	);
467
468	/* Errata table for the LC2 310 Level 2 cache from ARM.
469	* Information taken from ARMs
470	* "CoreLink controllers and peripherals
471	* - System controllers
472	* - L2C-310 Level 2 Cache Controller
473	* - Revision r3p3
474	* - Software Developer Errata Notice
475	* - ARM CoreLink Level 2 Cache Controller (L2C-310 or PL310),
476	* r3 releases Software Developers Errata Notice"
477	* The corresponding link is:
478	* http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0360f/BABJFIBA.html
479	* Please see this document for more information on these erratas */
480	static bool l2c_310_cache_errata_is_applicable_753970(
481	void
482	)
483	{
484	volatile L2CC *l2cc =
485	(volatile L2CC *) BSP_ARM_L2CC_BASE;
486	const cache_l2c_310_rtl_release RTL_RELEASE =
487	l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;
488	bool is_applicable = false;
489
490	switch( RTL_RELEASE ) {
491	case CACHE_L2C_310_RTL_RELEASE_R3_P3:
492	case CACHE_L2C_310_RTL_RELEASE_R3_P2:
493	case CACHE_L2C_310_RTL_RELEASE_R3_P1:
494	case CACHE_L2C_310_RTL_RELEASE_R2_P0:
495	case CACHE_L2C_310_RTL_RELEASE_R1_P0:
496	case CACHE_L2C_310_RTL_RELEASE_R0_P0:
497	is_applicable = false;
498	break;
499	case CACHE_L2C_310_RTL_RELEASE_R3_P0:
500	is_applicable = true;
501	break;
502	default:
503	assert( RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P3
504	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P2
505	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P1
506	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P0
507	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R2_P0
508	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R1_P0
509	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R0_P0 );
510	break;
511	}
512
513	return is_applicable;
514	}
515
516	static bool l2c_310_cache_errata_is_applicable_727913(
517	void
518	)
519	{
520	volatile L2CC *l2cc =
521	(volatile L2CC *) BSP_ARM_L2CC_BASE;
522	const cache_l2c_310_rtl_release RTL_RELEASE =
523	l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;
524	bool is_applicable = false;
525
526	switch( RTL_RELEASE ) {
527	case CACHE_L2C_310_RTL_RELEASE_R3_P3:
528	case CACHE_L2C_310_RTL_RELEASE_R3_P2:
529	case CACHE_L2C_310_RTL_RELEASE_R3_P1:
530	case CACHE_L2C_310_RTL_RELEASE_R2_P0:
531	case CACHE_L2C_310_RTL_RELEASE_R1_P0:
532	case CACHE_L2C_310_RTL_RELEASE_R0_P0:
533	is_applicable = false;
534	break;
535	case CACHE_L2C_310_RTL_RELEASE_R3_P0:
536	is_applicable = true;
537	break;
538	default:
539	assert( RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P3
540	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P2
541	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P1
542	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P0
543	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R2_P0
544	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R1_P0
545	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R0_P0 );
546	break;
547	}
548
549	return is_applicable;
550	}
551
552	static bool l2c_310_cache_errata_is_applicable_727914(
553	void
554	)
555	{
556	volatile L2CC *l2cc =
557	(volatile L2CC *) BSP_ARM_L2CC_BASE;
558	const cache_l2c_310_rtl_release RTL_RELEASE =
559	l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;
560	bool is_applicable = false;
561
562	switch( RTL_RELEASE ) {
563	case CACHE_L2C_310_RTL_RELEASE_R3_P3:
564	case CACHE_L2C_310_RTL_RELEASE_R3_P2:
565	case CACHE_L2C_310_RTL_RELEASE_R3_P1:
566	case CACHE_L2C_310_RTL_RELEASE_R2_P0:
567	case CACHE_L2C_310_RTL_RELEASE_R1_P0:
568	case CACHE_L2C_310_RTL_RELEASE_R0_P0:
569	is_applicable = false;
570	break;
571	case CACHE_L2C_310_RTL_RELEASE_R3_P0:
572	is_applicable = true;
573	break;
574	default:
575	assert( RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P3
576	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P2
577	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P1
578	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P0
579	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R2_P0
580	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R1_P0
581	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R0_P0 );
582	break;
583	}
584
585	return is_applicable;
586	}
587
588	static bool l2c_310_cache_errata_is_applicable_727915(
589	void
590	)
591	{
592	volatile L2CC *l2cc =
593	(volatile L2CC *) BSP_ARM_L2CC_BASE;
594	const cache_l2c_310_rtl_release RTL_RELEASE =
595	l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;
596	bool is_applicable = false;
597
598	switch( RTL_RELEASE ) {
599	case CACHE_L2C_310_RTL_RELEASE_R3_P3:
600	case CACHE_L2C_310_RTL_RELEASE_R3_P2:
601	case CACHE_L2C_310_RTL_RELEASE_R3_P1:
602	case CACHE_L2C_310_RTL_RELEASE_R1_P0:
603	case CACHE_L2C_310_RTL_RELEASE_R0_P0:
604	is_applicable = false;
605	break;
606	case CACHE_L2C_310_RTL_RELEASE_R3_P0:
607	case CACHE_L2C_310_RTL_RELEASE_R2_P0:
608	is_applicable = true;
609	break;
610	default:
611	assert( RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P3
612	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P2
613	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P1
614	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P0
615	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R2_P0
616	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R1_P0
617	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R0_P0 );
618	break;
619	}
620
621	return is_applicable;
622	}
623
624	static bool l2c_310_cache_errata_is_applicable_729806(
625	void
626	)
627	{
628	volatile L2CC *l2cc =
629	(volatile L2CC *) BSP_ARM_L2CC_BASE;
630	const cache_l2c_310_rtl_release RTL_RELEASE =
631	l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;
632	bool is_applicable = false;
633
634	switch( RTL_RELEASE ) {
635	case CACHE_L2C_310_RTL_RELEASE_R3_P3:
636	case CACHE_L2C_310_RTL_RELEASE_R3_P2:
637	case CACHE_L2C_310_RTL_RELEASE_R2_P0:
638	case CACHE_L2C_310_RTL_RELEASE_R1_P0:
639	case CACHE_L2C_310_RTL_RELEASE_R0_P0:
640	is_applicable = false;
641	break;
642	case CACHE_L2C_310_RTL_RELEASE_R3_P1:
643	case CACHE_L2C_310_RTL_RELEASE_R3_P0:
644	is_applicable = true;
645	break;
646	default:
647	assert( RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P3
648	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P2
649	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P1
650	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P0
651	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R2_P0
652	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R1_P0
653	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R0_P0 );
654	break;
655	}
656
657	return is_applicable;
658	}
659
660	static bool l2c_310_cache_errata_is_applicable_729815(
661	void
662	)
663	{
664	volatile L2CC *l2cc =
665	(volatile L2CC *) BSP_ARM_L2CC_BASE;
666	const cache_l2c_310_rtl_release RTL_RELEASE =
667	l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;
668	bool is_applicable = false;
669
670	switch( RTL_RELEASE ) {
671	case CACHE_L2C_310_RTL_RELEASE_R3_P3:
672	case CACHE_L2C_310_RTL_RELEASE_R1_P0:
673	case CACHE_L2C_310_RTL_RELEASE_R0_P0:
674	is_applicable = false;
675	break;
676	case CACHE_L2C_310_RTL_RELEASE_R3_P2:
677	case CACHE_L2C_310_RTL_RELEASE_R3_P1:
678	case CACHE_L2C_310_RTL_RELEASE_R3_P0:
679	case CACHE_L2C_310_RTL_RELEASE_R2_P0:
680	is_applicable = true;
681	break;
682	default:
683	assert( RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P3
684	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P2
685	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P1
686	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P0
687	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R2_P0
688	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R1_P0
689	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R0_P0 );
690	break;
691	}
692
693	return is_applicable;
694	}
695
696	static bool l2c_310_cache_errata_is_applicable_742884(
697	void
698	)
699	{
700	volatile L2CC *l2cc =
701	(volatile L2CC *) BSP_ARM_L2CC_BASE;
702	const cache_l2c_310_rtl_release RTL_RELEASE =
703	l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;
704	bool is_applicable = false;
705
706	switch( RTL_RELEASE ) {
707	case CACHE_L2C_310_RTL_RELEASE_R3_P3:
708	case CACHE_L2C_310_RTL_RELEASE_R3_P2:
709	case CACHE_L2C_310_RTL_RELEASE_R3_P0:
710	case CACHE_L2C_310_RTL_RELEASE_R2_P0:
711	case CACHE_L2C_310_RTL_RELEASE_R1_P0:
712	case CACHE_L2C_310_RTL_RELEASE_R0_P0:
713	is_applicable = false;
714	break;
715	case CACHE_L2C_310_RTL_RELEASE_R3_P1:
716	is_applicable = true;
717	break;
718	default:
719	assert( RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P3
720	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P2
721	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P1
722	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P0
723	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R2_P0
724	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R1_P0
725	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R0_P0 );
726	break;
727	}
728
729	return is_applicable;
730	}
731
732	static bool l2c_310_cache_errata_is_applicable_752271(
733	void
734	)
735	{
736	volatile L2CC *l2cc =
737	(volatile L2CC *) BSP_ARM_L2CC_BASE;
738	const cache_l2c_310_rtl_release RTL_RELEASE =
739	l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;
740	bool is_applicable = false;
741
742	switch( RTL_RELEASE ) {
743	case CACHE_L2C_310_RTL_RELEASE_R3_P3:
744	case CACHE_L2C_310_RTL_RELEASE_R3_P2:
745	case CACHE_L2C_310_RTL_RELEASE_R2_P0:
746	case CACHE_L2C_310_RTL_RELEASE_R1_P0:
747	case CACHE_L2C_310_RTL_RELEASE_R0_P0:
748	is_applicable = false;
749	break;
750	case CACHE_L2C_310_RTL_RELEASE_R3_P1:
751	case CACHE_L2C_310_RTL_RELEASE_R3_P0:
752	is_applicable = true;
753	break;
754	default:
755	assert( RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P3
756	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P2
757	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P1
758	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P0
759	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R2_P0
760	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R1_P0
761	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R0_P0 );
762	break;
763	}
764
765	return is_applicable;
766	}
767
768	static bool l2c_310_cache_errata_is_applicable_765569(
769	void
770	)
771	{
772	volatile L2CC *l2cc =
773	(volatile L2CC *) BSP_ARM_L2CC_BASE;
774	const cache_l2c_310_rtl_release RTL_RELEASE =
775	l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;
776	bool is_applicable = false;
777
778	switch( RTL_RELEASE ) {
779	case CACHE_L2C_310_RTL_RELEASE_R3_P3:
780	case CACHE_L2C_310_RTL_RELEASE_R3_P2:
781	case CACHE_L2C_310_RTL_RELEASE_R3_P1:
782	case CACHE_L2C_310_RTL_RELEASE_R3_P0:
783	case CACHE_L2C_310_RTL_RELEASE_R2_P0:
784	case CACHE_L2C_310_RTL_RELEASE_R1_P0:
785	case CACHE_L2C_310_RTL_RELEASE_R0_P0:
786	is_applicable = true;
787	break;
788	default:
789	assert( RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P3
790	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P2
791	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P1
792	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P0
793	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R2_P0
794	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R1_P0
795	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R0_P0 );
796	break;
797	}
798
799	return is_applicable;
800	}
801
802	static bool l2c_310_cache_errata_is_applicable_769419(
803	void
804	)
805	{
806	volatile L2CC *l2cc =
807	(volatile L2CC *) BSP_ARM_L2CC_BASE;
808	const cache_l2c_310_rtl_release RTL_RELEASE =
809	l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;
810	bool is_applicable = false;
811
812	switch( RTL_RELEASE ) {
813	case CACHE_L2C_310_RTL_RELEASE_R3_P3:
814	case CACHE_L2C_310_RTL_RELEASE_R3_P2:
815	is_applicable = false;
816	break;
817	case CACHE_L2C_310_RTL_RELEASE_R3_P1:
818	case CACHE_L2C_310_RTL_RELEASE_R3_P0:
819	case CACHE_L2C_310_RTL_RELEASE_R2_P0:
820	case CACHE_L2C_310_RTL_RELEASE_R1_P0:
821	case CACHE_L2C_310_RTL_RELEASE_R0_P0:
822	is_applicable = true;
823	break;
824	default:
825	assert( RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P3
826	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P2
827	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P1
828	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P0
829	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R2_P0
830	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R1_P0
831	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R0_P0 );
832	break;
833	}
834
835	return is_applicable;
836	}
837
838	static bool l2c_310_cache_errata_is_applicable_588369(
839	void
840	)
841	{
842	volatile L2CC *l2cc =
843	(volatile L2CC *) BSP_ARM_L2CC_BASE;
844	const cache_l2c_310_rtl_release RTL_RELEASE =
845	l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;
846	bool is_applicable = false;
847
848	switch( RTL_RELEASE ) {
849	case CACHE_L2C_310_RTL_RELEASE_R3_P3:
850	case CACHE_L2C_310_RTL_RELEASE_R3_P2:
851	case CACHE_L2C_310_RTL_RELEASE_R3_P1:
852	case CACHE_L2C_310_RTL_RELEASE_R3_P0:
853	case CACHE_L2C_310_RTL_RELEASE_R2_P0:
854	is_applicable = false;
855	break;
856	case CACHE_L2C_310_RTL_RELEASE_R1_P0:
857	case CACHE_L2C_310_RTL_RELEASE_R0_P0:
858	is_applicable = true;
859	break;
860	default:
861	assert( RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P3
862	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P2
863	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P1
864	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P0
865	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R2_P0
866	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R1_P0
867	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R0_P0 );
868	break;
869	}
870
871	return is_applicable;
872	}
873
874	#ifdef CACHE_ERRATA_CHECKS_FOR_IMPLEMENTED_ERRATAS
875	static bool l2c_310_cache_errata_is_applicable_754670(
876	void
877	)
878	{
879	volatile L2CC *l2cc =
880	(volatile L2CC *) BSP_ARM_L2CC_BASE;
881	const cache_l2c_310_rtl_release RTL_RELEASE =
882	l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;
883	bool is_applicable = false;
884
885	switch( RTL_RELEASE ) {
886	case CACHE_L2C_310_RTL_RELEASE_R3_P3:
887	case CACHE_L2C_310_RTL_RELEASE_R3_P2:
888	case CACHE_L2C_310_RTL_RELEASE_R3_P1:
889	case CACHE_L2C_310_RTL_RELEASE_R3_P0:
890	case CACHE_L2C_310_RTL_RELEASE_R2_P0:
891	case CACHE_L2C_310_RTL_RELEASE_R1_P0:
892	case CACHE_L2C_310_RTL_RELEASE_R0_P0:
893	is_applicable = true;
894	break;
895	default:
896	assert( RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P3
897	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P2
898	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P1
899	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P0
900	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R2_P0
901	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R1_P0
902	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R0_P0 );
903	break;
904	}
905
906	return is_applicable;
907	}
908	#endif /* CACHE_ERRATA_CHECKS_FOR_IMPLEMENTED_ERRATAS */
909
910	/* The common workaround for this erratum would be to add a
911	* data synchronization barrier to the beginning of the abort handler.
912	* But for RTEMS a call of the abort handler means a fatal condition anyway.
913	* So there is no need to handle this erratum */
914	#define CACHE_ARM_ERRATA_775420_HANDLER() \
915	if( arm_errata_is_applicable_processor_errata_775420 ) { \
916	} \
917
918	static void l2c_310_cache_check_errata( void )
919	{
920	/* This erratum gets handled within the sources */
921	/* Unhandled erratum present: 588369 Errata 588369 says that clean + inv may
922	* keep the cache line if it was clean. See ARMs documentation on the erratum
923	* for a workaround */
924	/* assert( ! l2c_310_cache_errata_is_applicable_588369() ); */
925
926	/* Unhandled erratum present: 727913 Prefetch dropping feature can cause
927	* incorrect behavior when PL310 handles reads that cross cache line
928	* boundary */
929	assert( ! l2c_310_cache_errata_is_applicable_727913() );
930
931	/* Unhandled erratum present: 727914 Double linefill feature can cause
932	* deadlock */
933	assert( ! l2c_310_cache_errata_is_applicable_727914() );
934
935	/* Unhandled erratum present: 727915 Background Clean and Invalidate by Way
936	* operation can cause data corruption */
937	assert( ! l2c_310_cache_errata_is_applicable_727915() );
938
939	/* Unhandled erratum present: 729806 Speculative reads from the Cortex-A9
940	* MPCore processor can cause deadlock */
941	assert( ! l2c_310_cache_errata_is_applicable_729806() );
942
943	if( l2c_310_cache_errata_is_applicable_729815() )
944	{
945	volatile L2CC l2cc = (volatile L2CC ) BSP_ARM_L2CC_BASE;
946
947	assert( 0 == ( l2cc->aux_ctrl & CACHE_L2C_310_L2CC_AUX_HPSODRE_MASK ) );
948
949	/* Erratum: 729815 The âHigh Priority for SO and Dev readsâ feature can
950	* cause Quality of Service issues to cacheable read transactions*/
951
952	/* Conditions
953	This problem occurs when the following conditions are met:
954	1. Bit[10] âHigh Priority for SO and Dev reads enableâ of the PL310
955	Auxiliary Control Register is set to 1.
956	2. PL310 receives a cacheable read that misses in the L2 cache.
957	3. PL310 receives a continuous flow of Strongly Ordered or Device
958	reads that take all address slots in the master interface.
959	Workaround
960	A workaround is only necessary in systems that are able to issue a
961	continuous flow of Strongly Ordered or Device reads. In such a case,
962	the workaround is to disable the âHigh Priority for SO and Dev readsâ
963	feature. This is the default behavior.*/
964	}
965
966	/* Unhandled erratum present: 742884 Double linefill feature might introduce
967	* circular dependency and deadlock */
968	assert( ! l2c_310_cache_errata_is_applicable_742884() );
969
970	/* Unhandled erratum present: 752271 Double linefill feature can cause data
971	* corruption */
972	assert( ! l2c_310_cache_errata_is_applicable_752271() );
973
974	/* This erratum can not be worked around: 754670 A continuous write flow can
975	* stall a read targeting the same memory area
976	* But this erratum does not lead to any data corruption */
977	/* assert( ! l2c_310_cache_errata_is_applicable_754670() ); */
978
979	if( l2c_310_cache_errata_is_applicable_765569() )
980	{
981	volatile L2CC l2cc = (volatile L2CC ) BSP_ARM_L2CC_BASE;
982
983	assert( !( ( l2cc->aux_ctrl & CACHE_L2C_310_L2CC_AUX_IPFE_MASK
984	\|\| l2cc->aux_ctrl & CACHE_L2C_310_L2CC_AUX_DPFE_MASK )
985	&& ( ( l2cc->prefetch_ctrl & CACHE_L2C_310_L2CC_PREFETCH_OFFSET_MASK )
986	== 23 ) ) );
987
988	/* Unhandled erratum present: 765569 Prefetcher can cross 4KB boundary if
989	* offset is programmed with value 23 */
990
991	/* Conditions
992	This problem occurs when the following conditions are met:
993	1. One of the Prefetch Enable bits (bits [29:28] of the Auxiliary or
994	Prefetch Control Register) is set HIGH.
995	2. The prefetch offset bits are programmed with value 23 (5'b10111).
996	Workaround
997	A workaround for this erratum is to program the prefetch offset with any
998	value except 23.*/
999	}
1000
1001	/* Unhandled erratum present: 769419 No automatic Store Buffer drain,
1002	* visibility of written data requires an explicit Cache */
1003	assert( ! l2c_310_cache_errata_is_applicable_769419() );
1004	}
1005
1006	static inline void
1007	cache_l2c_310_sync( void )
1008	{
1009	volatile L2CC l2cc = (volatile L2CC ) BSP_ARM_L2CC_BASE;
1010
1011	if( l2c_310_cache_errata_is_applicable_753970() ) {
1012	l2cc->dummy_cache_sync_reg = 0;
1013	} else {
1014	l2cc->cache_sync = 0;
1015	}
1016	}
1017
1018	static inline void
1019	cache_l2c_310_flush_1_line(
1020	const void *d_addr,
1021	const bool is_errata_588369applicable
1022	)
1023	{
1024	volatile L2CC l2cc = (volatile L2CC ) BSP_ARM_L2CC_BASE;
1025
1026	if( is_errata_588369applicable ) {
1027	/*
1028	* Errata 588369 says that clean + inv may keep the
1029	* cache line if it was clean, the recommended
1030	* workaround is to clean then invalidate the cache
1031	* line, with write-back and cache linefill disabled.
1032	*/
1033	l2cc->clean_pa = (uint32_t) d_addr;
1034	cache_l2c_310_sync();
1035	l2cc->inv_pa = (uint32_t) d_addr;
1036	} else {
1037	l2cc->clean_inv_pa = (uint32_t) d_addr;
1038	}
1039	}
1040
1041	static inline void
1042	cache_l2c_310_flush_range( const void* d_addr, const size_t n_bytes )
1043	{
1044	rtems_interrupt_lock_context lock_context;
1045	/* Back starting address up to start of a line and invalidate until ADDR_LAST */
1046	uint32_t adx = (uint32_t)d_addr
1047	& ~CACHE_L2C_310_DATA_LINE_MASK;
1048	const uint32_t ADDR_LAST =
1049	(uint32_t)( (size_t)d_addr + n_bytes - 1 );
1050	uint32_t block_end =
1051	CACHE_MIN( ADDR_LAST, adx + CACHE_MAX_LOCKING_BYTES );
1052	bool is_errata_588369_applicable =
1053	l2c_310_cache_errata_is_applicable_588369();
1054
1055	rtems_interrupt_lock_acquire( &l2c_310_cache_lock, &lock_context );
1056
1057	for (;
1058	adx <= ADDR_LAST;
1059	adx = block_end + 1,
1060	block_end = CACHE_MIN( ADDR_LAST, adx + CACHE_MAX_LOCKING_BYTES )) {
1061	for (; adx <= block_end; adx += CPU_DATA_CACHE_ALIGNMENT ) {
1062	cache_l2c_310_flush_1_line( (void*)adx, is_errata_588369_applicable );
1063	}
1064	if( block_end < ADDR_LAST ) {
1065	rtems_interrupt_lock_release( &l2c_310_cache_lock, &lock_context );
1066	rtems_interrupt_lock_acquire( &l2c_310_cache_lock, &lock_context );
1067	}
1068	}
1069	cache_l2c_310_sync();
1070	rtems_interrupt_lock_release( &l2c_310_cache_lock, &lock_context );
1071	}
1072
1073	static inline void
1074	cache_l2c_310_flush_entire( void )
1075	{
1076	volatile L2CC l2cc = (volatile L2CC ) BSP_ARM_L2CC_BASE;
1077	rtems_interrupt_lock_context lock_context;
1078
1079	/* Only flush if level 2 cache is active */
1080	if( ( l2cc->ctrl & CACHE_L2C_310_L2CC_ENABLE_MASK ) != 0 ) {
1081
1082	/* ensure ordering with previous memory accesses */
1083	_ARM_Data_memory_barrier();
1084
1085	rtems_interrupt_lock_acquire( &l2c_310_cache_lock, &lock_context );
1086	l2cc->clean_inv_way = CACHE_l2C_310_WAY_MASK;
1087
1088	while ( l2cc->clean_inv_way & CACHE_l2C_310_WAY_MASK ) {};
1089
1090	/* Wait for the flush to complete */
1091	cache_l2c_310_sync();
1092
1093	rtems_interrupt_lock_release( &l2c_310_cache_lock, &lock_context );
1094	}
1095	}
1096
1097	static inline void
1098	cache_l2c_310_invalidate_1_line( const void *d_addr )
1099	{
1100	volatile L2CC l2cc = (volatile L2CC ) BSP_ARM_L2CC_BASE;
1101
1102
1103	l2cc->inv_pa = (uint32_t) d_addr;
1104	cache_l2c_310_sync();
1105	}
1106
1107	static inline void
1108	cache_l2c_310_invalidate_range( uint32_t adx, const uint32_t ADDR_LAST )
1109	{
1110	volatile L2CC l2cc = (volatile L2CC ) BSP_ARM_L2CC_BASE;
1111	rtems_interrupt_lock_context lock_context;
1112
1113	rtems_interrupt_lock_acquire( &l2c_310_cache_lock, &lock_context );
1114	for (;
1115	adx <= ADDR_LAST;
1116	adx += CPU_INSTRUCTION_CACHE_ALIGNMENT ) {
1117	/* Invalidate L2 cache line */
1118	l2cc->inv_pa = adx;
1119	}
1120	cache_l2c_310_sync();
1121	rtems_interrupt_lock_release( &l2c_310_cache_lock, &lock_context );
1122	}
1123
1124	static inline void
1125	cache_l2c_310_invalidate_entire( void )
1126	{
1127	volatile L2CC l2cc = (volatile L2CC ) BSP_ARM_L2CC_BASE;
1128
1129	/* Invalidate the caches */
1130
1131	/* ensure ordering with previous memory accesses */
1132	_ARM_Data_memory_barrier();
1133
1134	l2cc->inv_way = CACHE_l2C_310_WAY_MASK;
1135
1136	while ( l2cc->inv_way & CACHE_l2C_310_WAY_MASK ) ;
1137
1138	/* Wait for the invalidate to complete */
1139	cache_l2c_310_sync();
1140	}
1141
1142	static inline void
1143	cache_l2c_310_clean_and_invalidate_entire( void )
1144	{
1145	volatile L2CC l2cc = (volatile L2CC ) BSP_ARM_L2CC_BASE;
1146	rtems_interrupt_lock_context lock_context;
1147
1148	if( ( l2cc->ctrl & CACHE_L2C_310_L2CC_ENABLE_MASK ) != 0 ) {
1149	/* Invalidate the caches */
1150
1151	/* ensure ordering with previous memory accesses */
1152	_ARM_Data_memory_barrier();
1153
1154	rtems_interrupt_lock_acquire( &l2c_310_cache_lock, &lock_context );
1155	l2cc->clean_inv_way = CACHE_l2C_310_WAY_MASK;
1156
1157	while ( l2cc->clean_inv_way & CACHE_l2C_310_WAY_MASK ) ;
1158
1159	/* Wait for the invalidate to complete */
1160	cache_l2c_310_sync();
1161
1162	rtems_interrupt_lock_release( &l2c_310_cache_lock, &lock_context );
1163	}
1164	}
1165
1166	static inline void
1167	cache_l2c_310_freeze( void )
1168	{
1169	/* To be implemented as needed, if supported
1170	by hardware at all */
1171	}
1172
1173	static inline void
1174	cache_l2c_310_unfreeze( void )
1175	{
1176	/* To be implemented as needed, if supported
1177	by hardware at all */
1178	}
1179
1180	static inline size_t
1181	cache_l2c_310_get_cache_size( void )
1182	{
1183	size_t size = 0;
1184	volatile L2CC l2cc = (volatile L2CC ) BSP_ARM_L2CC_BASE;
1185	uint32_t cache_type = l2cc->cache_type;
1186	uint32_t way_size;
1187	uint32_t num_ways;
1188
1189	way_size = (cache_type & CACHE_L2C_310_L2CC_TYPE_SIZE_D_WAYS_MASK)
1190	>> CACHE_L2C_310_L2CC_TYPE_SIZE_D_WAYS_SHIFT;
1191	num_ways = (cache_type & CACHE_L2C_310_L2CC_TYPE_NUM_D_WAYS_MASK)
1192	>> CACHE_L2C_310_L2CC_TYPE_NUM_D_WAYS_SHIFT;
1193
1194	assert( way_size <= 0x07 );
1195	assert( num_ways <= 0x01 );
1196	if( way_size <= 0x07 && num_ways <= 0x01 ) {
1197	if( way_size == 0x00 ) {
1198	way_size = 16 * 1024;
1199	} else if( way_size == 0x07 ) {
1200	way_size = 512 * 1024;
1201	} else {
1202	way_size = (1 << (way_size - 1)) * 16 * 1024;
1203	}
1204	switch( num_ways ) {
1205	case 0:
1206	num_ways = 8;
1207	break;
1208	case 1:
1209	num_ways = 16;
1210	break;
1211	default:
1212	num_ways = 0;
1213	break;
1214	}
1215	size = way_size * num_ways;
1216	}
1217	return size;
1218	}
1219
1220	static void cache_l2c_310_unlock( void )
1221	{
1222	volatile L2CC l2cc = (volatile L2CC ) BSP_ARM_L2CC_BASE;
1223
1224
1225	l2cc->d_lockdown_0 = 0;
1226	l2cc->i_lockdown_0 = 0;
1227	l2cc->d_lockdown_1 = 0;
1228	l2cc->i_lockdown_1 = 0;
1229	l2cc->d_lockdown_2 = 0;
1230	l2cc->i_lockdown_2 = 0;
1231	l2cc->d_lockdown_3 = 0;
1232	l2cc->i_lockdown_3 = 0;
1233	l2cc->d_lockdown_4 = 0;
1234	l2cc->i_lockdown_4 = 0;
1235	l2cc->d_lockdown_5 = 0;
1236	l2cc->i_lockdown_5 = 0;
1237	l2cc->d_lockdown_6 = 0;
1238	l2cc->i_lockdown_6 = 0;
1239	l2cc->d_lockdown_7 = 0;
1240	l2cc->i_lockdown_7 = 0;
1241	}
1242
1243	static inline void
1244	cache_l2c_310_enable( void )
1245	{
1246	volatile L2CC l2cc = (volatile L2CC ) BSP_ARM_L2CC_BASE;
1247
1248	/* Only enable if L2CC is currently disabled */
1249	if( ( l2cc->ctrl & CACHE_L2C_310_L2CC_ENABLE_MASK ) == 0 ) {
1250	uint32_t cache_id =
1251	l2cc->cache_id & CACHE_L2C_310_L2CC_ID_PART_MASK;
1252	int ways = 0;
1253
1254	/* Do we actually have an L2C-310 cache controller?
1255	* Has BSP_ARM_L2CC_BASE been configured correctly? */
1256	switch ( cache_id ) {
1257	case CACHE_L2C_310_L2CC_ID_PART_L310:
1258	{
1259	const cache_l2c_310_rtl_release RTL_RELEASE =
1260	l2cc->cache_id & CACHE_L2C_310_L2CC_ID_RTL_MASK;
1261	/* If this assertion fails, you have a release of the
1262	* L2C-310 cache for which the l2c_310_cache_errata_is_applicable_ ...
1263	* methods are not yet implemented. This means you will get incorrect
1264	* errata handling */
1265	assert( RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P3
1266	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P2
1267	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P1
1268	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R3_P0
1269	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R2_P0
1270	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R1_P0
1271	\|\| RTL_RELEASE == CACHE_L2C_310_RTL_RELEASE_R0_P0 );
1272	if ( l2cc->aux_ctrl & ( 1 << 16 ) ) {
1273	ways = 16;
1274	} else {
1275	ways = 8;
1276	}
1277
1278	assert( ways == CACHE_l2C_310_NUM_WAYS );
1279	}
1280	break;
1281	case CACHE_L2C_310_L2CC_ID_PART_L210:
1282
1283	/* Invalid case */
1284
1285	/* Support for this type is not implemented in this driver.
1286	* Either support needs to get added or a seperate driver needs to get
1287	* implemented */
1288	assert( cache_id != CACHE_L2C_310_L2CC_ID_PART_L210 );
1289	break;
1290	default:
1291
1292	/* Unknown case */
1293	assert( cache_id == CACHE_L2C_310_L2CC_ID_PART_L310 );
1294	break;
1295	}
1296
1297	if ( ways > 0 ) {
1298	uint32_t aux;
1299
1300	/* Set up the way size */
1301	aux = l2cc->aux_ctrl;
1302	aux &= CACHE_L2C_310_L2CC_AUX_REG_ZERO_MASK; /* Set way_size to 0 */
1303	aux \|= CACHE_L2C_310_L2CC_AUX_REG_DEFAULT_MASK;
1304
1305	/* Make sure that I&D is not locked down when starting */
1306	cache_l2c_310_unlock();
1307
1308	/* Level 2 configuration and control registers must not get written while
1309	* background operations are pending */
1310	while ( l2cc->inv_way & CACHE_l2C_310_WAY_MASK ) ;
1311
1312	while ( l2cc->clean_way & CACHE_l2C_310_WAY_MASK ) ;
1313
1314	while ( l2cc->clean_inv_way & CACHE_l2C_310_WAY_MASK ) ;
1315
1316	l2cc->aux_ctrl = aux;
1317
1318	/* Set up the latencies */
1319	l2cc->tag_ram_ctrl = CACHE_L2C_310_L2CC_TAG_RAM_DEFAULT_LAT;
1320	l2cc->data_ram_ctrl = CACHE_L2C_310_L2CC_DATA_RAM_DEFAULT_MASK;
1321
1322	cache_l2c_310_invalidate_entire();
1323
1324	/* Clear the pending interrupts */
1325	l2cc->int_clr = l2cc->int_raw_status;
1326
1327	l2c_310_cache_check_errata();
1328
1329	/* Enable the L2CC */
1330	l2cc->ctrl \|= CACHE_L2C_310_L2CC_ENABLE_MASK;
1331	}
1332	}
1333	}
1334
1335	static inline void
1336	cache_l2c_310_disable( void )
1337	{
1338	volatile L2CC l2cc = (volatile L2CC ) BSP_ARM_L2CC_BASE;
1339	rtems_interrupt_lock_context lock_context;
1340
1341	if ( l2cc->ctrl & CACHE_L2C_310_L2CC_ENABLE_MASK ) {
1342	/* Clean and Invalidate L2 Cache */
1343	cache_l2c_310_flush_entire();
1344	rtems_interrupt_lock_acquire( &l2c_310_cache_lock, &lock_context );
1345
1346	/* Level 2 configuration and control registers must not get written while
1347	* background operations are pending */
1348	while ( l2cc->inv_way & CACHE_l2C_310_WAY_MASK ) ;
1349
1350	while ( l2cc->clean_way & CACHE_l2C_310_WAY_MASK ) ;
1351
1352	while ( l2cc->clean_inv_way & CACHE_l2C_310_WAY_MASK ) ;
1353
1354	/* Disable the L2 cache */
1355	l2cc->ctrl &= ~CACHE_L2C_310_L2CC_ENABLE_MASK;
1356	rtems_interrupt_lock_release( &l2c_310_cache_lock, &lock_context );
1357	}
1358	}
1359
1360	static inline void
1361	_CPU_cache_enable_data( void )
1362	{
1363	cache_l2c_310_enable();
1364	}
1365
1366	static inline void
1367	_CPU_cache_disable_data( void )
1368	{
1369	arm_cache_l1_disable_data();
1370	cache_l2c_310_disable();
1371	}
1372
1373	static inline void
1374	_CPU_cache_enable_instruction( void )
1375	{
1376	cache_l2c_310_enable();
1377	}
1378
1379	static inline void
1380	_CPU_cache_disable_instruction( void )
1381	{
1382	arm_cache_l1_disable_instruction();
1383	cache_l2c_310_disable();
1384	}
1385
1386	static inline void
1387	_CPU_cache_flush_data_range(
1388	const void *d_addr,
1389	size_t n_bytes
1390	)
1391	{
1392	if ( n_bytes != 0 ) {
1393	arm_cache_l1_flush_data_range(
1394	d_addr,
1395	n_bytes
1396	);
1397	cache_l2c_310_flush_range(
1398	d_addr,
1399	n_bytes
1400	);
1401	}
1402	}
1403
1404	static inline void
1405	_CPU_cache_flush_entire_data( void )
1406	{
1407	arm_cache_l1_flush_entire_data();
1408	cache_l2c_310_flush_entire();
1409	}
1410
1411	static inline void
1412	_CPU_cache_invalidate_data_range(
1413	const void *addr_first,
1414	size_t n_bytes
1415	)
1416	{
1417	if ( n_bytes > 0 ) {
1418	/* Back starting address up to start of a line and invalidate until ADDR_LAST */
1419	uint32_t adx = (uint32_t) addr_first
1420	& ~CACHE_L2C_310_DATA_LINE_MASK;
1421	const uint32_t ADDR_LAST =
1422	(uint32_t)( (size_t)addr_first + n_bytes - 1 );
1423	uint32_t block_end =
1424	CACHE_MIN( ADDR_LAST, adx + CACHE_MAX_LOCKING_BYTES );
1425
1426	/* We have to apply a lock. Thus we will operate only CACHE_MAX_LOCKING_BYTES
1427	* at a time */
1428	for (;
1429	adx <= ADDR_LAST;
1430	adx = block_end + 1,
1431	block_end = CACHE_MIN( ADDR_LAST, adx + CACHE_MAX_LOCKING_BYTES )) {
1432	cache_l2c_310_invalidate_range(
1433	adx,
1434	block_end
1435	);
1436	}
1437	arm_cache_l1_invalidate_data_range(
1438	addr_first,
1439	n_bytes
1440	);
1441
1442	adx = (uint32_t)addr_first & ~CACHE_L2C_310_DATA_LINE_MASK;
1443	block_end = CACHE_MIN( ADDR_LAST, adx + CACHE_MAX_LOCKING_BYTES );
1444	for (;
1445	adx <= ADDR_LAST;
1446	adx = block_end + 1,
1447	block_end = CACHE_MIN( ADDR_LAST, adx + CACHE_MAX_LOCKING_BYTES )) {
1448	cache_l2c_310_invalidate_range(
1449	adx,
1450	block_end
1451	);
1452	}
1453	arm_cache_l1_invalidate_data_range(
1454	addr_first,
1455	n_bytes
1456	);
1457	}
1458	}
1459
1460	static inline void
1461	_CPU_cache_invalidate_entire_data( void )
1462	{
1463	/* This is broadcast within the cluster */
1464	arm_cache_l1_flush_entire_data();
1465
1466	/* forces the address out past level 2 */
1467	cache_l2c_310_clean_and_invalidate_entire();
1468
1469	/This is broadcast within the cluster /
1470	arm_cache_l1_clean_and_invalidate_entire_data();
1471	}
1472
1473	static inline void
1474	_CPU_cache_freeze_data( void )
1475	{
1476	arm_cache_l1_freeze_data();
1477	cache_l2c_310_freeze();
1478	}
1479
1480	static inline void
1481	_CPU_cache_unfreeze_data( void )
1482	{
1483	arm_cache_l1_unfreeze_data();
1484	cache_l2c_310_unfreeze();
1485	}
1486
1487	static inline void
1488	_CPU_cache_invalidate_instruction_range( const void *i_addr, size_t n_bytes)
1489	{
1490	arm_cache_l1_invalidate_instruction_range( i_addr, n_bytes );
1491	}
1492
1493	static inline void
1494	_CPU_cache_invalidate_entire_instruction( void )
1495	{
1496	arm_cache_l1_invalidate_entire_instruction();
1497	}
1498
1499	static inline void
1500	_CPU_cache_freeze_instruction( void )
1501	{
1502	arm_cache_l1_freeze_instruction();
1503	cache_l2c_310_freeze();
1504	}
1505
1506	static inline void
1507	_CPU_cache_unfreeze_instruction( void )
1508	{
1509	arm_cache_l1_unfreeze_instruction();
1510	cache_l2c_310_unfreeze();
1511	}
1512
1513	static inline size_t
1514	_CPU_cache_get_data_cache_size( const uint32_t level )
1515	{
1516	size_t size = 0;
1517
1518	switch( level )
1519	{
1520	case 1:
1521	size = arm_cache_l1_get_data_cache_size();
1522	break;
1523	case 0:
1524	case 2:
1525	size = cache_l2c_310_get_cache_size();
1526	break;
1527	default:
1528	size = 0;
1529	break;
1530	}
1531	return size;
1532	}
1533
1534	static inline size_t
1535	_CPU_cache_get_instruction_cache_size( const uint32_t level )
1536	{
1537	size_t size = 0;
1538
1539	switch( level )
1540	{
1541	case 1:
1542	size = arm_cache_l1_get_instruction_cache_size();
1543	break;
1544	case 0:
1545	case 2:
1546	size = cache_l2c_310_get_cache_size();
1547	break;
1548	default:
1549	size = 0;
1550	break;
1551	}
1552	return size;
1553	}
1554
1555
1556	/** @} */
1557
1558	#ifdef __cplusplus
1559	}
1560	#endif /* __cplusplus */
1561
1562	#endif /* LIBBSP_ARM_SHARED_L2C_310_CACHE_H */

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