[9fcd1b35] | 1 | /** |
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| 2 | * @file cache_.h |
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| 3 | * |
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| 4 | * @ingroup L2C-310_cache |
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| 5 | * |
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| 6 | * @brief Cache definitions and functions. |
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[a9d6c20] | 7 | * |
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[9fcd1b35] | 8 | * This file implements handling for the ARM L2C-310 cache controller |
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| 9 | */ |
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| 10 | |
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| 11 | /* |
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| 12 | * Authorship |
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| 13 | * ---------- |
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| 14 | * This software was created by |
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| 15 | * R. Claus <claus@slac.stanford.edu>, 2013, |
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| 16 | * Stanford Linear Accelerator Center, Stanford University. |
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| 17 | * |
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| 18 | * Acknowledgement of sponsorship |
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| 19 | * ------------------------------ |
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| 20 | * This software was produced by |
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| 21 | * the Stanford Linear Accelerator Center, Stanford University, |
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| 22 | * under Contract DE-AC03-76SFO0515 with the Department of Energy. |
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| 23 | * |
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| 24 | * Government disclaimer of liability |
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| 25 | * ---------------------------------- |
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| 26 | * Neither the United States nor the United States Department of Energy, |
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| 27 | * nor any of their employees, makes any warranty, express or implied, or |
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| 28 | * assumes any legal liability or responsibility for the accuracy, |
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| 29 | * completeness, or usefulness of any data, apparatus, product, or process |
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| 30 | * disclosed, or represents that its use would not infringe privately owned |
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| 31 | * rights. |
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| 32 | * |
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| 33 | * Stanford disclaimer of liability |
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| 34 | * -------------------------------- |
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| 35 | * Stanford University makes no representations or warranties, express or |
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| 36 | * implied, nor assumes any liability for the use of this software. |
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| 37 | * |
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| 38 | * Stanford disclaimer of copyright |
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| 39 | * -------------------------------- |
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| 40 | * Stanford University, owner of the copyright, hereby disclaims its |
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| 41 | * copyright and all other rights in this software. Hence, anyone may |
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| 42 | * freely use it for any purpose without restriction. |
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| 43 | * |
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| 44 | * Maintenance of notices |
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| 45 | * ---------------------- |
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| 46 | * In the interest of clarity regarding the origin and status of this |
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| 47 | * SLAC software, this and all the preceding Stanford University notices |
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| 48 | * are to remain affixed to any copy or derivative of this software made |
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| 49 | * or distributed by the recipient and are to be affixed to any copy of |
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| 50 | * software made or distributed by the recipient that contains a copy or |
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| 51 | * derivative of this software. |
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| 52 | * |
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| 53 | * ------------------ SLAC Software Notices, Set 4 OTT.002a, 2004 FEB 03 |
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| 54 | */ |
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| 55 | |
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| 56 | #ifndef LIBBSP_ARM_SHARED_L2C_310_CACHE_H |
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| 57 | #define LIBBSP_ARM_SHARED_L2C_310_CACHE_H |
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| 58 | |
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| 59 | #include <assert.h> |
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| 60 | #include <bsp.h> |
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[f2fed0c1] | 61 | #include <bsp/fatal.h> |
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[9fcd1b35] | 62 | #include <libcpu/arm-cp15.h> |
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[1c62f74d] | 63 | #include <rtems/rtems/intr.h> |
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[9fcd1b35] | 64 | #include <bsp/arm-release-id.h> |
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| 65 | #include <bsp/arm-errata.h> |
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| 66 | #include "../include/arm-cache-l1.h" |
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| 67 | |
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| 68 | #ifdef __cplusplus |
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| 69 | extern "C" { |
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| 70 | #endif /* __cplusplus */ |
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| 71 | |
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| 72 | /* These two defines also ensure that the rtems_cache_* functions have bodies */ |
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| 73 | #define CPU_DATA_CACHE_ALIGNMENT ARM_CACHE_L1_CPU_DATA_ALIGNMENT |
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| 74 | #define CPU_INSTRUCTION_CACHE_ALIGNMENT ARM_CACHE_L1_CPU_INSTRUCTION_ALIGNMENT |
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| 75 | #define CPU_CACHE_SUPPORT_PROVIDES_RANGE_FUNCTIONS \ |
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| 76 | ARM_CACHE_L1_CPU_SUPPORT_PROVIDES_RANGE_FUNCTIONS |
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[62fa1ea] | 77 | #define CPU_CACHE_SUPPORT_PROVIDES_CACHE_SIZE_FUNCTIONS |
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[9fcd1b35] | 78 | |
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[861d315] | 79 | #define L2C_310_DATA_LINE_MASK ( CPU_DATA_CACHE_ALIGNMENT - 1 ) |
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| 80 | #define L2C_310_INSTRUCTION_LINE_MASK \ |
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[9fcd1b35] | 81 | ( CPU_INSTRUCTION_CACHE_ALIGNMENT \ |
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| 82 | - 1 ) |
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[861d315] | 83 | #define L2C_310_NUM_WAYS 8 |
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| 84 | #define L2C_310_WAY_MASK ( ( 1 << L2C_310_NUM_WAYS ) - 1 ) |
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[9fcd1b35] | 85 | |
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[861d315] | 86 | #define L2C_310_MIN( a, b ) \ |
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[92e2757] | 87 | ((a < b) ? (a) : (b)) |
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| 88 | |
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[861d315] | 89 | #define L2C_310_MAX_LOCKING_BYTES (4 * 1024) |
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[1c62f74d] | 90 | |
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[9fcd1b35] | 91 | |
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| 92 | /* RTL release number as can be read from cache_id register */ |
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[52d24b00] | 93 | #define L2C_310_RTL_RELEASE_R0_P0 0x0 |
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| 94 | #define L2C_310_RTL_RELEASE_R1_P0 0x2 |
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| 95 | #define L2C_310_RTL_RELEASE_R2_P0 0x4 |
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| 96 | #define L2C_310_RTL_RELEASE_R3_P0 0x5 |
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| 97 | #define L2C_310_RTL_RELEASE_R3_P1 0x6 |
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| 98 | #define L2C_310_RTL_RELEASE_R3_P2 0x8 |
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| 99 | #define L2C_310_RTL_RELEASE_R3_P3 0x9 |
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| 100 | |
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| 101 | #define BSP_ARM_L2C_310_RTL_RELEASE (BSP_ARM_L2C_310_ID & L2C_310_ID_RTL_MASK) |
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[9fcd1b35] | 102 | |
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| 103 | /** |
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| 104 | * @defgroup L2C-310_cache Cache Support |
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| 105 | * @ingroup arm_shared |
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| 106 | * @brief Cache Functions and Defitions |
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| 107 | * @{ |
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| 108 | */ |
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| 109 | |
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| 110 | |
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| 111 | /** |
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| 112 | * @brief L2CC Register Offsets |
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| 113 | */ |
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| 114 | typedef struct { |
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| 115 | /** @brief Cache ID */ |
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| 116 | uint32_t cache_id; |
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[861d315] | 117 | #define L2C_310_ID_RTL_MASK 0x3f |
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| 118 | #define L2C_310_ID_PART_MASK ( 0xf << 6 ) |
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| 119 | #define L2C_310_ID_PART_L210 ( 1 << 6 ) |
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| 120 | #define L2C_310_ID_PART_L310 ( 3 << 6 ) |
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| 121 | #define L2C_310_ID_IMPL_MASK ( 0xff << 24 ) |
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[9fcd1b35] | 122 | /** @brief Cache type */ |
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| 123 | uint32_t cache_type; |
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| 124 | /** @brief 1 if data banking implemented, 0 if not */ |
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[861d315] | 125 | #define L2C_310_TYPE_DATA_BANKING_MASK 0x80000000 |
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[9fcd1b35] | 126 | /** @brief 11xy, where: x=1 if pl310_LOCKDOWN_BY_MASTER is defined, otherwise 0 */ |
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[861d315] | 127 | #define L2C_310_TYPE_CTYPE_MASK 0x1E000000 |
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[9fcd1b35] | 128 | /** @brief y=1 if pl310_LOCKDOWN_BY_LINE is defined, otherwise 0. */ |
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[861d315] | 129 | #define L2C_310_TYPE_CTYPE_SHIFT 25 |
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[9fcd1b35] | 130 | /** @brief 1 for Harvard architecture, 0 for unified architecture */ |
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[861d315] | 131 | #define L2C_310_TYPE_HARVARD_MASK 0x01000000 |
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[9fcd1b35] | 132 | /** @brief Data cache way size = 2 Exp(value + 2) KB */ |
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[861d315] | 133 | #define L2C_310_TYPE_SIZE_D_WAYS_MASK 0x00700000 |
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| 134 | #define L2C_310_TYPE_SIZE_D_WAYS_SHIFT 20 |
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[9fcd1b35] | 135 | /** @brief Assoziativity aka number of data ways = (value * 8) + 8 */ |
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[861d315] | 136 | #define L2C_310_TYPE_NUM_D_WAYS_MASK 0x00040000 |
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| 137 | #define L2C_310_TYPE_NUM_D_WAYS_SHIFT 18 |
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[9fcd1b35] | 138 | /** @brief Data cache line length 00 - 32 */ |
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[861d315] | 139 | #define L2C_310_TYPE_LENGTH_D_LINE_MASK 0x00003000 |
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| 140 | #define L2C_310_TYPE_LENGTH_D_LINE_SHIFT 12 |
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| 141 | #define L2C_310_TYPE_LENGTH_D_LINE_VAL_32 0x0 |
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[9fcd1b35] | 142 | /** @brief Instruction cache way size = 2 Exp(value + 2) KB */ |
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[861d315] | 143 | #define L2C_310_TYPE_SIZE_I_WAYS_MASK 0x00000700 |
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| 144 | #define L2C_310_TYPE_SIZE_I_WAYS_SHIFT 8 |
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[9fcd1b35] | 145 | /** @brief Assoziativity aka number of instruction ways = (value * 8) + 8 */ |
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[861d315] | 146 | #define L2C_310_TYPE_NUM_I_WAYS_MASK 0x00000040 |
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| 147 | #define L2C_310_TYPE_NUM_I_WAYS_SHIFT 6 |
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[9fcd1b35] | 148 | /** @brief Instruction cache line length 00 - 32 */ |
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[861d315] | 149 | #define L2C_310_TYPE_LENGTH_I_LINE_MASK 0x00000003 |
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| 150 | #define L2C_310_TYPE_LENGTH_I_LINE_SHIFT 0 |
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| 151 | #define L2C_310_TYPE_LENGTH_I_LINE_VAL_32 0x0 |
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[9fcd1b35] | 152 | |
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| 153 | uint8_t reserved_8[0x100 - 8]; |
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| 154 | uint32_t ctrl; /* Control */ |
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| 155 | /** @brief Enables the L2CC */ |
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[55741886] | 156 | #define L2C_310_CTRL_ENABLE 0x00000001 |
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| 157 | |
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| 158 | #define L2C_310_CTRL_EXCL_CONFIG (1 << 12) |
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[9fcd1b35] | 159 | |
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| 160 | /** @brief Auxiliary control */ |
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| 161 | uint32_t aux_ctrl; |
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| 162 | |
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| 163 | /** @brief Early BRESP Enable */ |
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[861d315] | 164 | #define L2C_310_AUX_EBRESPE_MASK 0x40000000 |
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[9fcd1b35] | 165 | |
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| 166 | /** @brief Instruction Prefetch Enable */ |
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[861d315] | 167 | #define L2C_310_AUX_IPFE_MASK 0x20000000 |
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[9fcd1b35] | 168 | |
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| 169 | /** @brief Data Prefetch Enable */ |
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[861d315] | 170 | #define L2C_310_AUX_DPFE_MASK 0x10000000 |
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[9fcd1b35] | 171 | |
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| 172 | /** @brief Non-secure interrupt access control */ |
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[861d315] | 173 | #define L2C_310_AUX_NSIC_MASK 0x08000000 |
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[9fcd1b35] | 174 | |
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| 175 | /** @brief Non-secure lockdown enable */ |
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[861d315] | 176 | #define L2C_310_AUX_NSLE_MASK 0x04000000 |
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[9fcd1b35] | 177 | |
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| 178 | /** @brief Cache replacement policy */ |
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[861d315] | 179 | #define L2C_310_AUX_CRP_MASK 0x02000000 |
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[9fcd1b35] | 180 | |
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| 181 | /** @brief Force write allocate */ |
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[861d315] | 182 | #define L2C_310_AUX_FWE_MASK 0x01800000 |
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[9fcd1b35] | 183 | |
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| 184 | /** @brief Shared attribute override enable */ |
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[861d315] | 185 | #define L2C_310_AUX_SAOE_MASK 0x00400000 |
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[9fcd1b35] | 186 | |
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| 187 | /** @brief Parity enable */ |
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[861d315] | 188 | #define L2C_310_AUX_PE_MASK 0x00200000 |
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[9fcd1b35] | 189 | |
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| 190 | /** @brief Event monitor bus enable */ |
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[861d315] | 191 | #define L2C_310_AUX_EMBE_MASK 0x00100000 |
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[9fcd1b35] | 192 | |
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| 193 | /** @brief Way-size */ |
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[861d315] | 194 | #define L2C_310_AUX_WAY_SIZE_MASK 0x000E0000 |
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| 195 | #define L2C_310_AUX_WAY_SIZE_SHIFT 17 |
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[9fcd1b35] | 196 | |
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| 197 | /** @brief Way-size */ |
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[861d315] | 198 | #define L2C_310_AUX_ASSOC_MASK 0x00010000 |
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[9fcd1b35] | 199 | |
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| 200 | /** @brief Shared attribute invalidate enable */ |
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[861d315] | 201 | #define L2C_310_AUX_SAIE_MASK 0x00002000 |
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[9fcd1b35] | 202 | |
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| 203 | /** @brief Exclusive cache configuration */ |
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[861d315] | 204 | #define L2C_310_AUX_EXCL_CACHE_MASK 0x00001000 |
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[9fcd1b35] | 205 | |
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| 206 | /** @brief Store buffer device limitation Enable */ |
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[861d315] | 207 | #define L2C_310_AUX_SBDLE_MASK 0x00000800 |
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[9fcd1b35] | 208 | |
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| 209 | /** @brief High Priority for SO and Dev Reads Enable */ |
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[861d315] | 210 | #define L2C_310_AUX_HPSODRE_MASK 0x00000400 |
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[9fcd1b35] | 211 | |
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| 212 | /** @brief Full line of zero enable */ |
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[861d315] | 213 | #define L2C_310_AUX_FLZE_MASK 0x00000001 |
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[9fcd1b35] | 214 | |
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| 215 | /** @brief Enable all prefetching, */ |
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[861d315] | 216 | #define L2C_310_AUX_REG_DEFAULT_MASK \ |
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| 217 | ( L2C_310_AUX_WAY_SIZE_MASK & ( 0x3 << L2C_310_AUX_WAY_SIZE_SHIFT ) ) \ |
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| 218 | | L2C_310_AUX_PE_MASK /* Prefetch enable */ \ |
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| 219 | | L2C_310_AUX_SAOE_MASK /* Shared attribute override enable */ \ |
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| 220 | | L2C_310_AUX_CRP_MASK /* Cache replacement policy */ \ |
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| 221 | | L2C_310_AUX_DPFE_MASK /* Data prefetch enable */ \ |
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| 222 | | L2C_310_AUX_IPFE_MASK /* Instruction prefetch enable */ \ |
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| 223 | | L2C_310_AUX_EBRESPE_MASK /* Early BRESP enable */ |
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[9fcd1b35] | 224 | |
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[861d315] | 225 | #define L2C_310_AUX_REG_ZERO_MASK 0xFFF1FFFF |
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[9fcd1b35] | 226 | |
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| 227 | /** @brief 1 cycle of latency, there is no additional latency fot tag RAM */ |
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[861d315] | 228 | #define L2C_310_RAM_1_CYCLE_LAT_VAL 0x00000000 |
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[9fcd1b35] | 229 | /** @brief 2 cycles of latency for tag RAM */ |
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[861d315] | 230 | #define L2C_310_RAM_2_CYCLE_LAT_VAL 0x00000001 |
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[9fcd1b35] | 231 | /** @brief 3 cycles of latency for tag RAM */ |
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[861d315] | 232 | #define L2C_310_RAM_3_CYCLE_LAT_VAL 0x00000002 |
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[9fcd1b35] | 233 | /** @brief 4 cycles of latency for tag RAM */ |
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[861d315] | 234 | #define L2C_310_RAM_4_CYCLE_LAT_VAL 0x00000003 |
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[9fcd1b35] | 235 | /** @brief 5 cycles of latency for tag RAM */ |
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[861d315] | 236 | #define L2C_310_RAM_5_CYCLE_LAT_VAL 0x00000004 |
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[9fcd1b35] | 237 | /** @brief 6 cycles of latency for tag RAM */ |
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[861d315] | 238 | #define L2C_310_RAM_6_CYCLE_LAT_VAL 0x00000005 |
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[9fcd1b35] | 239 | /** @brief 7 cycles of latency for tag RAM */ |
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[861d315] | 240 | #define L2C_310_RAM_7_CYCLE_LAT_VAL 0x00000006 |
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[9fcd1b35] | 241 | /** @brief 8 cycles of latency for tag RAM */ |
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[861d315] | 242 | #define L2C_310_RAM_8_CYCLE_LAT_VAL 0x00000007 |
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[9fcd1b35] | 243 | /** @brief Shift left setup latency values by this value */ |
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[861d315] | 244 | #define L2C_310_RAM_SETUP_SHIFT 0x00000000 |
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[9fcd1b35] | 245 | /** @brief Shift left read latency values by this value */ |
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[861d315] | 246 | #define L2C_310_RAM_READ_SHIFT 0x00000004 |
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[9fcd1b35] | 247 | /** @brief Shift left write latency values by this value */ |
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[861d315] | 248 | #define L2C_310_RAM_WRITE_SHIFT 0x00000008 |
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[9fcd1b35] | 249 | /** @brief Mask for RAM setup latency */ |
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[861d315] | 250 | #define L2C_310_RAM_SETUP_LAT_MASK 0x00000007 |
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[9fcd1b35] | 251 | /** @brief Mask for RAM read latency */ |
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[861d315] | 252 | #define L2C_310_RAM_READ_LAT_MASK 0x00000070 |
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[9fcd1b35] | 253 | /** @brief Mask for RAM read latency */ |
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[861d315] | 254 | #define L2C_310_RAM_WRITE_LAT_MASK 0x00000700 |
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[9fcd1b35] | 255 | /** @brief Latency for tag RAM */ |
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| 256 | uint32_t tag_ram_ctrl; |
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| 257 | /* @brief Latency for tag RAM */ |
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[861d315] | 258 | #define L2C_310_TAG_RAM_DEFAULT_LAT \ |
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| 259 | ( ( L2C_310_RAM_2_CYCLE_LAT_VAL << L2C_310_RAM_SETUP_SHIFT ) \ |
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| 260 | | ( L2C_310_RAM_2_CYCLE_LAT_VAL << L2C_310_RAM_READ_SHIFT ) \ |
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| 261 | | ( L2C_310_RAM_2_CYCLE_LAT_VAL << L2C_310_RAM_WRITE_SHIFT ) ) |
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[9fcd1b35] | 262 | /** @brief Latency for data RAM */ |
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| 263 | uint32_t data_ram_ctrl; |
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| 264 | /** @brief Latency for data RAM */ |
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[861d315] | 265 | #define L2C_310_DATA_RAM_DEFAULT_MASK \ |
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| 266 | ( ( L2C_310_RAM_2_CYCLE_LAT_VAL << L2C_310_RAM_SETUP_SHIFT ) \ |
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| 267 | | ( L2C_310_RAM_3_CYCLE_LAT_VAL << L2C_310_RAM_READ_SHIFT ) \ |
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| 268 | | ( L2C_310_RAM_2_CYCLE_LAT_VAL << L2C_310_RAM_WRITE_SHIFT ) ) |
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[9fcd1b35] | 269 | |
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| 270 | uint8_t reserved_110[0x200 - 0x110]; |
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| 271 | |
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| 272 | /** @brief Event counter control */ |
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| 273 | uint32_t ev_ctrl; |
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| 274 | |
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| 275 | /** @brief Event counter 1 configuration */ |
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| 276 | uint32_t ev_cnt1_cfg; |
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| 277 | |
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| 278 | /** @brief Event counter 0 configuration */ |
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| 279 | uint32_t ev_cnt0_cfg; |
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| 280 | |
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| 281 | /** @brief Event counter 1 value */ |
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| 282 | uint32_t ev_cnt1; |
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| 283 | |
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| 284 | /** @brief Event counter 0 value */ |
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| 285 | uint32_t ev_cnt0; |
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| 286 | |
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| 287 | /** @brief Interrupt enable mask */ |
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| 288 | uint32_t int_mask; |
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| 289 | |
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| 290 | /** @brief Masked interrupt status (read-only)*/ |
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| 291 | uint32_t int_mask_status; |
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| 292 | |
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| 293 | /** @brief Unmasked interrupt status */ |
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| 294 | uint32_t int_raw_status; |
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| 295 | |
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| 296 | /** @brief Interrupt clear */ |
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| 297 | uint32_t int_clr; |
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| 298 | |
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| 299 | /** |
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| 300 | * @name Interrupt bit masks |
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| 301 | * |
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| 302 | * @{ |
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| 303 | */ |
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| 304 | |
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| 305 | /** @brief DECERR from L3 */ |
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[861d315] | 306 | #define L2C_310_INT_DECERR_MASK 0x00000100 |
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[9fcd1b35] | 307 | |
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| 308 | /** @brief SLVERR from L3 */ |
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[861d315] | 309 | #define L2C_310_INT_SLVERR_MASK 0x00000080 |
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[9fcd1b35] | 310 | |
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| 311 | /** @brief Error on L2 data RAM (Read) */ |
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[861d315] | 312 | #define L2C_310_INT_ERRRD_MASK 0x00000040 |
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[9fcd1b35] | 313 | |
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| 314 | /** @brief Error on L2 tag RAM (Read) */ |
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[861d315] | 315 | #define L2C_310_INT_ERRRT_MASK 0x00000020 |
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[9fcd1b35] | 316 | |
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| 317 | /** @brief Error on L2 data RAM (Write) */ |
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[861d315] | 318 | #define L2C_310_INT_ERRWD_MASK 0x00000010 |
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[9fcd1b35] | 319 | |
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| 320 | /** @brief Error on L2 tag RAM (Write) */ |
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[861d315] | 321 | #define L2C_310_INT_ERRWT_MASK 0x00000008 |
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[9fcd1b35] | 322 | |
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| 323 | /** @brief Parity Error on L2 data RAM (Read) */ |
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[861d315] | 324 | #define L2C_310_INT_PARRD_MASK 0x00000004 |
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[9fcd1b35] | 325 | |
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| 326 | /** @brief Parity Error on L2 tag RAM (Read) */ |
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[861d315] | 327 | #define L2C_310_INT_PARRT_MASK 0x00000002 |
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[9fcd1b35] | 328 | |
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| 329 | /** @brief Event Counter1/0 Overflow Increment */ |
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[861d315] | 330 | #define L2C_310_INT_ECNTR_MASK 0x00000001 |
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[9fcd1b35] | 331 | |
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| 332 | /** @} */ |
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| 333 | |
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| 334 | uint8_t reserved_224[0x730 - 0x224]; |
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| 335 | |
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| 336 | /** @brief Drain the STB */ |
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| 337 | uint32_t cache_sync; |
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| 338 | uint8_t reserved_734[0x740 - 0x734]; |
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| 339 | /** @brief ARM Errata 753970 for pl310-r3p0 */ |
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| 340 | uint32_t dummy_cache_sync_reg; |
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| 341 | uint8_t reserved_744[0x770 - 0x744]; |
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| 342 | |
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| 343 | /** @brief Invalidate line by PA */ |
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| 344 | uint32_t inv_pa; |
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| 345 | uint8_t reserved_774[0x77c - 0x774]; |
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| 346 | |
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| 347 | /** @brief Invalidate by Way */ |
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| 348 | uint32_t inv_way; |
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| 349 | uint8_t reserved_780[0x7b0 - 0x780]; |
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| 350 | |
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| 351 | /** @brief Clean Line by PA */ |
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| 352 | uint32_t clean_pa; |
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| 353 | uint8_t reserved_7b4[0x7b8 - 0x7b4]; |
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| 354 | |
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| 355 | /** @brief Clean Line by Set/Way */ |
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| 356 | uint32_t clean_index; |
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| 357 | |
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| 358 | /** @brief Clean by Way */ |
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| 359 | uint32_t clean_way; |
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| 360 | uint8_t reserved_7c0[0x7f0 - 0x7c0]; |
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| 361 | |
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| 362 | /** @brief Clean and Invalidate Line by PA */ |
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| 363 | uint32_t clean_inv_pa; |
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| 364 | uint8_t reserved_7f4[0x7f8 - 0x7f4]; |
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| 365 | |
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| 366 | /** @brief Clean and Invalidate Line by Set/Way */ |
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| 367 | uint32_t clean_inv_indx; |
---|
| 368 | |
---|
| 369 | /** @brief Clean and Invalidate by Way */ |
---|
| 370 | uint32_t clean_inv_way; |
---|
| 371 | |
---|
| 372 | /** @brief Data lock down 0 */ |
---|
| 373 | uint32_t d_lockdown_0; |
---|
| 374 | |
---|
| 375 | /** @brief Instruction lock down 0 */ |
---|
| 376 | uint32_t i_lockdown_0; |
---|
| 377 | |
---|
| 378 | /** @brief Data lock down 1 */ |
---|
| 379 | uint32_t d_lockdown_1; |
---|
| 380 | |
---|
| 381 | /** @brief Instruction lock down 1 */ |
---|
| 382 | uint32_t i_lockdown_1; |
---|
| 383 | |
---|
| 384 | /** @brief Data lock down 2 */ |
---|
| 385 | uint32_t d_lockdown_2; |
---|
| 386 | |
---|
| 387 | /** @brief Instruction lock down 2 */ |
---|
| 388 | uint32_t i_lockdown_2; |
---|
| 389 | |
---|
| 390 | /** @brief Data lock down 3 */ |
---|
| 391 | uint32_t d_lockdown_3; |
---|
| 392 | |
---|
| 393 | /** @brief Instruction lock down 3 */ |
---|
| 394 | uint32_t i_lockdown_3; |
---|
| 395 | |
---|
| 396 | /** @brief Data lock down 4 */ |
---|
| 397 | uint32_t d_lockdown_4; |
---|
| 398 | |
---|
| 399 | /** @brief Instruction lock down 4 */ |
---|
| 400 | uint32_t i_lockdown_4; |
---|
| 401 | |
---|
| 402 | /** @brief Data lock down 5 */ |
---|
| 403 | uint32_t d_lockdown_5; |
---|
| 404 | |
---|
| 405 | /** @brief Instruction lock down 5 */ |
---|
| 406 | uint32_t i_lockdown_5; |
---|
| 407 | |
---|
| 408 | /** @brief Data lock down 6 */ |
---|
| 409 | uint32_t d_lockdown_6; |
---|
| 410 | |
---|
| 411 | /** @brief Instruction lock down 6 */ |
---|
| 412 | uint32_t i_lockdown_6; |
---|
| 413 | |
---|
| 414 | /** @brief Data lock down 7 */ |
---|
| 415 | uint32_t d_lockdown_7; |
---|
| 416 | |
---|
| 417 | /** @brief Instruction lock down 7 */ |
---|
| 418 | uint32_t i_lockdown_7; |
---|
| 419 | |
---|
| 420 | uint8_t reserved_940[0x950 - 0x940]; |
---|
| 421 | |
---|
| 422 | /** @brief Lockdown by Line Enable */ |
---|
| 423 | uint32_t lock_line_en; |
---|
| 424 | |
---|
| 425 | /** @brief Cache lockdown by way */ |
---|
| 426 | uint32_t unlock_way; |
---|
| 427 | |
---|
| 428 | uint8_t reserved_958[0xc00 - 0x958]; |
---|
| 429 | |
---|
| 430 | /** @brief Address range redirect, part 1 */ |
---|
| 431 | uint32_t addr_filtering_start; |
---|
| 432 | |
---|
| 433 | /** @brief Address range redirect, part 2 */ |
---|
| 434 | uint32_t addr_filtering_end; |
---|
| 435 | |
---|
| 436 | /** @brief Address filtering valid bits*/ |
---|
[861d315] | 437 | #define L2C_310_ADDR_FILTER_VALID_MASK 0xFFF00000 |
---|
[9fcd1b35] | 438 | |
---|
| 439 | /** @brief Address filtering enable bit*/ |
---|
[861d315] | 440 | #define L2C_310_ADDR_FILTER_ENABLE_MASK 0x00000001 |
---|
[9fcd1b35] | 441 | |
---|
| 442 | uint8_t reserved_c08[0xf40 - 0xc08]; |
---|
| 443 | |
---|
| 444 | /** @brief Debug control */ |
---|
| 445 | uint32_t debug_ctrl; |
---|
| 446 | |
---|
| 447 | /** @brief Debug SPIDEN bit */ |
---|
[861d315] | 448 | #define L2C_310_DEBUG_SPIDEN_MASK 0x00000004 |
---|
[9fcd1b35] | 449 | |
---|
| 450 | /** @brief Debug DWB bit, forces write through */ |
---|
[861d315] | 451 | #define L2C_310_DEBUG_DWB_MASK 0x00000002 |
---|
[9fcd1b35] | 452 | |
---|
| 453 | /** @brief Debug DCL bit, disables cache line fill */ |
---|
[861d315] | 454 | #define L2C_310_DEBUG_DCL_MASK 0x00000002 |
---|
[9fcd1b35] | 455 | |
---|
| 456 | uint8_t reserved_f44[0xf60 - 0xf44]; |
---|
| 457 | |
---|
| 458 | /** @brief Purpose prefetch enables */ |
---|
| 459 | uint32_t prefetch_ctrl; |
---|
| 460 | /** @brief Prefetch offset */ |
---|
[861d315] | 461 | #define L2C_310_PREFETCH_OFFSET_MASK 0x0000001F |
---|
[9fcd1b35] | 462 | uint8_t reserved_f64[0xf80 - 0xf64]; |
---|
| 463 | |
---|
| 464 | /** @brief Purpose power controls */ |
---|
| 465 | uint32_t power_ctrl; |
---|
| 466 | } L2CC; |
---|
| 467 | |
---|
[d53de34] | 468 | rtems_interrupt_lock l2c_310_lock = RTEMS_INTERRUPT_LOCK_INITIALIZER( |
---|
[d1eb7b1] | 469 | "L2-310 cache controller" |
---|
[1c62f74d] | 470 | ); |
---|
| 471 | |
---|
[9fcd1b35] | 472 | /* Errata table for the LC2 310 Level 2 cache from ARM. |
---|
| 473 | * Information taken from ARMs |
---|
| 474 | * "CoreLink controllers and peripherals |
---|
| 475 | * - System controllers |
---|
| 476 | * - L2C-310 Level 2 Cache Controller |
---|
| 477 | * - Revision r3p3 |
---|
| 478 | * - Software Developer Errata Notice |
---|
[d98eea0] | 479 | * - ARM CoreLink Level 2 Cache Controller (L2C-310 or PL310), |
---|
[9fcd1b35] | 480 | * r3 releases Software Developers Errata Notice" |
---|
| 481 | * Please see this document for more information on these erratas */ |
---|
[52d24b00] | 482 | #if BSP_ARM_L2C_310_RTL_RELEASE == L2C_310_RTL_RELEASE_R3_P0 |
---|
| 483 | #define L2C_310_ERRATA_IS_APPLICABLE_753970 |
---|
| 484 | #endif |
---|
[9fcd1b35] | 485 | |
---|
[d53de34] | 486 | static bool l2c_310_errata_is_applicable_727913( |
---|
[52d24b00] | 487 | uint32_t rtl_release |
---|
[9fcd1b35] | 488 | ) |
---|
| 489 | { |
---|
[a9d6c20] | 490 | bool is_applicable = false; |
---|
| 491 | |
---|
| 492 | switch ( rtl_release ) { |
---|
[861d315] | 493 | case L2C_310_RTL_RELEASE_R3_P3: |
---|
| 494 | case L2C_310_RTL_RELEASE_R3_P2: |
---|
| 495 | case L2C_310_RTL_RELEASE_R3_P1: |
---|
| 496 | case L2C_310_RTL_RELEASE_R2_P0: |
---|
| 497 | case L2C_310_RTL_RELEASE_R1_P0: |
---|
| 498 | case L2C_310_RTL_RELEASE_R0_P0: |
---|
[9fcd1b35] | 499 | is_applicable = false; |
---|
[a9d6c20] | 500 | break; |
---|
[861d315] | 501 | case L2C_310_RTL_RELEASE_R3_P0: |
---|
[9fcd1b35] | 502 | is_applicable = true; |
---|
[a9d6c20] | 503 | break; |
---|
[9fcd1b35] | 504 | default: |
---|
[a9d6c20] | 505 | assert( 0 ); |
---|
| 506 | break; |
---|
[9fcd1b35] | 507 | } |
---|
[a9d6c20] | 508 | |
---|
[9fcd1b35] | 509 | return is_applicable; |
---|
| 510 | } |
---|
| 511 | |
---|
[d53de34] | 512 | static bool l2c_310_errata_is_applicable_727914( |
---|
[52d24b00] | 513 | uint32_t rtl_release |
---|
[9fcd1b35] | 514 | ) |
---|
| 515 | { |
---|
[a9d6c20] | 516 | bool is_applicable = false; |
---|
| 517 | |
---|
| 518 | switch ( rtl_release ) { |
---|
[861d315] | 519 | case L2C_310_RTL_RELEASE_R3_P3: |
---|
| 520 | case L2C_310_RTL_RELEASE_R3_P2: |
---|
| 521 | case L2C_310_RTL_RELEASE_R3_P1: |
---|
| 522 | case L2C_310_RTL_RELEASE_R2_P0: |
---|
| 523 | case L2C_310_RTL_RELEASE_R1_P0: |
---|
| 524 | case L2C_310_RTL_RELEASE_R0_P0: |
---|
[9fcd1b35] | 525 | is_applicable = false; |
---|
[a9d6c20] | 526 | break; |
---|
[861d315] | 527 | case L2C_310_RTL_RELEASE_R3_P0: |
---|
[9fcd1b35] | 528 | is_applicable = true; |
---|
[a9d6c20] | 529 | break; |
---|
[9fcd1b35] | 530 | default: |
---|
[a9d6c20] | 531 | assert( 0 ); |
---|
| 532 | break; |
---|
[9fcd1b35] | 533 | } |
---|
[a9d6c20] | 534 | |
---|
[9fcd1b35] | 535 | return is_applicable; |
---|
| 536 | } |
---|
| 537 | |
---|
[d53de34] | 538 | static bool l2c_310_errata_is_applicable_727915( |
---|
[52d24b00] | 539 | uint32_t rtl_release |
---|
[9fcd1b35] | 540 | ) |
---|
| 541 | { |
---|
[a9d6c20] | 542 | bool is_applicable = false; |
---|
| 543 | |
---|
| 544 | switch ( rtl_release ) { |
---|
[861d315] | 545 | case L2C_310_RTL_RELEASE_R3_P3: |
---|
| 546 | case L2C_310_RTL_RELEASE_R3_P2: |
---|
| 547 | case L2C_310_RTL_RELEASE_R3_P1: |
---|
| 548 | case L2C_310_RTL_RELEASE_R1_P0: |
---|
| 549 | case L2C_310_RTL_RELEASE_R0_P0: |
---|
[9fcd1b35] | 550 | is_applicable = false; |
---|
[a9d6c20] | 551 | break; |
---|
[861d315] | 552 | case L2C_310_RTL_RELEASE_R3_P0: |
---|
| 553 | case L2C_310_RTL_RELEASE_R2_P0: |
---|
[9fcd1b35] | 554 | is_applicable = true; |
---|
[a9d6c20] | 555 | break; |
---|
[9fcd1b35] | 556 | default: |
---|
[a9d6c20] | 557 | assert( 0 ); |
---|
| 558 | break; |
---|
[9fcd1b35] | 559 | } |
---|
[a9d6c20] | 560 | |
---|
[9fcd1b35] | 561 | return is_applicable; |
---|
| 562 | } |
---|
| 563 | |
---|
[d53de34] | 564 | static bool l2c_310_errata_is_applicable_729806( |
---|
[52d24b00] | 565 | uint32_t rtl_release |
---|
[9fcd1b35] | 566 | ) |
---|
| 567 | { |
---|
[a9d6c20] | 568 | bool is_applicable = false; |
---|
| 569 | |
---|
| 570 | switch ( rtl_release ) { |
---|
[861d315] | 571 | case L2C_310_RTL_RELEASE_R3_P3: |
---|
| 572 | case L2C_310_RTL_RELEASE_R3_P2: |
---|
| 573 | case L2C_310_RTL_RELEASE_R2_P0: |
---|
| 574 | case L2C_310_RTL_RELEASE_R1_P0: |
---|
| 575 | case L2C_310_RTL_RELEASE_R0_P0: |
---|
[9fcd1b35] | 576 | is_applicable = false; |
---|
[a9d6c20] | 577 | break; |
---|
[861d315] | 578 | case L2C_310_RTL_RELEASE_R3_P1: |
---|
| 579 | case L2C_310_RTL_RELEASE_R3_P0: |
---|
[9fcd1b35] | 580 | is_applicable = true; |
---|
[a9d6c20] | 581 | break; |
---|
[9fcd1b35] | 582 | default: |
---|
[a9d6c20] | 583 | assert( 0 ); |
---|
| 584 | break; |
---|
[9fcd1b35] | 585 | } |
---|
[a9d6c20] | 586 | |
---|
[9fcd1b35] | 587 | return is_applicable; |
---|
| 588 | } |
---|
| 589 | |
---|
[d53de34] | 590 | static bool l2c_310_errata_is_applicable_729815( |
---|
[52d24b00] | 591 | uint32_t rtl_release |
---|
[9fcd1b35] | 592 | ) |
---|
| 593 | { |
---|
[a9d6c20] | 594 | bool is_applicable = false; |
---|
| 595 | |
---|
| 596 | switch ( rtl_release ) { |
---|
[861d315] | 597 | case L2C_310_RTL_RELEASE_R3_P3: |
---|
| 598 | case L2C_310_RTL_RELEASE_R1_P0: |
---|
| 599 | case L2C_310_RTL_RELEASE_R0_P0: |
---|
[9fcd1b35] | 600 | is_applicable = false; |
---|
[a9d6c20] | 601 | break; |
---|
[861d315] | 602 | case L2C_310_RTL_RELEASE_R3_P2: |
---|
| 603 | case L2C_310_RTL_RELEASE_R3_P1: |
---|
| 604 | case L2C_310_RTL_RELEASE_R3_P0: |
---|
| 605 | case L2C_310_RTL_RELEASE_R2_P0: |
---|
[9fcd1b35] | 606 | is_applicable = true; |
---|
[a9d6c20] | 607 | break; |
---|
[9fcd1b35] | 608 | default: |
---|
[a9d6c20] | 609 | assert( 0 ); |
---|
| 610 | break; |
---|
[9fcd1b35] | 611 | } |
---|
[a9d6c20] | 612 | |
---|
[9fcd1b35] | 613 | return is_applicable; |
---|
| 614 | } |
---|
| 615 | |
---|
[d53de34] | 616 | static bool l2c_310_errata_is_applicable_742884( |
---|
[52d24b00] | 617 | uint32_t rtl_release |
---|
[9fcd1b35] | 618 | ) |
---|
| 619 | { |
---|
[a9d6c20] | 620 | bool is_applicable = false; |
---|
| 621 | |
---|
| 622 | switch ( rtl_release ) { |
---|
[861d315] | 623 | case L2C_310_RTL_RELEASE_R3_P3: |
---|
| 624 | case L2C_310_RTL_RELEASE_R3_P2: |
---|
| 625 | case L2C_310_RTL_RELEASE_R3_P0: |
---|
| 626 | case L2C_310_RTL_RELEASE_R2_P0: |
---|
| 627 | case L2C_310_RTL_RELEASE_R1_P0: |
---|
| 628 | case L2C_310_RTL_RELEASE_R0_P0: |
---|
[9fcd1b35] | 629 | is_applicable = false; |
---|
[a9d6c20] | 630 | break; |
---|
[861d315] | 631 | case L2C_310_RTL_RELEASE_R3_P1: |
---|
[9fcd1b35] | 632 | is_applicable = true; |
---|
[a9d6c20] | 633 | break; |
---|
[9fcd1b35] | 634 | default: |
---|
[a9d6c20] | 635 | assert( 0 ); |
---|
| 636 | break; |
---|
[9fcd1b35] | 637 | } |
---|
[a9d6c20] | 638 | |
---|
[9fcd1b35] | 639 | return is_applicable; |
---|
| 640 | } |
---|
| 641 | |
---|
[d53de34] | 642 | static bool l2c_310_errata_is_applicable_752271( |
---|
[52d24b00] | 643 | uint32_t rtl_release |
---|
[9fcd1b35] | 644 | ) |
---|
| 645 | { |
---|
[a9d6c20] | 646 | bool is_applicable = false; |
---|
| 647 | |
---|
| 648 | switch ( rtl_release ) { |
---|
[861d315] | 649 | case L2C_310_RTL_RELEASE_R3_P3: |
---|
| 650 | case L2C_310_RTL_RELEASE_R3_P2: |
---|
| 651 | case L2C_310_RTL_RELEASE_R2_P0: |
---|
| 652 | case L2C_310_RTL_RELEASE_R1_P0: |
---|
| 653 | case L2C_310_RTL_RELEASE_R0_P0: |
---|
[9fcd1b35] | 654 | is_applicable = false; |
---|
[a9d6c20] | 655 | break; |
---|
[861d315] | 656 | case L2C_310_RTL_RELEASE_R3_P1: |
---|
| 657 | case L2C_310_RTL_RELEASE_R3_P0: |
---|
[9fcd1b35] | 658 | is_applicable = true; |
---|
[a9d6c20] | 659 | break; |
---|
[9fcd1b35] | 660 | default: |
---|
[a9d6c20] | 661 | assert( 0 ); |
---|
| 662 | break; |
---|
[9fcd1b35] | 663 | } |
---|
[a9d6c20] | 664 | |
---|
[9fcd1b35] | 665 | return is_applicable; |
---|
| 666 | } |
---|
| 667 | |
---|
[d53de34] | 668 | static bool l2c_310_errata_is_applicable_765569( |
---|
[52d24b00] | 669 | uint32_t rtl_release |
---|
[9fcd1b35] | 670 | ) |
---|
| 671 | { |
---|
[a9d6c20] | 672 | bool is_applicable = false; |
---|
| 673 | |
---|
| 674 | switch ( rtl_release ) { |
---|
[861d315] | 675 | case L2C_310_RTL_RELEASE_R3_P3: |
---|
| 676 | case L2C_310_RTL_RELEASE_R3_P2: |
---|
| 677 | case L2C_310_RTL_RELEASE_R3_P1: |
---|
| 678 | case L2C_310_RTL_RELEASE_R3_P0: |
---|
| 679 | case L2C_310_RTL_RELEASE_R2_P0: |
---|
| 680 | case L2C_310_RTL_RELEASE_R1_P0: |
---|
| 681 | case L2C_310_RTL_RELEASE_R0_P0: |
---|
[9fcd1b35] | 682 | is_applicable = true; |
---|
[a9d6c20] | 683 | break; |
---|
[9fcd1b35] | 684 | default: |
---|
[a9d6c20] | 685 | assert( 0 ); |
---|
| 686 | break; |
---|
[9fcd1b35] | 687 | } |
---|
[a9d6c20] | 688 | |
---|
[9fcd1b35] | 689 | return is_applicable; |
---|
| 690 | } |
---|
| 691 | |
---|
[d53de34] | 692 | static bool l2c_310_errata_is_applicable_769419( |
---|
[52d24b00] | 693 | uint32_t rtl_release |
---|
[9fcd1b35] | 694 | ) |
---|
| 695 | { |
---|
[a9d6c20] | 696 | bool is_applicable = false; |
---|
| 697 | |
---|
| 698 | switch ( rtl_release ) { |
---|
[861d315] | 699 | case L2C_310_RTL_RELEASE_R3_P3: |
---|
| 700 | case L2C_310_RTL_RELEASE_R3_P2: |
---|
[9fcd1b35] | 701 | is_applicable = false; |
---|
[a9d6c20] | 702 | break; |
---|
[861d315] | 703 | case L2C_310_RTL_RELEASE_R3_P1: |
---|
| 704 | case L2C_310_RTL_RELEASE_R3_P0: |
---|
| 705 | case L2C_310_RTL_RELEASE_R2_P0: |
---|
| 706 | case L2C_310_RTL_RELEASE_R1_P0: |
---|
| 707 | case L2C_310_RTL_RELEASE_R0_P0: |
---|
[9fcd1b35] | 708 | is_applicable = true; |
---|
[a9d6c20] | 709 | break; |
---|
[9fcd1b35] | 710 | default: |
---|
[a9d6c20] | 711 | assert( 0 ); |
---|
| 712 | break; |
---|
[9fcd1b35] | 713 | } |
---|
[a9d6c20] | 714 | |
---|
[9fcd1b35] | 715 | return is_applicable; |
---|
| 716 | } |
---|
| 717 | |
---|
[e492e7f8] | 718 | #if BSP_ARM_L2C_310_RTL_RELEASE == L2C_310_RTL_RELEASE_R0_P0 \ |
---|
| 719 | || BSP_ARM_L2C_310_RTL_RELEASE == L2C_310_RTL_RELEASE_R1_P0 |
---|
| 720 | #define L2C_310_ERRATA_IS_APPLICABLE_588369 |
---|
| 721 | #endif |
---|
[9fcd1b35] | 722 | |
---|
| 723 | #ifdef CACHE_ERRATA_CHECKS_FOR_IMPLEMENTED_ERRATAS |
---|
[d53de34] | 724 | static bool l2c_310_errata_is_applicable_754670( |
---|
[52d24b00] | 725 | uint32_t rtl_release |
---|
[9fcd1b35] | 726 | ) |
---|
| 727 | { |
---|
[a9d6c20] | 728 | bool is_applicable = false; |
---|
| 729 | |
---|
| 730 | switch ( rtl_release ) { |
---|
[861d315] | 731 | case L2C_310_RTL_RELEASE_R3_P3: |
---|
| 732 | case L2C_310_RTL_RELEASE_R3_P2: |
---|
| 733 | case L2C_310_RTL_RELEASE_R3_P1: |
---|
| 734 | case L2C_310_RTL_RELEASE_R3_P0: |
---|
| 735 | case L2C_310_RTL_RELEASE_R2_P0: |
---|
| 736 | case L2C_310_RTL_RELEASE_R1_P0: |
---|
| 737 | case L2C_310_RTL_RELEASE_R0_P0: |
---|
[9fcd1b35] | 738 | is_applicable = true; |
---|
| 739 | break; |
---|
| 740 | default: |
---|
[a9d6c20] | 741 | assert( 0 ); |
---|
| 742 | break; |
---|
[9fcd1b35] | 743 | } |
---|
[a9d6c20] | 744 | |
---|
[9fcd1b35] | 745 | return is_applicable; |
---|
| 746 | } |
---|
| 747 | #endif /* CACHE_ERRATA_CHECKS_FOR_IMPLEMENTED_ERRATAS */ |
---|
| 748 | |
---|
[a9d6c20] | 749 | /* The common workaround for this erratum would be to add a |
---|
[9fcd1b35] | 750 | * data synchronization barrier to the beginning of the abort handler. |
---|
[a9d6c20] | 751 | * But for RTEMS a call of the abort handler means a fatal condition anyway. |
---|
[9fcd1b35] | 752 | * So there is no need to handle this erratum */ |
---|
| 753 | #define CACHE_ARM_ERRATA_775420_HANDLER() \ |
---|
| 754 | if( arm_errata_is_applicable_processor_errata_775420 ) { \ |
---|
| 755 | } \ |
---|
| 756 | |
---|
[52d24b00] | 757 | static void l2c_310_check_errata( uint32_t rtl_release ) |
---|
[9fcd1b35] | 758 | { |
---|
| 759 | /* This erratum gets handled within the sources */ |
---|
[a9d6c20] | 760 | /* Unhandled erratum present: 588369 Errata 588369 says that clean + inv may |
---|
[9fcd1b35] | 761 | * keep the cache line if it was clean. See ARMs documentation on the erratum |
---|
| 762 | * for a workaround */ |
---|
[d53de34] | 763 | /* assert( ! l2c_310_errata_is_applicable_588369( rtl_release ) ); */ |
---|
[9fcd1b35] | 764 | |
---|
[a9d6c20] | 765 | /* Unhandled erratum present: 727913 Prefetch dropping feature can cause |
---|
| 766 | * incorrect behavior when PL310 handles reads that cross cache line |
---|
[9fcd1b35] | 767 | * boundary */ |
---|
[d53de34] | 768 | assert( ! l2c_310_errata_is_applicable_727913( rtl_release ) ); |
---|
[9fcd1b35] | 769 | |
---|
[a9d6c20] | 770 | /* Unhandled erratum present: 727914 Double linefill feature can cause |
---|
[9fcd1b35] | 771 | * deadlock */ |
---|
[d53de34] | 772 | assert( ! l2c_310_errata_is_applicable_727914( rtl_release ) ); |
---|
[a9d6c20] | 773 | |
---|
| 774 | /* Unhandled erratum present: 727915 Background Clean and Invalidate by Way |
---|
[9fcd1b35] | 775 | * operation can cause data corruption */ |
---|
[d53de34] | 776 | assert( ! l2c_310_errata_is_applicable_727915( rtl_release ) ); |
---|
[9fcd1b35] | 777 | |
---|
[a9d6c20] | 778 | /* Unhandled erratum present: 729806 Speculative reads from the Cortex-A9 |
---|
[9fcd1b35] | 779 | * MPCore processor can cause deadlock */ |
---|
[d53de34] | 780 | assert( ! l2c_310_errata_is_applicable_729806( rtl_release ) ); |
---|
[9fcd1b35] | 781 | |
---|
[d53de34] | 782 | if( l2c_310_errata_is_applicable_729815( rtl_release ) ) |
---|
[9fcd1b35] | 783 | { |
---|
[957c075] | 784 | volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; |
---|
[9fcd1b35] | 785 | |
---|
[861d315] | 786 | assert( 0 == ( l2cc->aux_ctrl & L2C_310_AUX_HPSODRE_MASK ) ); |
---|
[9fcd1b35] | 787 | |
---|
[a9d6c20] | 788 | /* Erratum: 729815 The âHigh Priority for SO and Dev readsâ feature can |
---|
[9fcd1b35] | 789 | * cause Quality of Service issues to cacheable read transactions*/ |
---|
| 790 | |
---|
| 791 | /* Conditions |
---|
| 792 | This problem occurs when the following conditions are met: |
---|
[a9d6c20] | 793 | 1. Bit[10] âHigh Priority for SO and Dev reads enableâ of the PL310 |
---|
[9fcd1b35] | 794 | Auxiliary Control Register is set to 1. |
---|
| 795 | 2. PL310 receives a cacheable read that misses in the L2 cache. |
---|
[a9d6c20] | 796 | 3. PL310 receives a continuous flow of Strongly Ordered or Device |
---|
[9fcd1b35] | 797 | reads that take all address slots in the master interface. |
---|
| 798 | Workaround |
---|
[a9d6c20] | 799 | A workaround is only necessary in systems that are able to issue a |
---|
| 800 | continuous flow of Strongly Ordered or Device reads. In such a case, |
---|
| 801 | the workaround is to disable the âHigh Priority for SO and Dev readsâ |
---|
[9fcd1b35] | 802 | feature. This is the default behavior.*/ |
---|
| 803 | } |
---|
[a9d6c20] | 804 | |
---|
| 805 | /* Unhandled erratum present: 742884 Double linefill feature might introduce |
---|
[9fcd1b35] | 806 | * circular dependency and deadlock */ |
---|
[d53de34] | 807 | assert( ! l2c_310_errata_is_applicable_742884( rtl_release ) ); |
---|
[9fcd1b35] | 808 | |
---|
[a9d6c20] | 809 | /* Unhandled erratum present: 752271 Double linefill feature can cause data |
---|
[9fcd1b35] | 810 | * corruption */ |
---|
[d53de34] | 811 | assert( ! l2c_310_errata_is_applicable_752271( rtl_release ) ); |
---|
[9fcd1b35] | 812 | |
---|
[a9d6c20] | 813 | /* This erratum can not be worked around: 754670 A continuous write flow can |
---|
[9fcd1b35] | 814 | * stall a read targeting the same memory area |
---|
| 815 | * But this erratum does not lead to any data corruption */ |
---|
[d53de34] | 816 | /* assert( ! l2c_310_errata_is_applicable_754670() ); */ |
---|
[9fcd1b35] | 817 | |
---|
[d53de34] | 818 | if( l2c_310_errata_is_applicable_765569( rtl_release ) ) |
---|
[9fcd1b35] | 819 | { |
---|
[957c075] | 820 | volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; |
---|
[9fcd1b35] | 821 | |
---|
[861d315] | 822 | assert( !( ( l2cc->aux_ctrl & L2C_310_AUX_IPFE_MASK |
---|
| 823 | || l2cc->aux_ctrl & L2C_310_AUX_DPFE_MASK ) |
---|
| 824 | && ( ( l2cc->prefetch_ctrl & L2C_310_PREFETCH_OFFSET_MASK ) |
---|
[9fcd1b35] | 825 | == 23 ) ) ); |
---|
| 826 | |
---|
[a9d6c20] | 827 | /* Unhandled erratum present: 765569 Prefetcher can cross 4KB boundary if |
---|
[9fcd1b35] | 828 | * offset is programmed with value 23 */ |
---|
| 829 | |
---|
| 830 | /* Conditions |
---|
| 831 | This problem occurs when the following conditions are met: |
---|
[a9d6c20] | 832 | 1. One of the Prefetch Enable bits (bits [29:28] of the Auxiliary or |
---|
[9fcd1b35] | 833 | Prefetch Control Register) is set HIGH. |
---|
| 834 | 2. The prefetch offset bits are programmed with value 23 (5'b10111). |
---|
| 835 | Workaround |
---|
| 836 | A workaround for this erratum is to program the prefetch offset with any |
---|
| 837 | value except 23.*/ |
---|
| 838 | } |
---|
| 839 | |
---|
[a9d6c20] | 840 | /* Unhandled erratum present: 769419 No automatic Store Buffer drain, |
---|
[9fcd1b35] | 841 | * visibility of written data requires an explicit Cache */ |
---|
[d53de34] | 842 | assert( ! l2c_310_errata_is_applicable_769419( rtl_release ) ); |
---|
[9fcd1b35] | 843 | } |
---|
| 844 | |
---|
| 845 | static inline void |
---|
[52d24b00] | 846 | l2c_310_sync( volatile L2CC *l2cc ) |
---|
[9fcd1b35] | 847 | { |
---|
[52d24b00] | 848 | #ifdef L2C_310_ERRATA_IS_APPLICABLE_753970 |
---|
| 849 | l2cc->dummy_cache_sync_reg = 0; |
---|
| 850 | #else |
---|
| 851 | l2cc->cache_sync = 0; |
---|
| 852 | #endif |
---|
[9fcd1b35] | 853 | } |
---|
| 854 | |
---|
| 855 | static inline void |
---|
[e492e7f8] | 856 | l2c_310_flush_1_line( volatile L2CC *l2cc, uint32_t d_addr ) |
---|
[9fcd1b35] | 857 | { |
---|
[e492e7f8] | 858 | #ifdef L2C_310_ERRATA_IS_APPLICABLE_588369 |
---|
| 859 | /* |
---|
| 860 | * Errata 588369 says that clean + inv may keep the |
---|
| 861 | * cache line if it was clean, the recommended |
---|
| 862 | * workaround is to clean then invalidate the cache |
---|
| 863 | * line, with write-back and cache linefill disabled. |
---|
| 864 | */ |
---|
| 865 | l2cc->clean_pa = d_addr; |
---|
| 866 | l2c_310_sync( l2cc ); |
---|
| 867 | l2cc->inv_pa = d_addr; |
---|
| 868 | #else |
---|
| 869 | l2cc->clean_inv_pa = d_addr; |
---|
| 870 | #endif |
---|
[9fcd1b35] | 871 | } |
---|
| 872 | |
---|
| 873 | static inline void |
---|
[d53de34] | 874 | l2c_310_flush_range( const void* d_addr, const size_t n_bytes ) |
---|
[9fcd1b35] | 875 | { |
---|
[92e2757] | 876 | /* Back starting address up to start of a line and invalidate until ADDR_LAST */ |
---|
| 877 | uint32_t adx = (uint32_t)d_addr |
---|
[861d315] | 878 | & ~L2C_310_DATA_LINE_MASK; |
---|
[92e2757] | 879 | const uint32_t ADDR_LAST = |
---|
| 880 | (uint32_t)( (size_t)d_addr + n_bytes - 1 ); |
---|
| 881 | uint32_t block_end = |
---|
[861d315] | 882 | L2C_310_MIN( ADDR_LAST, adx + L2C_310_MAX_LOCKING_BYTES ); |
---|
[a9d6c20] | 883 | volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; |
---|
[92e2757] | 884 | |
---|
[42fe0d3] | 885 | if ( n_bytes == 0 ) { |
---|
| 886 | return; |
---|
| 887 | } |
---|
| 888 | |
---|
[92e2757] | 889 | for (; |
---|
| 890 | adx <= ADDR_LAST; |
---|
| 891 | adx = block_end + 1, |
---|
[861d315] | 892 | block_end = L2C_310_MIN( ADDR_LAST, adx + L2C_310_MAX_LOCKING_BYTES )) { |
---|
[d1eb7b1] | 893 | rtems_interrupt_lock_context lock_context; |
---|
| 894 | |
---|
| 895 | rtems_interrupt_lock_acquire( &l2c_310_lock, &lock_context ); |
---|
| 896 | |
---|
[92e2757] | 897 | for (; adx <= block_end; adx += CPU_DATA_CACHE_ALIGNMENT ) { |
---|
[e492e7f8] | 898 | l2c_310_flush_1_line( l2cc, adx ); |
---|
[92e2757] | 899 | } |
---|
[d1eb7b1] | 900 | |
---|
| 901 | l2c_310_sync( l2cc ); |
---|
| 902 | |
---|
| 903 | rtems_interrupt_lock_release( &l2c_310_lock, &lock_context ); |
---|
[9fcd1b35] | 904 | } |
---|
| 905 | } |
---|
| 906 | |
---|
| 907 | static inline void |
---|
[d53de34] | 908 | l2c_310_flush_entire( void ) |
---|
[9fcd1b35] | 909 | { |
---|
[957c075] | 910 | volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; |
---|
[1c62f74d] | 911 | rtems_interrupt_lock_context lock_context; |
---|
[9fcd1b35] | 912 | |
---|
| 913 | /* Only flush if level 2 cache is active */ |
---|
[55741886] | 914 | if( ( l2cc->ctrl & L2C_310_CTRL_ENABLE ) != 0 ) { |
---|
[9fcd1b35] | 915 | |
---|
| 916 | /* ensure ordering with previous memory accesses */ |
---|
| 917 | _ARM_Data_memory_barrier(); |
---|
| 918 | |
---|
[d53de34] | 919 | rtems_interrupt_lock_acquire( &l2c_310_lock, &lock_context ); |
---|
[861d315] | 920 | l2cc->clean_inv_way = L2C_310_WAY_MASK; |
---|
[9fcd1b35] | 921 | |
---|
[861d315] | 922 | while ( l2cc->clean_inv_way & L2C_310_WAY_MASK ) {}; |
---|
[9fcd1b35] | 923 | |
---|
| 924 | /* Wait for the flush to complete */ |
---|
[52d24b00] | 925 | l2c_310_sync( l2cc ); |
---|
[1c62f74d] | 926 | |
---|
[d53de34] | 927 | rtems_interrupt_lock_release( &l2c_310_lock, &lock_context ); |
---|
[9fcd1b35] | 928 | } |
---|
| 929 | } |
---|
| 930 | |
---|
| 931 | static inline void |
---|
[d53de34] | 932 | l2c_310_invalidate_1_line( const void *d_addr ) |
---|
[9fcd1b35] | 933 | { |
---|
[957c075] | 934 | volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; |
---|
[9fcd1b35] | 935 | |
---|
| 936 | |
---|
| 937 | l2cc->inv_pa = (uint32_t) d_addr; |
---|
[52d24b00] | 938 | l2c_310_sync( l2cc ); |
---|
[9fcd1b35] | 939 | } |
---|
| 940 | |
---|
| 941 | static inline void |
---|
[d1eb7b1] | 942 | l2c_310_invalidate_range( const void* d_addr, const size_t n_bytes ) |
---|
[9fcd1b35] | 943 | { |
---|
[d1eb7b1] | 944 | /* Back starting address up to start of a line and invalidate until ADDR_LAST */ |
---|
| 945 | uint32_t adx = (uint32_t)d_addr |
---|
| 946 | & ~L2C_310_DATA_LINE_MASK; |
---|
| 947 | const uint32_t ADDR_LAST = |
---|
| 948 | (uint32_t)( (size_t)d_addr + n_bytes - 1 ); |
---|
| 949 | uint32_t block_end = |
---|
| 950 | L2C_310_MIN( ADDR_LAST, adx + L2C_310_MAX_LOCKING_BYTES ); |
---|
| 951 | volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; |
---|
[9fcd1b35] | 952 | |
---|
[42fe0d3] | 953 | if ( n_bytes == 0 ) { |
---|
| 954 | return; |
---|
| 955 | } |
---|
| 956 | |
---|
[db5a84d] | 957 | for (; |
---|
[d1eb7b1] | 958 | adx <= ADDR_LAST; |
---|
| 959 | adx = block_end + 1, |
---|
| 960 | block_end = L2C_310_MIN( ADDR_LAST, adx + L2C_310_MAX_LOCKING_BYTES )) { |
---|
| 961 | rtems_interrupt_lock_context lock_context; |
---|
| 962 | |
---|
| 963 | rtems_interrupt_lock_acquire( &l2c_310_lock, &lock_context ); |
---|
| 964 | |
---|
| 965 | for (; adx <= block_end; adx += CPU_DATA_CACHE_ALIGNMENT ) { |
---|
| 966 | /* Invalidate L2 cache line */ |
---|
| 967 | l2cc->inv_pa = adx; |
---|
| 968 | } |
---|
| 969 | |
---|
| 970 | l2c_310_sync( l2cc ); |
---|
| 971 | |
---|
| 972 | rtems_interrupt_lock_release( &l2c_310_lock, &lock_context ); |
---|
[db5a84d] | 973 | } |
---|
[9fcd1b35] | 974 | } |
---|
| 975 | |
---|
[d1eb7b1] | 976 | |
---|
[9fcd1b35] | 977 | static inline void |
---|
[d53de34] | 978 | l2c_310_invalidate_entire( void ) |
---|
[9fcd1b35] | 979 | { |
---|
[957c075] | 980 | volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; |
---|
[9fcd1b35] | 981 | |
---|
| 982 | /* Invalidate the caches */ |
---|
| 983 | |
---|
| 984 | /* ensure ordering with previous memory accesses */ |
---|
| 985 | _ARM_Data_memory_barrier(); |
---|
| 986 | |
---|
[861d315] | 987 | l2cc->inv_way = L2C_310_WAY_MASK; |
---|
[9fcd1b35] | 988 | |
---|
[861d315] | 989 | while ( l2cc->inv_way & L2C_310_WAY_MASK ) ; |
---|
[9fcd1b35] | 990 | |
---|
| 991 | /* Wait for the invalidate to complete */ |
---|
[52d24b00] | 992 | l2c_310_sync( l2cc ); |
---|
[9fcd1b35] | 993 | } |
---|
| 994 | |
---|
| 995 | static inline void |
---|
[d53de34] | 996 | l2c_310_clean_and_invalidate_entire( void ) |
---|
[9fcd1b35] | 997 | { |
---|
[957c075] | 998 | volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; |
---|
[1c62f74d] | 999 | rtems_interrupt_lock_context lock_context; |
---|
[9fcd1b35] | 1000 | |
---|
[55741886] | 1001 | if( ( l2cc->ctrl & L2C_310_CTRL_ENABLE ) != 0 ) { |
---|
[9fcd1b35] | 1002 | /* Invalidate the caches */ |
---|
| 1003 | |
---|
| 1004 | /* ensure ordering with previous memory accesses */ |
---|
| 1005 | _ARM_Data_memory_barrier(); |
---|
| 1006 | |
---|
[d53de34] | 1007 | rtems_interrupt_lock_acquire( &l2c_310_lock, &lock_context ); |
---|
[861d315] | 1008 | l2cc->clean_inv_way = L2C_310_WAY_MASK; |
---|
[9fcd1b35] | 1009 | |
---|
[861d315] | 1010 | while ( l2cc->clean_inv_way & L2C_310_WAY_MASK ) ; |
---|
[9fcd1b35] | 1011 | |
---|
| 1012 | /* Wait for the invalidate to complete */ |
---|
[52d24b00] | 1013 | l2c_310_sync( l2cc ); |
---|
[1c62f74d] | 1014 | |
---|
[d53de34] | 1015 | rtems_interrupt_lock_release( &l2c_310_lock, &lock_context ); |
---|
[9fcd1b35] | 1016 | } |
---|
| 1017 | } |
---|
| 1018 | |
---|
| 1019 | static inline void |
---|
[d53de34] | 1020 | l2c_310_freeze( void ) |
---|
[9fcd1b35] | 1021 | { |
---|
| 1022 | /* To be implemented as needed, if supported |
---|
| 1023 | by hardware at all */ |
---|
| 1024 | } |
---|
| 1025 | |
---|
| 1026 | static inline void |
---|
[d53de34] | 1027 | l2c_310_unfreeze( void ) |
---|
[9fcd1b35] | 1028 | { |
---|
| 1029 | /* To be implemented as needed, if supported |
---|
| 1030 | by hardware at all */ |
---|
| 1031 | } |
---|
| 1032 | |
---|
[62fa1ea] | 1033 | static inline size_t |
---|
[d53de34] | 1034 | l2c_310_get_cache_size( void ) |
---|
[62fa1ea] | 1035 | { |
---|
| 1036 | size_t size = 0; |
---|
[957c075] | 1037 | volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; |
---|
[62fa1ea] | 1038 | uint32_t cache_type = l2cc->cache_type; |
---|
| 1039 | uint32_t way_size; |
---|
| 1040 | uint32_t num_ways; |
---|
[a9d6c20] | 1041 | |
---|
[861d315] | 1042 | way_size = (cache_type & L2C_310_TYPE_SIZE_D_WAYS_MASK) |
---|
| 1043 | >> L2C_310_TYPE_SIZE_D_WAYS_SHIFT; |
---|
| 1044 | num_ways = (cache_type & L2C_310_TYPE_NUM_D_WAYS_MASK) |
---|
| 1045 | >> L2C_310_TYPE_NUM_D_WAYS_SHIFT; |
---|
[62fa1ea] | 1046 | |
---|
| 1047 | assert( way_size <= 0x07 ); |
---|
| 1048 | assert( num_ways <= 0x01 ); |
---|
| 1049 | if( way_size <= 0x07 && num_ways <= 0x01 ) { |
---|
| 1050 | if( way_size == 0x00 ) { |
---|
| 1051 | way_size = 16 * 1024; |
---|
| 1052 | } else if( way_size == 0x07 ) { |
---|
| 1053 | way_size = 512 * 1024; |
---|
| 1054 | } else { |
---|
| 1055 | way_size = (1 << (way_size - 1)) * 16 * 1024; |
---|
| 1056 | } |
---|
| 1057 | switch( num_ways ) { |
---|
| 1058 | case 0: |
---|
| 1059 | num_ways = 8; |
---|
| 1060 | break; |
---|
| 1061 | case 1: |
---|
| 1062 | num_ways = 16; |
---|
| 1063 | break; |
---|
| 1064 | default: |
---|
| 1065 | num_ways = 0; |
---|
| 1066 | break; |
---|
| 1067 | } |
---|
| 1068 | size = way_size * num_ways; |
---|
| 1069 | } |
---|
| 1070 | return size; |
---|
| 1071 | } |
---|
| 1072 | |
---|
[d53de34] | 1073 | static void l2c_310_unlock( volatile L2CC *l2cc ) |
---|
[9fcd1b35] | 1074 | { |
---|
| 1075 | l2cc->d_lockdown_0 = 0; |
---|
| 1076 | l2cc->i_lockdown_0 = 0; |
---|
| 1077 | l2cc->d_lockdown_1 = 0; |
---|
| 1078 | l2cc->i_lockdown_1 = 0; |
---|
| 1079 | l2cc->d_lockdown_2 = 0; |
---|
| 1080 | l2cc->i_lockdown_2 = 0; |
---|
| 1081 | l2cc->d_lockdown_3 = 0; |
---|
| 1082 | l2cc->i_lockdown_3 = 0; |
---|
| 1083 | l2cc->d_lockdown_4 = 0; |
---|
| 1084 | l2cc->i_lockdown_4 = 0; |
---|
| 1085 | l2cc->d_lockdown_5 = 0; |
---|
| 1086 | l2cc->i_lockdown_5 = 0; |
---|
| 1087 | l2cc->d_lockdown_6 = 0; |
---|
| 1088 | l2cc->i_lockdown_6 = 0; |
---|
| 1089 | l2cc->d_lockdown_7 = 0; |
---|
| 1090 | l2cc->i_lockdown_7 = 0; |
---|
| 1091 | } |
---|
| 1092 | |
---|
[d53de34] | 1093 | static void l2c_310_wait_for_background_ops( volatile L2CC *l2cc ) |
---|
[f2fed0c1] | 1094 | { |
---|
[861d315] | 1095 | while ( l2cc->inv_way & L2C_310_WAY_MASK ) ; |
---|
[f2fed0c1] | 1096 | |
---|
[861d315] | 1097 | while ( l2cc->clean_way & L2C_310_WAY_MASK ) ; |
---|
[f2fed0c1] | 1098 | |
---|
[861d315] | 1099 | while ( l2cc->clean_inv_way & L2C_310_WAY_MASK ) ; |
---|
[f2fed0c1] | 1100 | } |
---|
| 1101 | |
---|
| 1102 | /* We support only the L2C-310 revisions r3p2 and r3p3 cache controller */ |
---|
| 1103 | |
---|
[861d315] | 1104 | #if (BSP_ARM_L2C_310_ID & L2C_310_ID_PART_MASK) \ |
---|
| 1105 | != L2C_310_ID_PART_L310 |
---|
[f2fed0c1] | 1106 | #error "invalid L2-310 cache controller part number" |
---|
| 1107 | #endif |
---|
| 1108 | |
---|
[52d24b00] | 1109 | #if (BSP_ARM_L2C_310_RTL_RELEASE != L2C_310_RTL_RELEASE_R3_P2) \ |
---|
| 1110 | && (BSP_ARM_L2C_310_RTL_RELEASE != L2C_310_RTL_RELEASE_R3_P3) |
---|
[f2fed0c1] | 1111 | #error "invalid L2-310 cache controller RTL revision" |
---|
| 1112 | #endif |
---|
| 1113 | |
---|
[9fcd1b35] | 1114 | static inline void |
---|
[d53de34] | 1115 | l2c_310_enable( void ) |
---|
[9fcd1b35] | 1116 | { |
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[957c075] | 1117 | volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; |
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[f2fed0c1] | 1118 | uint32_t cache_id = l2cc->cache_id; |
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[52d24b00] | 1119 | uint32_t rtl_release = cache_id & L2C_310_ID_RTL_MASK; |
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| 1120 | uint32_t id_mask = L2C_310_ID_IMPL_MASK | L2C_310_ID_PART_MASK; |
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[55741886] | 1121 | uint32_t ctrl; |
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[f2fed0c1] | 1122 | |
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| 1123 | /* |
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| 1124 | * Do we actually have an L2C-310 cache controller? Has BSP_ARM_L2C_310_BASE |
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| 1125 | * been configured correctly? |
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| 1126 | */ |
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| 1127 | if ( |
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| 1128 | (BSP_ARM_L2C_310_ID & id_mask) != (cache_id & id_mask) |
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[52d24b00] | 1129 | || rtl_release < BSP_ARM_L2C_310_RTL_RELEASE |
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[f2fed0c1] | 1130 | ) { |
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| 1131 | bsp_fatal( ARM_FATAL_L2C_310_UNEXPECTED_ID ); |
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| 1132 | } |
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| 1133 | |
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[d53de34] | 1134 | l2c_310_check_errata( rtl_release ); |
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[a9d6c20] | 1135 | |
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[55741886] | 1136 | ctrl = l2cc->ctrl; |
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| 1137 | |
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| 1138 | if ( ( ctrl & L2C_310_CTRL_EXCL_CONFIG ) != 0 ) { |
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| 1139 | bsp_fatal( ARM_FATAL_L2C_310_EXCLUSIVE_CONFIG ); |
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| 1140 | } |
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| 1141 | |
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[127634c] | 1142 | /* Only enable if L2CC is currently disabled */ |
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[55741886] | 1143 | if( ( ctrl & L2C_310_CTRL_ENABLE ) == 0 ) { |
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[f2fed0c1] | 1144 | uint32_t aux_ctrl; |
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| 1145 | int ways; |
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[9fcd1b35] | 1146 | |
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[f2fed0c1] | 1147 | /* Make sure that I&D is not locked down when starting */ |
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[d53de34] | 1148 | l2c_310_unlock( l2cc ); |
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[9fcd1b35] | 1149 | |
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[d53de34] | 1150 | l2c_310_wait_for_background_ops( l2cc ); |
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[9fcd1b35] | 1151 | |
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[f2fed0c1] | 1152 | aux_ctrl = l2cc->aux_ctrl; |
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[9fcd1b35] | 1153 | |
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[f2fed0c1] | 1154 | if ( (aux_ctrl & ( 1 << 16 )) != 0 ) { |
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| 1155 | ways = 16; |
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| 1156 | } else { |
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| 1157 | ways = 8; |
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| 1158 | } |
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[9fcd1b35] | 1159 | |
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[861d315] | 1160 | if ( ways != L2C_310_NUM_WAYS ) { |
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[f2fed0c1] | 1161 | bsp_fatal( ARM_FATAL_L2C_310_UNEXPECTED_NUM_WAYS ); |
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| 1162 | } |
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[9fcd1b35] | 1163 | |
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[f2fed0c1] | 1164 | /* Set up the way size */ |
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[861d315] | 1165 | aux_ctrl &= L2C_310_AUX_REG_ZERO_MASK; /* Set way_size to 0 */ |
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| 1166 | aux_ctrl |= L2C_310_AUX_REG_DEFAULT_MASK; |
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[9fcd1b35] | 1167 | |
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[f2fed0c1] | 1168 | l2cc->aux_ctrl = aux_ctrl; |
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[9fcd1b35] | 1169 | |
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[f2fed0c1] | 1170 | /* Set up the latencies */ |
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[861d315] | 1171 | l2cc->tag_ram_ctrl = L2C_310_TAG_RAM_DEFAULT_LAT; |
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| 1172 | l2cc->data_ram_ctrl = L2C_310_DATA_RAM_DEFAULT_MASK; |
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[9fcd1b35] | 1173 | |
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[d53de34] | 1174 | l2c_310_invalidate_entire(); |
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[9fcd1b35] | 1175 | |
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[f2fed0c1] | 1176 | /* Clear the pending interrupts */ |
---|
| 1177 | l2cc->int_clr = l2cc->int_raw_status; |
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[9fcd1b35] | 1178 | |
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[f2fed0c1] | 1179 | /* Enable the L2CC */ |
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[55741886] | 1180 | l2cc->ctrl = ctrl | L2C_310_CTRL_ENABLE; |
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[9fcd1b35] | 1181 | } |
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| 1182 | } |
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| 1183 | |
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[a9d6c20] | 1184 | static inline void |
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[d53de34] | 1185 | l2c_310_disable( void ) |
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[9fcd1b35] | 1186 | { |
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[957c075] | 1187 | volatile L2CC *l2cc = (volatile L2CC *) BSP_ARM_L2C_310_BASE; |
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[1c62f74d] | 1188 | rtems_interrupt_lock_context lock_context; |
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[9fcd1b35] | 1189 | |
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[55741886] | 1190 | if ( l2cc->ctrl & L2C_310_CTRL_ENABLE ) { |
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[9fcd1b35] | 1191 | /* Clean and Invalidate L2 Cache */ |
---|
[d53de34] | 1192 | l2c_310_flush_entire(); |
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| 1193 | rtems_interrupt_lock_acquire( &l2c_310_lock, &lock_context ); |
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[9fcd1b35] | 1194 | |
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[d53de34] | 1195 | l2c_310_wait_for_background_ops( l2cc ); |
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[9fcd1b35] | 1196 | |
---|
| 1197 | /* Disable the L2 cache */ |
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[55741886] | 1198 | l2cc->ctrl &= ~L2C_310_CTRL_ENABLE; |
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[d53de34] | 1199 | rtems_interrupt_lock_release( &l2c_310_lock, &lock_context ); |
---|
[9fcd1b35] | 1200 | } |
---|
| 1201 | } |
---|
| 1202 | |
---|
[a9d6c20] | 1203 | static inline void |
---|
[9fcd1b35] | 1204 | _CPU_cache_enable_data( void ) |
---|
| 1205 | { |
---|
[d53de34] | 1206 | l2c_310_enable(); |
---|
[9fcd1b35] | 1207 | } |
---|
| 1208 | |
---|
[a9d6c20] | 1209 | static inline void |
---|
[9fcd1b35] | 1210 | _CPU_cache_disable_data( void ) |
---|
| 1211 | { |
---|
| 1212 | arm_cache_l1_disable_data(); |
---|
[d53de34] | 1213 | l2c_310_disable(); |
---|
[9fcd1b35] | 1214 | } |
---|
| 1215 | |
---|
[a9d6c20] | 1216 | static inline void |
---|
[9fcd1b35] | 1217 | _CPU_cache_enable_instruction( void ) |
---|
| 1218 | { |
---|
[d53de34] | 1219 | l2c_310_enable(); |
---|
[9fcd1b35] | 1220 | } |
---|
| 1221 | |
---|
[a9d6c20] | 1222 | static inline void |
---|
[9fcd1b35] | 1223 | _CPU_cache_disable_instruction( void ) |
---|
| 1224 | { |
---|
| 1225 | arm_cache_l1_disable_instruction(); |
---|
[d53de34] | 1226 | l2c_310_disable(); |
---|
[9fcd1b35] | 1227 | } |
---|
| 1228 | |
---|
[a9d6c20] | 1229 | static inline void |
---|
[9fcd1b35] | 1230 | _CPU_cache_flush_data_range( |
---|
| 1231 | const void *d_addr, |
---|
| 1232 | size_t n_bytes |
---|
| 1233 | ) |
---|
| 1234 | { |
---|
[d1eb7b1] | 1235 | arm_cache_l1_flush_data_range( |
---|
| 1236 | d_addr, |
---|
| 1237 | n_bytes |
---|
| 1238 | ); |
---|
| 1239 | l2c_310_flush_range( |
---|
| 1240 | d_addr, |
---|
| 1241 | n_bytes |
---|
| 1242 | ); |
---|
[9fcd1b35] | 1243 | } |
---|
| 1244 | |
---|
[a9d6c20] | 1245 | static inline void |
---|
[9fcd1b35] | 1246 | _CPU_cache_flush_entire_data( void ) |
---|
| 1247 | { |
---|
| 1248 | arm_cache_l1_flush_entire_data(); |
---|
[d53de34] | 1249 | l2c_310_flush_entire(); |
---|
[9fcd1b35] | 1250 | } |
---|
| 1251 | |
---|
[a9d6c20] | 1252 | static inline void |
---|
| 1253 | _CPU_cache_invalidate_data_range( |
---|
[9fcd1b35] | 1254 | const void *addr_first, |
---|
[a9d6c20] | 1255 | size_t n_bytes |
---|
[9fcd1b35] | 1256 | ) |
---|
| 1257 | { |
---|
[d1eb7b1] | 1258 | l2c_310_invalidate_range( |
---|
| 1259 | addr_first, |
---|
| 1260 | n_bytes |
---|
| 1261 | ); |
---|
| 1262 | arm_cache_l1_invalidate_data_range( |
---|
| 1263 | addr_first, |
---|
| 1264 | n_bytes |
---|
| 1265 | ); |
---|
[9fcd1b35] | 1266 | } |
---|
| 1267 | |
---|
[a9d6c20] | 1268 | static inline void |
---|
[9fcd1b35] | 1269 | _CPU_cache_invalidate_entire_data( void ) |
---|
| 1270 | { |
---|
| 1271 | /* This is broadcast within the cluster */ |
---|
| 1272 | arm_cache_l1_flush_entire_data(); |
---|
| 1273 | |
---|
| 1274 | /* forces the address out past level 2 */ |
---|
[d53de34] | 1275 | l2c_310_clean_and_invalidate_entire(); |
---|
[9fcd1b35] | 1276 | |
---|
| 1277 | /*This is broadcast within the cluster */ |
---|
| 1278 | arm_cache_l1_clean_and_invalidate_entire_data(); |
---|
| 1279 | } |
---|
| 1280 | |
---|
[a9d6c20] | 1281 | static inline void |
---|
[9fcd1b35] | 1282 | _CPU_cache_freeze_data( void ) |
---|
| 1283 | { |
---|
| 1284 | arm_cache_l1_freeze_data(); |
---|
[d53de34] | 1285 | l2c_310_freeze(); |
---|
[9fcd1b35] | 1286 | } |
---|
| 1287 | |
---|
[a9d6c20] | 1288 | static inline void |
---|
[9fcd1b35] | 1289 | _CPU_cache_unfreeze_data( void ) |
---|
| 1290 | { |
---|
| 1291 | arm_cache_l1_unfreeze_data(); |
---|
[d53de34] | 1292 | l2c_310_unfreeze(); |
---|
[9fcd1b35] | 1293 | } |
---|
| 1294 | |
---|
[a9d6c20] | 1295 | static inline void |
---|
[4768ae0f] | 1296 | _CPU_cache_invalidate_instruction_range( const void *i_addr, size_t n_bytes) |
---|
[9fcd1b35] | 1297 | { |
---|
[4768ae0f] | 1298 | arm_cache_l1_invalidate_instruction_range( i_addr, n_bytes ); |
---|
[9fcd1b35] | 1299 | } |
---|
| 1300 | |
---|
[a9d6c20] | 1301 | static inline void |
---|
[9fcd1b35] | 1302 | _CPU_cache_invalidate_entire_instruction( void ) |
---|
| 1303 | { |
---|
| 1304 | arm_cache_l1_invalidate_entire_instruction(); |
---|
| 1305 | } |
---|
| 1306 | |
---|
[a9d6c20] | 1307 | static inline void |
---|
[9fcd1b35] | 1308 | _CPU_cache_freeze_instruction( void ) |
---|
| 1309 | { |
---|
| 1310 | arm_cache_l1_freeze_instruction(); |
---|
[d53de34] | 1311 | l2c_310_freeze(); |
---|
[9fcd1b35] | 1312 | } |
---|
| 1313 | |
---|
[a9d6c20] | 1314 | static inline void |
---|
[9fcd1b35] | 1315 | _CPU_cache_unfreeze_instruction( void ) |
---|
| 1316 | { |
---|
| 1317 | arm_cache_l1_unfreeze_instruction(); |
---|
[d53de34] | 1318 | l2c_310_unfreeze(); |
---|
[9fcd1b35] | 1319 | } |
---|
| 1320 | |
---|
[62fa1ea] | 1321 | static inline size_t |
---|
| 1322 | _CPU_cache_get_data_cache_size( const uint32_t level ) |
---|
| 1323 | { |
---|
| 1324 | size_t size = 0; |
---|
[a9d6c20] | 1325 | |
---|
[62fa1ea] | 1326 | switch( level ) |
---|
| 1327 | { |
---|
[12ab8d6] | 1328 | case 1: |
---|
[62fa1ea] | 1329 | size = arm_cache_l1_get_data_cache_size(); |
---|
| 1330 | break; |
---|
[12ab8d6] | 1331 | case 0: |
---|
| 1332 | case 2: |
---|
[d53de34] | 1333 | size = l2c_310_get_cache_size(); |
---|
[62fa1ea] | 1334 | break; |
---|
| 1335 | default: |
---|
| 1336 | size = 0; |
---|
| 1337 | break; |
---|
| 1338 | } |
---|
| 1339 | return size; |
---|
| 1340 | } |
---|
| 1341 | |
---|
| 1342 | static inline size_t |
---|
| 1343 | _CPU_cache_get_instruction_cache_size( const uint32_t level ) |
---|
| 1344 | { |
---|
| 1345 | size_t size = 0; |
---|
[a9d6c20] | 1346 | |
---|
[62fa1ea] | 1347 | switch( level ) |
---|
| 1348 | { |
---|
[12ab8d6] | 1349 | case 1: |
---|
[62fa1ea] | 1350 | size = arm_cache_l1_get_instruction_cache_size(); |
---|
| 1351 | break; |
---|
[12ab8d6] | 1352 | case 0: |
---|
| 1353 | case 2: |
---|
[d53de34] | 1354 | size = l2c_310_get_cache_size(); |
---|
[62fa1ea] | 1355 | break; |
---|
| 1356 | default: |
---|
| 1357 | size = 0; |
---|
| 1358 | break; |
---|
| 1359 | } |
---|
| 1360 | return size; |
---|
| 1361 | } |
---|
| 1362 | |
---|
| 1363 | |
---|
[9fcd1b35] | 1364 | /** @} */ |
---|
| 1365 | |
---|
| 1366 | #ifdef __cplusplus |
---|
| 1367 | } |
---|
| 1368 | #endif /* __cplusplus */ |
---|
| 1369 | |
---|
[40599e7e] | 1370 | #endif /* LIBBSP_ARM_SHARED_L2C_310_CACHE_H */ |
---|