[a91dc98b] | 1 | /* |
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| 2 | * Copyright (c) 2013 embedded brains GmbH. All rights reserved. |
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| 3 | * |
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| 4 | * embedded brains GmbH |
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| 5 | * Dornierstr. 4 |
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| 6 | * 82178 Puchheim |
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| 7 | * Germany |
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| 8 | * <info@embedded-brains.de> |
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| 9 | * |
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| 10 | * The license and distribution terms for this file may be |
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| 11 | * found in the file LICENSE in this distribution or at |
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| 12 | * http://www.rtems.com/license/LICENSE. |
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| 13 | */ |
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| 14 | |
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| 15 | #include <bsp/arm-gic.h> |
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| 16 | |
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| 17 | #include <rtems/score/armv4.h> |
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| 18 | |
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| 19 | #include <libcpu/arm-cp15.h> |
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| 20 | |
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| 21 | #include <bsp/irq.h> |
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| 22 | #include <bsp/irq-generic.h> |
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[db42c079] | 23 | #include <bsp/start.h> |
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[a91dc98b] | 24 | |
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| 25 | #define GIC_CPUIF ((volatile gic_cpuif *) BSP_ARM_GIC_CPUIF_BASE) |
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| 26 | |
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| 27 | #define PRIORITY_DEFAULT 128 |
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| 28 | |
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| 29 | void bsp_interrupt_dispatch(void) |
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| 30 | { |
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| 31 | volatile gic_cpuif *cpuif = GIC_CPUIF; |
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| 32 | uint32_t icciar = cpuif->icciar; |
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| 33 | rtems_vector_number vector = GIC_CPUIF_ICCIAR_ACKINTID_GET(icciar); |
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| 34 | rtems_vector_number spurious = 1023; |
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| 35 | |
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| 36 | if (vector != spurious) { |
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| 37 | uint32_t psr = _ARMV4_Status_irq_enable(); |
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| 38 | |
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| 39 | bsp_interrupt_handler_dispatch(vector); |
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| 40 | |
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| 41 | _ARMV4_Status_restore(psr); |
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| 42 | |
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| 43 | cpuif->icceoir = icciar; |
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| 44 | } |
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| 45 | } |
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| 46 | |
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| 47 | rtems_status_code bsp_interrupt_vector_enable(rtems_vector_number vector) |
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| 48 | { |
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| 49 | rtems_status_code sc = RTEMS_SUCCESSFUL; |
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| 50 | |
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| 51 | if (bsp_interrupt_is_valid_vector(vector)) { |
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[db42c079] | 52 | volatile gic_dist *dist = ARM_GIC_DIST; |
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[a91dc98b] | 53 | |
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| 54 | gic_id_enable(dist, vector); |
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| 55 | } else { |
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| 56 | sc = RTEMS_INVALID_ID; |
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| 57 | } |
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| 58 | |
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| 59 | return sc; |
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| 60 | } |
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| 61 | |
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| 62 | rtems_status_code bsp_interrupt_vector_disable(rtems_vector_number vector) |
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| 63 | { |
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| 64 | rtems_status_code sc = RTEMS_SUCCESSFUL; |
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| 65 | |
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| 66 | if (bsp_interrupt_is_valid_vector(vector)) { |
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[db42c079] | 67 | volatile gic_dist *dist = ARM_GIC_DIST; |
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[a91dc98b] | 68 | |
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| 69 | gic_id_disable(dist, vector); |
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| 70 | } else { |
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| 71 | sc = RTEMS_INVALID_ID; |
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| 72 | } |
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| 73 | |
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| 74 | return sc; |
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| 75 | } |
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| 76 | |
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| 77 | static inline uint32_t get_id_count(volatile gic_dist *dist) |
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| 78 | { |
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| 79 | uint32_t id_count = GIC_DIST_ICDICTR_IT_LINES_NUMBER_GET(dist->icdictr); |
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| 80 | |
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| 81 | id_count = 32 * (id_count + 1); |
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| 82 | id_count = id_count <= 1020 ? id_count : 1020; |
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| 83 | |
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| 84 | return id_count; |
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| 85 | } |
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| 86 | |
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| 87 | rtems_status_code bsp_interrupt_facility_initialize(void) |
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| 88 | { |
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| 89 | volatile gic_cpuif *cpuif = GIC_CPUIF; |
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[db42c079] | 90 | volatile gic_dist *dist = ARM_GIC_DIST; |
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[a91dc98b] | 91 | uint32_t id_count = get_id_count(dist); |
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| 92 | uint32_t id; |
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| 93 | |
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[db42c079] | 94 | arm_cp15_set_exception_handler( |
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| 95 | ARM_EXCEPTION_IRQ, |
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| 96 | _ARMV4_Exception_interrupt |
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| 97 | ); |
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| 98 | |
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[a91dc98b] | 99 | for (id = 0; id < id_count; ++id) { |
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| 100 | gic_id_set_priority(dist, id, PRIORITY_DEFAULT); |
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| 101 | } |
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| 102 | |
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| 103 | for (id = 32; id < id_count; ++id) { |
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| 104 | gic_id_set_targets(dist, id, 0x01); |
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| 105 | } |
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| 106 | |
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| 107 | cpuif->iccpmr = GIC_CPUIF_ICCPMR_PRIORITY(0xff); |
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| 108 | cpuif->iccbpr = GIC_CPUIF_ICCBPR_BINARY_POINT(0x0); |
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| 109 | cpuif->iccicr = GIC_CPUIF_ICCICR_ENABLE; |
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| 110 | |
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| 111 | dist->icddcr = GIC_DIST_ICDDCR_ENABLE; |
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| 112 | |
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| 113 | return RTEMS_SUCCESSFUL; |
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| 114 | } |
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| 115 | |
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[db42c079] | 116 | #ifdef RTEMS_SMP |
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| 117 | BSP_START_TEXT_SECTION void arm_gic_irq_initialize_secondary_cpu(void) |
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| 118 | { |
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| 119 | volatile gic_cpuif *cpuif = GIC_CPUIF; |
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| 120 | volatile gic_dist *dist = ARM_GIC_DIST; |
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| 121 | |
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| 122 | while ((dist->icddcr & GIC_DIST_ICDDCR_ENABLE) == 0) { |
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| 123 | /* Wait */ |
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| 124 | } |
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| 125 | |
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| 126 | cpuif->iccpmr = GIC_CPUIF_ICCPMR_PRIORITY(0xff); |
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| 127 | cpuif->iccbpr = GIC_CPUIF_ICCBPR_BINARY_POINT(0x0); |
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| 128 | cpuif->iccicr = GIC_CPUIF_ICCICR_ENABLE; |
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| 129 | } |
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| 130 | #endif |
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| 131 | |
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[a91dc98b] | 132 | rtems_status_code arm_gic_irq_set_priority( |
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| 133 | rtems_vector_number vector, |
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| 134 | uint8_t priority |
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| 135 | ) |
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| 136 | { |
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| 137 | rtems_status_code sc = RTEMS_SUCCESSFUL; |
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| 138 | |
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| 139 | if (bsp_interrupt_is_valid_vector(vector)) { |
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[db42c079] | 140 | volatile gic_dist *dist = ARM_GIC_DIST; |
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[a91dc98b] | 141 | |
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| 142 | gic_id_set_priority(dist, vector, priority); |
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| 143 | } else { |
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| 144 | sc = RTEMS_INVALID_ID; |
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| 145 | } |
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| 146 | |
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| 147 | return sc; |
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| 148 | } |
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| 149 | |
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| 150 | rtems_status_code arm_gic_irq_get_priority( |
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| 151 | rtems_vector_number vector, |
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| 152 | uint8_t *priority |
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| 153 | ) |
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| 154 | { |
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| 155 | rtems_status_code sc = RTEMS_SUCCESSFUL; |
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| 156 | |
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| 157 | if (bsp_interrupt_is_valid_vector(vector)) { |
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[db42c079] | 158 | volatile gic_dist *dist = ARM_GIC_DIST; |
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[a91dc98b] | 159 | |
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| 160 | *priority = gic_id_get_priority(dist, vector); |
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| 161 | } else { |
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| 162 | sc = RTEMS_INVALID_ID; |
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| 163 | } |
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| 164 | |
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| 165 | return sc; |
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| 166 | } |
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