1 | /* |
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2 | * Copyright (c) 2010-2013 embedded brains GmbH. All rights reserved. |
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3 | * |
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4 | * embedded brains GmbH |
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5 | * Obere Lagerstr. 30 |
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6 | * 82178 Puchheim |
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7 | * Germany |
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8 | * <rtems@embedded-brains.de> |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.rtems.org/license/LICENSE. |
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13 | */ |
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14 | |
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15 | #include <rtems.h> |
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16 | #include <libcpu/arm-cp15.h> |
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17 | |
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18 | /* |
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19 | * Translation table modification requires to propagate |
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20 | * information to memory and other cores. |
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21 | * |
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22 | * Algorithm follows example found in the section |
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23 | * |
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24 | * B3.10.1 General TLB maintenance requirements |
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25 | * TLB maintenance operations and the memory order model |
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26 | * |
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27 | * of ARM Architecture Reference Manual |
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28 | * ARMv7-A and ARMv7-R edition |
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29 | * ARM DDI 0406C.b (ID072512) |
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30 | */ |
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31 | |
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32 | static uint32_t set_translation_table_entries( |
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33 | const void *begin, |
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34 | const void *end, |
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35 | uint32_t section_flags |
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36 | ) |
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37 | { |
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38 | uint32_t *ttb = arm_cp15_get_translation_table_base(); |
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39 | uint32_t istart = ARM_MMU_SECT_GET_INDEX(begin); |
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40 | uint32_t iend = ARM_MMU_SECT_GET_INDEX(ARM_MMU_SECT_MVA_ALIGN_UP(end)); |
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41 | uint32_t index_mask = (1U << (32 - ARM_MMU_SECT_BASE_SHIFT)) - 1U; |
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42 | uint32_t ctrl; |
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43 | uint32_t section_flags_of_first_entry; |
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44 | uint32_t i; |
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45 | void *first_ttb_addr; |
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46 | void *last_ttb_end; |
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47 | |
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48 | ctrl = arm_cp15_get_control(); |
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49 | section_flags_of_first_entry = ttb [istart]; |
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50 | last_ttb_end = first_ttb_addr = ttb + istart; |
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51 | |
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52 | for ( i = istart; i != iend; i = (i + 1U) & index_mask ) { |
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53 | uint32_t addr = i << ARM_MMU_SECT_BASE_SHIFT; |
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54 | |
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55 | ttb [i] = addr | section_flags; |
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56 | last_ttb_end = ttb + i + 1; |
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57 | } |
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58 | |
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59 | if ( ctrl & (ARM_CP15_CTRL_C | ARM_CP15_CTRL_M ) ) { |
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60 | rtems_cache_flush_multiple_data_lines(first_ttb_addr, |
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61 | last_ttb_end - first_ttb_addr); |
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62 | } |
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63 | |
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64 | _ARM_Data_synchronization_barrier(); |
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65 | |
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66 | for ( i = istart; i != iend; i = (i + 1U) & index_mask ) { |
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67 | void *mva = (void *) (i << ARM_MMU_SECT_BASE_SHIFT); |
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68 | #if defined(__ARM_ARCH_7A__) |
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69 | arm_cp15_tlb_invalidate_entry_all_asids(mva); |
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70 | #else |
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71 | arm_cp15_tlb_instruction_invalidate_entry(mva); |
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72 | arm_cp15_tlb_data_invalidate_entry(mva); |
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73 | #endif |
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74 | } |
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75 | |
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76 | _ARM_Data_synchronization_barrier(); |
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77 | _ARM_Instruction_synchronization_barrier(); |
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78 | |
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79 | return section_flags_of_first_entry; |
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80 | } |
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81 | |
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82 | uint32_t arm_cp15_set_translation_table_entries( |
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83 | const void *begin, |
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84 | const void *end, |
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85 | uint32_t section_flags |
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86 | ) |
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87 | { |
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88 | return set_translation_table_entries(begin, end, section_flags); |
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89 | } |
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