1 | /* |
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2 | * Copyright (c) 2013 embedded brains GmbH. All rights reserved. |
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3 | * |
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4 | * embedded brains GmbH |
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5 | * Dornierstr. 4 |
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6 | * 82178 Puchheim |
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7 | * Germany |
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8 | * <info@embedded-brains.de> |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.rtems.org/license/LICENSE. |
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13 | */ |
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14 | |
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15 | #include <assert.h> |
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16 | |
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17 | #include <rtems/score/smpimpl.h> |
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18 | |
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19 | #include <libcpu/arm-cp15.h> |
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20 | |
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21 | #include <bsp/irq.h> |
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22 | #include <bsp/linker-symbols.h> |
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23 | |
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24 | static void bsp_inter_processor_interrupt(void *arg) |
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25 | { |
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26 | _SMP_Inter_processor_interrupt_handler(); |
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27 | } |
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28 | |
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29 | uint32_t _CPU_SMP_Initialize(void) |
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30 | { |
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31 | uint32_t hardware_count = arm_gic_irq_processor_count(); |
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32 | uint32_t linker_count = (uint32_t) bsp_processor_count; |
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33 | |
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34 | return hardware_count <= linker_count ? hardware_count : linker_count; |
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35 | } |
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36 | |
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37 | void _CPU_SMP_Finalize_initialization(uint32_t cpu_count) |
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38 | { |
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39 | if (cpu_count > 0) { |
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40 | rtems_status_code sc; |
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41 | |
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42 | sc = rtems_interrupt_handler_install( |
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43 | ARM_GIC_IRQ_SGI_0, |
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44 | "IPI", |
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45 | RTEMS_INTERRUPT_UNIQUE, |
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46 | bsp_inter_processor_interrupt, |
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47 | NULL |
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48 | ); |
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49 | assert(sc == RTEMS_SUCCESSFUL); |
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50 | |
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51 | #if defined(BSP_DATA_CACHE_ENABLED) || defined(BSP_INSTRUCTION_CACHE_ENABLED) |
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52 | /* Enable unified L2 cache */ |
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53 | rtems_cache_enable_data(); |
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54 | #endif |
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55 | } |
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56 | } |
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57 | |
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58 | void _CPU_SMP_Prepare_start_multitasking( void ) |
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59 | { |
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60 | /* Do nothing */ |
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61 | } |
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62 | |
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63 | void _CPU_SMP_Send_interrupt( uint32_t target_processor_index ) |
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64 | { |
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65 | arm_gic_irq_generate_software_irq( |
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66 | ARM_GIC_IRQ_SGI_0, |
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67 | ARM_GIC_IRQ_SOFTWARE_IRQ_TO_ALL_IN_LIST, |
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68 | (uint8_t) (1U << target_processor_index) |
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69 | ); |
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70 | } |
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