1 | /* |
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2 | * Copyright (c) 2013-2014 embedded brains GmbH. All rights reserved. |
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3 | * |
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4 | * embedded brains GmbH |
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5 | * Dornierstr. 4 |
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6 | * 82178 Puchheim |
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7 | * Germany |
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8 | * <info@embedded-brains.de> |
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9 | * |
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10 | * The license and distribution terms for this file may be |
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11 | * found in the file LICENSE in this distribution or at |
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12 | * http://www.rtems.org/license/LICENSE. |
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13 | */ |
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14 | |
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15 | #include <rtems/counter.h> |
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16 | |
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17 | #include <bsp.h> |
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18 | #include <bsp/fatal.h> |
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19 | #include <bsp/irq.h> |
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20 | #include <bsp/arm-a9mpcore-regs.h> |
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21 | #include <bsp/arm-a9mpcore-clock.h> |
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22 | |
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23 | #define A9MPCORE_GT ((volatile a9mpcore_gt *) BSP_ARM_A9MPCORE_GT_BASE) |
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24 | |
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25 | static uint64_t a9mpcore_clock_last_tick_k; |
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26 | |
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27 | /* This is defined in clockdrv_shell.h */ |
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28 | void Clock_isr(rtems_irq_hdl_param arg); |
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29 | |
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30 | __attribute__ ((weak)) uint32_t a9mpcore_clock_periphclk(void) |
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31 | { |
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32 | /* default to the BSP option. */ |
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33 | return BSP_ARM_A9MPCORE_PERIPHCLK; |
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34 | } |
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35 | |
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36 | static void a9mpcore_clock_at_tick(void) |
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37 | { |
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38 | volatile a9mpcore_gt *gt = A9MPCORE_GT; |
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39 | |
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40 | gt->irqst = A9MPCORE_GT_IRQST_EFLG; |
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41 | } |
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42 | |
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43 | static void a9mpcore_clock_handler_install(void) |
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44 | { |
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45 | rtems_status_code sc; |
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46 | |
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47 | sc = rtems_interrupt_handler_install( |
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48 | A9MPCORE_IRQ_GT, |
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49 | "Clock", |
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50 | RTEMS_INTERRUPT_UNIQUE, |
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51 | (rtems_interrupt_handler) Clock_isr, |
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52 | NULL |
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53 | ); |
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54 | if (sc != RTEMS_SUCCESSFUL) { |
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55 | bsp_fatal(BSP_ARM_A9MPCORE_FATAL_CLOCK_IRQ_INSTALL); |
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56 | } |
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57 | } |
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58 | |
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59 | static uint64_t a9mpcore_clock_get_counter(volatile a9mpcore_gt *gt) |
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60 | { |
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61 | uint32_t cl; |
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62 | uint32_t cu1; |
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63 | uint32_t cu2; |
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64 | |
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65 | do { |
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66 | cu1 = gt->cntrupper; |
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67 | cl = gt->cntrlower; |
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68 | cu2 = gt->cntrupper; |
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69 | } while (cu1 != cu2); |
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70 | |
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71 | return ((uint64_t) cu2 << 32) | cl; |
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72 | } |
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73 | |
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74 | static void a9mpcore_clock_initialize(void) |
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75 | { |
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76 | volatile a9mpcore_gt *gt = A9MPCORE_GT; |
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77 | uint64_t periphclk = a9mpcore_clock_periphclk(); |
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78 | uint64_t us_per_tick = rtems_configuration_get_microseconds_per_tick(); |
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79 | uint32_t interval = (uint32_t) ((periphclk * us_per_tick) / 1000000); |
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80 | uint64_t cmpval; |
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81 | |
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82 | a9mpcore_clock_last_tick_k = (UINT64_C(1000000000) << 32) / periphclk; |
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83 | |
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84 | gt->ctrl &= A9MPCORE_GT_CTRL_TMR_EN; |
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85 | gt->irqst = A9MPCORE_GT_IRQST_EFLG; |
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86 | |
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87 | cmpval = a9mpcore_clock_get_counter(gt); |
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88 | cmpval += interval; |
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89 | |
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90 | gt->cmpvallower = (uint32_t) cmpval; |
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91 | gt->cmpvalupper = (uint32_t) (cmpval >> 32); |
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92 | gt->autoinc = interval; |
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93 | gt->ctrl = A9MPCORE_GT_CTRL_AUTOINC_EN |
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94 | | A9MPCORE_GT_CTRL_IRQ_EN |
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95 | | A9MPCORE_GT_CTRL_COMP_EN |
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96 | | A9MPCORE_GT_CTRL_TMR_EN; |
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97 | |
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98 | rtems_counter_initialize_converter((uint32_t) periphclk); |
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99 | } |
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100 | |
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101 | CPU_Counter_ticks _CPU_Counter_read(void) |
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102 | { |
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103 | volatile a9mpcore_gt *gt = A9MPCORE_GT; |
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104 | |
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105 | return gt->cntrlower; |
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106 | } |
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107 | |
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108 | static void a9mpcore_clock_cleanup_isr(void *arg) |
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109 | { |
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110 | volatile a9mpcore_gt *gt = A9MPCORE_GT; |
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111 | |
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112 | (void) arg; |
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113 | |
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114 | gt->ctrl &= A9MPCORE_GT_CTRL_TMR_EN; |
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115 | gt->irqst = A9MPCORE_GT_IRQST_EFLG; |
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116 | } |
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117 | |
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118 | static void a9mpcore_clock_cleanup(void) |
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119 | { |
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120 | rtems_status_code sc; |
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121 | |
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122 | /* |
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123 | * The relevant registers / bits of the global timer are banked and chances |
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124 | * are on an SPM system, that we are executing on the wrong CPU to reset |
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125 | * them. Thus we will have the actual cleanup done with the next clock tick. |
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126 | * The ISR will execute on the right CPU for the cleanup. |
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127 | */ |
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128 | sc = rtems_interrupt_handler_install( |
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129 | A9MPCORE_IRQ_GT, |
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130 | "Clock", |
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131 | RTEMS_INTERRUPT_REPLACE, |
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132 | a9mpcore_clock_cleanup_isr, |
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133 | NULL |
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134 | ); |
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135 | if (sc != RTEMS_SUCCESSFUL) { |
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136 | bsp_fatal(BSP_ARM_A9MPCORE_FATAL_CLOCK_IRQ_REMOVE); |
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137 | } |
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138 | } |
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139 | |
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140 | static uint32_t a9mpcore_clock_nanoseconds_since_last_tick(void) |
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141 | { |
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142 | volatile a9mpcore_gt *gt = A9MPCORE_GT; |
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143 | uint64_t k = a9mpcore_clock_last_tick_k; |
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144 | uint32_t c = gt->cntrlower; |
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145 | uint32_t n = gt->cmpvallower; |
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146 | uint32_t i = gt->autoinc; |
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147 | |
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148 | if ((gt->irqst & A9MPCORE_GT_IRQST_EFLG) != 0) { |
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149 | n = gt->cmpvallower - i; |
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150 | } |
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151 | |
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152 | return (uint32_t) (((c - n + i) * k) >> 32); |
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153 | } |
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154 | |
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155 | #define Clock_driver_support_at_tick() \ |
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156 | a9mpcore_clock_at_tick() |
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157 | |
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158 | #define Clock_driver_support_initialize_hardware() \ |
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159 | a9mpcore_clock_initialize() |
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160 | |
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161 | #define Clock_driver_support_install_isr(isr, old_isr) \ |
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162 | do { \ |
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163 | a9mpcore_clock_handler_install(); \ |
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164 | old_isr = NULL; \ |
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165 | } while (0) |
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166 | |
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167 | #define Clock_driver_support_shutdown_hardware() \ |
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168 | a9mpcore_clock_cleanup() |
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169 | |
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170 | #define Clock_driver_nanoseconds_since_last_tick \ |
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171 | a9mpcore_clock_nanoseconds_since_last_tick |
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172 | |
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173 | /* Include shared source clock driver code */ |
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174 | #include "../../shared/clockdrv_shell.h" |
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