source: rtems/c/src/lib/libbsp/arm/shared/arm-a9mpcore-clock-config.c @ c19342a7

4.115
Last change on this file since c19342a7 was c19342a7, checked in by Sebastian Huber <sebastian.huber@…>, on Jun 5, 2014 at 2:19:21 PM

bsps/arm: Fix Cortex-A9 MPCore clock driver

The nanoseconds extension returned wrong values on secondary processors
since some of the global timer registeres are banked. Use global
variables instead.

  • Property mode set to 100644
File size: 4.5 KB
Line 
1/*
2 * Copyright (c) 2013-2014 embedded brains GmbH.  All rights reserved.
3 *
4 *  embedded brains GmbH
5 *  Dornierstr. 4
6 *  82178 Puchheim
7 *  Germany
8 *  <info@embedded-brains.de>
9 *
10 * The license and distribution terms for this file may be
11 * found in the file LICENSE in this distribution or at
12 * http://www.rtems.org/license/LICENSE.
13 */
14
15#include <rtems/counter.h>
16
17#include <bsp.h>
18#include <bsp/fatal.h>
19#include <bsp/irq.h>
20#include <bsp/arm-a9mpcore-regs.h>
21#include <bsp/arm-a9mpcore-clock.h>
22
23#define A9MPCORE_GT ((volatile a9mpcore_gt *) BSP_ARM_A9MPCORE_GT_BASE)
24
25static uint64_t a9mpcore_clock_last_tick_k;
26
27static uint32_t a9mpcore_clock_last_tick_cmpvallower;
28
29static uint32_t a9mpcore_clock_autoinc;
30
31/* This is defined in clockdrv_shell.h */
32void Clock_isr(rtems_irq_hdl_param arg);
33
34__attribute__ ((weak)) uint32_t a9mpcore_clock_periphclk(void)
35{
36  /* default to the BSP option. */
37  return BSP_ARM_A9MPCORE_PERIPHCLK;
38}
39
40static void a9mpcore_clock_at_tick(void)
41{
42  volatile a9mpcore_gt *gt = A9MPCORE_GT;
43
44  /*
45   * FIXME: Now the _TOD_Get_with_nanoseconds() yields wrong values until
46   * _TOD_Tickle_ticks() managed to update the uptime.  See also PR2180.
47   */
48  a9mpcore_clock_last_tick_cmpvallower =
49    gt->cmpvallower - a9mpcore_clock_autoinc;
50
51  gt->irqst = A9MPCORE_GT_IRQST_EFLG;
52}
53
54static void a9mpcore_clock_handler_install(void)
55{
56  rtems_status_code sc;
57
58  sc = rtems_interrupt_handler_install(
59    A9MPCORE_IRQ_GT,
60    "Clock",
61    RTEMS_INTERRUPT_UNIQUE,
62    (rtems_interrupt_handler) Clock_isr,
63    NULL
64  );
65  if (sc != RTEMS_SUCCESSFUL) {
66    bsp_fatal(BSP_ARM_A9MPCORE_FATAL_CLOCK_IRQ_INSTALL);
67  }
68}
69
70static uint64_t a9mpcore_clock_get_counter(volatile a9mpcore_gt *gt)
71{
72  uint32_t cl;
73  uint32_t cu1;
74  uint32_t cu2;
75
76  do {
77    cu1 = gt->cntrupper;
78    cl = gt->cntrlower;
79    cu2 = gt->cntrupper;
80  } while (cu1 != cu2);
81
82  return ((uint64_t) cu2 << 32) | cl;
83}
84
85static void a9mpcore_clock_initialize(void)
86{
87  volatile a9mpcore_gt *gt = A9MPCORE_GT;
88  uint64_t periphclk = a9mpcore_clock_periphclk();
89  uint64_t us_per_tick = rtems_configuration_get_microseconds_per_tick();
90  uint32_t interval = (uint32_t) ((periphclk * us_per_tick) / 1000000);
91  uint64_t cmpval;
92
93  gt->ctrl &= A9MPCORE_GT_CTRL_TMR_EN;
94  gt->irqst = A9MPCORE_GT_IRQST_EFLG;
95
96  cmpval = a9mpcore_clock_get_counter(gt);
97  cmpval += interval;
98
99  gt->cmpvallower = (uint32_t) cmpval;
100  gt->cmpvalupper = (uint32_t) (cmpval >> 32);
101  gt->autoinc = interval;
102
103  a9mpcore_clock_last_tick_k = (UINT64_C(1000000000) << 32) / periphclk;
104  a9mpcore_clock_last_tick_cmpvallower = (uint32_t) cmpval - interval;
105  a9mpcore_clock_autoinc = interval;
106
107  gt->ctrl = A9MPCORE_GT_CTRL_AUTOINC_EN
108    | A9MPCORE_GT_CTRL_IRQ_EN
109    | A9MPCORE_GT_CTRL_COMP_EN
110    | A9MPCORE_GT_CTRL_TMR_EN;
111
112  rtems_counter_initialize_converter((uint32_t) periphclk);
113}
114
115CPU_Counter_ticks _CPU_Counter_read(void)
116{
117  volatile a9mpcore_gt *gt = A9MPCORE_GT;
118
119  return gt->cntrlower;
120}
121
122static void a9mpcore_clock_cleanup_isr(void *arg)
123{
124  volatile a9mpcore_gt *gt = A9MPCORE_GT;
125
126  (void) arg;
127
128  gt->ctrl &= A9MPCORE_GT_CTRL_TMR_EN;
129  gt->irqst = A9MPCORE_GT_IRQST_EFLG;
130}
131
132static void a9mpcore_clock_cleanup(void)
133{
134  rtems_status_code sc;
135
136  /*
137   * The relevant registers / bits of the global timer are banked and chances
138   * are on an SPM system, that we are executing on the wrong CPU to reset
139   * them. Thus we will have the actual cleanup done with the next clock tick.
140   * The ISR will execute on the right CPU for the cleanup.
141   */
142  sc = rtems_interrupt_handler_install(
143    A9MPCORE_IRQ_GT,
144    "Clock",
145    RTEMS_INTERRUPT_REPLACE,
146    a9mpcore_clock_cleanup_isr,
147    NULL
148  );
149  if (sc != RTEMS_SUCCESSFUL) {
150    bsp_fatal(BSP_ARM_A9MPCORE_FATAL_CLOCK_IRQ_REMOVE);
151  }
152}
153
154static uint32_t a9mpcore_clock_nanoseconds_since_last_tick(void)
155{
156  volatile a9mpcore_gt *gt = A9MPCORE_GT;
157  uint64_t k = a9mpcore_clock_last_tick_k;
158  uint32_t n = a9mpcore_clock_last_tick_cmpvallower;
159  uint32_t c = gt->cntrlower;
160
161  return (uint32_t) (((c - n) * k) >> 32);
162}
163
164#define Clock_driver_support_at_tick() \
165  a9mpcore_clock_at_tick()
166
167#define Clock_driver_support_initialize_hardware() \
168  a9mpcore_clock_initialize()
169
170#define Clock_driver_support_install_isr(isr, old_isr) \
171  do { \
172    a9mpcore_clock_handler_install();   \
173    old_isr = NULL; \
174  } while (0)
175
176#define Clock_driver_support_shutdown_hardware() \
177  a9mpcore_clock_cleanup()
178
179#define Clock_driver_nanoseconds_since_last_tick \
180  a9mpcore_clock_nanoseconds_since_last_tick
181
182/* Include shared source clock driver code */
183#include "../../shared/clockdrv_shell.h"
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